pub const SKYLAKE_CORE: Map<&'static str, IntelPerformanceCounterDescription> = ::phf::Map{key: 1897749892740154578,
disps:
::phf::Slice::Static(&[(0, 8), (0, 0), (0, 619), (0, 705),
(0, 3), (0, 123), (0, 16), (0, 399),
(0, 73), (0, 30), (1, 98), (0, 53),
(0, 358), (0, 165), (0, 4), (1, 0),
(0, 6), (0, 3), (0, 492), (2, 82),
(0, 7), (0, 2), (0, 0), (0, 82),
(0, 15), (0, 20), (0, 379), (0, 8),
(0, 3), (0, 51), (0, 44), (0, 5),
(0, 0), (3, 391), (0, 15), (0, 200),
(0, 421), (2, 559), (0, 0), (0, 3),
(0, 17), (2, 423), (2, 470), (0, 100),
(0, 1), (0, 4), (0, 39), (0, 349),
(0, 36), (3, 252), (0, 0), (0, 6),
(0, 17), (2, 128), (0, 254), (0, 23),
(0, 218), (14, 149), (1, 480), (0, 131),
(14, 372), (0, 35), (0, 0), (0, 39),
(1, 34), (0, 15), (0, 85), (0, 669),
(0, 3), (0, 123), (0, 13), (0, 146),
(0, 59), (0, 38), (0, 39), (0, 324),
(0, 662), (7, 291), (2, 44), (0, 334),
(0, 234), (0, 211), (0, 1), (3, 28),
(0, 24), (1, 572), (0, 0), (0, 25),
(8, 519), (0, 165), (0, 92), (0, 0),
(0, 204), (0, 0), (0, 1), (0, 67),
(1, 487), (0, 14), (0, 60), (0, 204),
(0, 35), (0, 290), (0, 3), (0, 237),
(0, 85), (0, 515), (3, 566), (0, 84),
(8, 325), (18, 305), (22, 57), (0, 67),
(0, 507), (0, 8), (0, 4), (1, 0),
(0, 6), (0, 17), (0, 478), (0, 192),
(12, 69), (0, 0), (0, 512), (4, 252),
(11, 519), (112, 147), (1, 110),
(68, 178), (2, 420), (0, 7), (1, 73),
(10, 272), (0, 1), (0, 1), (81, 233),
(2, 16), (0, 128), (0, 8), (0, 19),
(1, 130), (0, 12), (0, 335)]),
entries:
::phf::Slice::Static(&[("IDQ.MITE_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(121),
umask:
Tuple::One(4),
event_name:
"IDQ.MITE_CYCLES",
brief_description:
"Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_M.SNOOP_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_M.SNOOP_HITM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
68719740928,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NON_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NON_DRAM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
138445619200,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
4362078208,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.SNOOP_HIT_NO_FWD",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.SNOOP_HIT_NO_FWD",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
17180131584,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
273871276032,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("CPU_CLK_UNHALTED.THREAD_ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(0),
umask:
Tuple::One(2),
event_name:
"CPU_CLK_UNHALTED.THREAD_ANY",
brief_description:
"Core cycles when at least one thread on the physical core is not in halt state",
public_description:
None,
counter:
Counter::Fixed(4),
counter_ht_off:
Counter::Fixed(4),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
true,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
IntelPerformanceCounterDescription{event_code:
Tuple::One(8),
umask:
Tuple::One(1),
event_name:
"DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
brief_description:
"Load misses in all DTLB levels that cause page walks",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_LOAD_RETIRED.L1_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(209),
umask:
Tuple::One(8),
event_name:
"MEM_LOAD_RETIRED.L1_MISS",
brief_description:
"Retired load instructions missed L1 cache as data sources",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
true,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_MISS",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
8590983170,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("FP_ASSIST.ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(202),
umask:
Tuple::One(30),
event_name:
"FP_ASSIST.ANY",
brief_description:
"Cycles with any input/output SSE or FP assist",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.SUPPLIER_NONE.SNOOP_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.SUPPLIER_NONE.SNOOP_MISS",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
8590067712,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_HITM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
69726142464,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
273805213700,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
17180000260,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.SNOOP_NON_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.SNOOP_NON_DRAM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
137440002176,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOP",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOP",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
273805213824,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_NOT_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_NOT_NEEDED",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
4296015874,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
2149318784,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("DSB2MITE_SWITCHES.PENALTY_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(171),
umask:
Tuple::One(2),
event_name:
"DSB2MITE_SWITCHES.PENALTY_CYCLES",
brief_description:
"Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_REQUESTS.ALL_DATA_RD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(176),
umask:
Tuple::One(8),
event_name:
"OFFCORE_REQUESTS.ALL_DATA_RD",
brief_description:
"Demand and prefetch data reads",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS.SNOOP_HIT_NO_FWD",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS.SNOOP_HIT_NO_FWD",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
18186504192,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.L4_HIT_LOCAL_L4.SNOOP_NONE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.L4_HIT_LOCAL_L4.SNOOP_NONE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
2151680000,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("TX_MEM.HLE_ELISION_BUFFER_FULL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(84),
umask:
Tuple::One(64),
event_name:
"TX_MEM.HLE_ELISION_BUFFER_FULL",
brief_description:
"Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
4299161604,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
17246978049,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("FRONTEND_RETIRED.L2_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(198),
umask:
Tuple::One(1),
event_name:
"FRONTEND_RETIRED.L2_MISS",
brief_description:
"Retired Instructions who experienced Instruction L2 Cache true miss.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100007,
msr_index:
MSRIndex::One(247),
msr_value:
19,
taken_alone:
true,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NOT_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NOT_NEEDED",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
4295229444,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_LOAD_RETIRED.L3_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(209),
umask:
Tuple::One(4),
event_name:
"MEM_LOAD_RETIRED.L3_HIT",
brief_description:
"Retired load instructions with L3 cache hits as data sources",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
50021,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
true,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
68786585601,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("DTLB_LOAD_MISSES.STLB_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(8),
umask:
Tuple::One(32),
event_name:
"DTLB_LOAD_MISSES.STLB_HIT",
brief_description:
"Loads that miss the DTLB and hit the STLB.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("HLE_RETIRED.COMMIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(200),
umask:
Tuple::One(2),
event_name:
"HLE_RETIRED.COMMIT",
brief_description:
"Number of times an HLE execution successfully committed",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_REQUESTS.DEMAND_DATA_RD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(176),
umask:
Tuple::One(1),
event_name:
"OFFCORE_REQUESTS.DEMAND_DATA_RD",
brief_description:
"Demand Data Read requests sent to uncore",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_DISPATCHED_PORT.PORT_4",
IntelPerformanceCounterDescription{event_code:
Tuple::One(161),
umask:
Tuple::One(16),
event_name:
"UOPS_DISPATCHED_PORT.PORT_4",
brief_description:
"Cycles per thread when uops are executed in port 4",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("CYCLE_ACTIVITY.CYCLES_MEM_ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(163),
umask:
Tuple::One(16),
event_name:
"CYCLE_ACTIVITY.CYCLES_MEM_ANY",
brief_description:
"Cycles while memory subsystem has an outstanding load.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
16,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.SNOOP_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.SNOOP_MISS",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
8590459008,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("HLE_RETIRED.ABORTED",
IntelPerformanceCounterDescription{event_code:
Tuple::One(200),
umask:
Tuple::One(4),
event_name:
"HLE_RETIRED.ABORTED",
brief_description:
"Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
IntelPerformanceCounterDescription{event_code:
Tuple::One(205),
umask:
Tuple::One(1),
event_name:
"MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
brief_description:
"Counts loads when the latency from first dispatch to completion is greater than 4 cycles.",
public_description:
Some("Counts loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::One(246),
msr_value:
4,
taken_alone:
true,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOnly,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_DISPATCHED_PORT.PORT_3",
IntelPerformanceCounterDescription{event_code:
Tuple::One(161),
umask:
Tuple::One(8),
event_name:
"UOPS_DISPATCHED_PORT.PORT_3",
brief_description:
"Cycles per thread when uops are executed in port 3",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
9596567680,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_NOT_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_NOT_NEEDED",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
4295229442,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("IDQ.MS_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(121),
umask:
Tuple::One(48),
event_name:
"IDQ.MS_CYCLES",
brief_description:
"Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("CYCLE_ACTIVITY.STALLS_MEM_ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(163),
umask:
Tuple::One(20),
event_name:
"CYCLE_ACTIVITY.STALLS_MEM_ANY",
brief_description:
"Execution stalls while memory subsystem has an outstanding load.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
20,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.SNOOP_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.SNOOP_MISS",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
8590459136,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC",
IntelPerformanceCounterDescription{event_code:
Tuple::One(177),
umask:
Tuple::One(1),
event_name:
"UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC",
brief_description:
"Cycles where at least 1 uop was executed per-thread",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NOT_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NOT_NEEDED",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
4295098624,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
137443147780,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NON_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NON_DRAM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
137439477764,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("FRONTEND_RETIRED.LATENCY_GE_8",
IntelPerformanceCounterDescription{event_code:
Tuple::One(198),
umask:
Tuple::One(1),
event_name:
"FRONTEND_RETIRED.LATENCY_GE_8",
brief_description:
"Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100007,
msr_index:
MSRIndex::One(247),
msr_value:
4196358,
taken_alone:
true,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NONE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NONE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
2147745793,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_EXECUTED.CORE_CYCLES_NONE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(177),
umask:
Tuple::One(2),
event_name:
"UOPS_EXECUTED.CORE_CYCLES_NONE",
brief_description:
"Cycles with no micro-ops executed from any thread on physical core",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
true,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD",
brief_description:
"Counts all demand code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
17181704196,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_DISPATCHED_PORT.PORT_7",
IntelPerformanceCounterDescription{event_code:
Tuple::One(161),
umask:
Tuple::One(128),
event_name:
"UOPS_DISPATCHED_PORT.PORT_7",
brief_description:
"Cycles per thread when uops are executed in port 7",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.SNOOP_HIT_NO_FWD",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.SNOOP_HIT_NO_FWD",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
17180131456,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_RQSTS.CODE_RD_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(36),
umask:
Tuple::One(36),
event_name:
"L2_RQSTS.CODE_RD_MISS",
brief_description:
"L2 cache misses when fetching instructions",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_MISS",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
8590065666,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("IDQ.DSB_UOPS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(121),
umask:
Tuple::One(8),
event_name:
"IDQ.DSB_UOPS",
brief_description:
"Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
IntelPerformanceCounterDescription{event_code:
Tuple::One(205),
umask:
Tuple::One(1),
event_name:
"MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
brief_description:
"Counts loads when the latency from first dispatch to completion is greater than 128 cycles.",
public_description:
Some("Counts loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
1009,
msr_index:
MSRIndex::One(246),
msr_value:
128,
taken_alone:
true,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOnly,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("FRONTEND_RETIRED.STLB_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(198),
umask:
Tuple::One(1),
event_name:
"FRONTEND_RETIRED.STLB_MISS",
brief_description:
"Retired Instructions who experienced STLB (2nd level TLB) true miss.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100007,
msr_index:
MSRIndex::One(247),
msr_value:
21,
taken_alone:
true,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("IDQ.DSB_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(121),
umask:
Tuple::One(8),
event_name:
"IDQ.DSB_CYCLES",
brief_description:
"Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("CPU_CLK_UNHALTED.THREAD_P_ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(60),
umask:
Tuple::One(0),
event_name:
"CPU_CLK_UNHALTED.THREAD_P_ANY",
brief_description:
"Core cycles when at least one thread on the physical core is not in halt state",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
true,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("IDQ.ALL_DSB_CYCLES_4_UOPS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(121),
umask:
Tuple::One(24),
event_name:
"IDQ.ALL_DSB_CYCLES_4_UOPS",
brief_description:
"Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
4,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.ANY_SNOOP",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.ANY_SNOOP",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
273806000130,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_MISP_RETIRED.CONDITIONAL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(197),
umask:
Tuple::One(1),
event_name:
"BR_MISP_RETIRED.CONDITIONAL",
brief_description:
"Mispredicted conditional branch instructions retired.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
400009,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(156),
umask:
Tuple::One(1),
event_name:
"IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",
brief_description:
"Cycles with less than 3 uops delivered by the front end.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_EXECUTED.CORE_CYCLES_GE_2",
IntelPerformanceCounterDescription{event_code:
Tuple::One(177),
umask:
Tuple::One(2),
event_name:
"UOPS_EXECUTED.CORE_CYCLES_GE_2",
brief_description:
"Cycles at least 2 micro-op is executed from any thread on physical core",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
2,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
273804427268,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC",
IntelPerformanceCounterDescription{event_code:
Tuple::One(177),
umask:
Tuple::One(1),
event_name:
"UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC",
brief_description:
"Cycles where at least 4 uops were executed per-thread",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
4,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_E.SPL_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_E.SPL_HIT",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
1074268160,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK",
IntelPerformanceCounterDescription{event_code:
Tuple::One(84),
umask:
Tuple::One(4),
event_name:
"TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK",
brief_description:
"Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.ANY_SNOOP",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.ANY_SNOOP",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
273805213952,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_M.SNOOP_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_M.SNOOP_MISS",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
8590198784,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS",
brief_description:
"Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and the snoops sent to sibling cores return clean response.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
8591769728,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.L4_HIT_LOCAL_L4.ANY_SNOOP",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.L4_HIT_LOCAL_L4.ANY_SNOOP",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
273808359552,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NON_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NON_DRAM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
137439084800,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
2214592516,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_HIT_NO_FWD",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_HIT_NO_FWD",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
17180917762,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
17184063492,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_NONE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_NONE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
3154116736,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_HIT_NO_FWD",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_HIT_NO_FWD",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
17180131329,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SPL_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SPL_HIT",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
1073872897,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SPL_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SPL_HIT",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
1074266114,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("RTM_RETIRED.ABORTED_MEM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(201),
umask:
Tuple::One(8),
event_name:
"RTM_RETIRED.ABORTED_MEM",
brief_description:
"Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NOT_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NOT_NEEDED",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
4296015873,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_ISSUED.VECTOR_WIDTH_MISMATCH",
IntelPerformanceCounterDescription{event_code:
Tuple::One(14),
umask:
Tuple::One(2),
event_name:
"UOPS_ISSUED.VECTOR_WIDTH_MISMATCH",
brief_description:
"Uops inserted at issue-stage in order to preserve upper bits of vector registers.",
public_description:
Some("This event counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register.\r\nFor more information, refer to ?Mixing Intel AVX and Intel SSE Code? section of the Optimization Guide."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SPL_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SPL_HIT",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
1073872898,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
274810798084,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.SNOOP_NOT_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.SNOOP_NOT_NEEDED",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
4295491712,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.SUPPLIER_NONE.ANY_SNOOP",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.SUPPLIER_NONE.ANY_SNOOP",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
273804298240,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_HIT_NO_FWD",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_HIT_NO_FWD",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
17180164096,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_RQSTS.RFO_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(36),
umask:
Tuple::One(66),
event_name:
"L2_RQSTS.RFO_HIT",
brief_description:
"RFO requests that hit L2 cache",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
17246978050,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_NOT_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_NOT_NEEDED",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
4295524352,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.L3_HIT_S.ANY_SNOOP",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.L3_HIT_S.ANY_SNOOP",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
273805246464,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_HITM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
68723671041,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_REQUESTS.DEMAND_RFO",
IntelPerformanceCounterDescription{event_code:
Tuple::One(176),
umask:
Tuple::One(4),
event_name:
"OFFCORE_REQUESTS.DEMAND_RFO",
brief_description:
"Demand RFO requests including regular RFOs, locks, ItoM",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(176),
umask:
Tuple::One(16),
event_name:
"OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD",
brief_description:
"Demand Data Read requests who miss L3 cache",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS.SNOOP_NON_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS.SNOOP_NON_DRAM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
138445588480,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(96),
umask:
Tuple::One(2),
event_name:
"OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD",
brief_description:
"Cycles with offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_RETIRED.RETIRE_SLOTS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(194),
umask:
Tuple::One(2),
event_name:
"UOPS_RETIRED.RETIRE_SLOTS",
brief_description:
"Retirement slots used.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SPL_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SPL_HIT",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
1073905664,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
4299163648,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.ANY_RESPONSE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.ANY_RESPONSE",
brief_description:
"Counts all prefetch (that bring data to LLC only) RFOs that have any response type.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
65792,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("CYCLE_ACTIVITY.CYCLES_L3_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(163),
umask:
Tuple::One(2),
event_name:
"CYCLE_ACTIVITY.CYCLES_L3_MISS",
brief_description:
"Cycles while L3 cache miss demand load is outstanding.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
2,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("RTM_RETIRED.ABORTED_MEMTYPE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(201),
umask:
Tuple::One(64),
event_name:
"RTM_RETIRED.ABORTED_MEMTYPE",
brief_description:
"Number of times an RTM execution aborted due to incompatible memory type",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SPL_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SPL_HIT",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
1073873024,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_HITM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
68720001025,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_RETIRED.TOTAL_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(194),
umask:
Tuple::One(1),
event_name:
"UOPS_RETIRED.TOTAL_CYCLES",
brief_description:
"Cycles with less than 10 actually retired uops.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
10,
invert:
true,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SPL_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SPL_HIT",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
1074790401,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_INST_RETIRED.ALL_LOADS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(208),
umask:
Tuple::One(129),
event_name:
"MEM_INST_RETIRED.ALL_LOADS",
brief_description:
"All retired load instructions.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
true,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
17184065536,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("FRONTEND_RETIRED.LATENCY_GE_16",
IntelPerformanceCounterDescription{event_code:
Tuple::One(198),
umask:
Tuple::One(1),
event_name:
"FRONTEND_RETIRED.LATENCY_GE_16",
brief_description:
"Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100007,
msr_index:
MSRIndex::One(247),
msr_value:
4198406,
taken_alone:
true,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS",
brief_description:
"Counts demand data reads that hit in the L3 and the snoops sent to sibling cores return clean response.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
8591769601,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_RETIRED.STALL_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(194),
umask:
Tuple::One(1),
event_name:
"UOPS_RETIRED.STALL_CYCLES",
brief_description:
"Cycles without actually retired uops.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
true,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NONE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NONE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
2148532225,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_DISPATCHED_PORT.PORT_2",
IntelPerformanceCounterDescription{event_code:
Tuple::One(161),
umask:
Tuple::One(4),
event_name:
"UOPS_DISPATCHED_PORT.PORT_2",
brief_description:
"Cycles per thread when uops are executed in port 2",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_EXECUTED.THREAD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(177),
umask:
Tuple::One(1),
event_name:
"UOPS_EXECUTED.THREAD",
brief_description:
"Counts the number of uops to be executed per-thread each cycle.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(96),
umask:
Tuple::One(2),
event_name:
"OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
brief_description:
"Offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore, every cycle.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_EXECUTED.STALL_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(177),
umask:
Tuple::One(1),
event_name:
"UOPS_EXECUTED.STALL_CYCLES",
brief_description:
"Counts number of cycles no uops were dispatched to be executed on this thread.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
true,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_NON_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_NON_DRAM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
137440002050,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("INT_MISC.RECOVERY_CYCLES_ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(13),
umask:
Tuple::One(1),
event_name:
"INT_MISC.RECOVERY_CYCLES_ANY",
brief_description:
"Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
true,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("IDQ.MS_MITE_UOPS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(121),
umask:
Tuple::One(32),
event_name:
"IDQ.MS_MITE_UOPS",
brief_description:
"Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_HIT_NO_FWD",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_HIT_NO_FWD",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
18186502148,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("EXE_ACTIVITY.2_PORTS_UTIL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(166),
umask:
Tuple::One(4),
event_name:
"EXE_ACTIVITY.2_PORTS_UTIL",
brief_description:
"Cycles total of 2 uops are executed on all ports and Reservation Station was not empty.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_S.SNOOP_NON_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_S.SNOOP_NON_DRAM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
137440004096,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("FRONTEND_RETIRED.LATENCY_GE_2",
IntelPerformanceCounterDescription{event_code:
Tuple::One(198),
umask:
Tuple::One(1),
event_name:
"FRONTEND_RETIRED.LATENCY_GE_2",
brief_description:
"Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 2 cycles which was not interrupted by a back-end stall.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100007,
msr_index:
MSRIndex::One(247),
msr_value:
4194822,
taken_alone:
true,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_LOAD_RETIRED.L1_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(209),
umask:
Tuple::One(1),
event_name:
"MEM_LOAD_RETIRED.L1_HIT",
brief_description:
"Retired load instructions with L1 cache hits as data sources",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
true,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
IntelPerformanceCounterDescription{event_code:
Tuple::One(205),
umask:
Tuple::One(1),
event_name:
"MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
brief_description:
"Counts loads when the latency from first dispatch to completion is greater than 8 cycles.",
public_description:
Some("Counts loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
50021,
msr_index:
MSRIndex::One(246),
msr_value:
8,
taken_alone:
true,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOnly,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_MISS",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
8594128898,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_NONE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_NONE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
2147778560,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SPL_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SPL_HIT",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
1075577088,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SPL_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SPL_HIT",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
2080374912,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.SNOOP_NON_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.SNOOP_NON_DRAM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
137439215872,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.SNOOP_HIT_NO_FWD",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.SNOOP_HIT_NO_FWD",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
17180917888,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_INST_RETIRED.STLB_MISS_STORES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(208),
umask:
Tuple::One(18),
event_name:
"MEM_INST_RETIRED.STLB_MISS_STORES",
brief_description:
"Retired store instructions that miss the STLB.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
true,
l1_hit_indication:
true,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_MISS",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
8590229504,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("RTM_RETIRED.START",
IntelPerformanceCounterDescription{event_code:
Tuple::One(201),
umask:
Tuple::One(1),
event_name:
"RTM_RETIRED.START",
brief_description:
"Number of times an RTM execution started.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SPL_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SPL_HIT",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
1074003969,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_HITM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
68723671168,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.L4_HIT_LOCAL_L4.SPL_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.L4_HIT_LOCAL_L4.SPL_HIT",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
1077936384,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
18186502145,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.SNOOP_NON_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.SNOOP_NON_DRAM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
137439215744,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(96),
umask:
Tuple::One(16),
event_name:
"OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD",
brief_description:
"Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_RQSTS.DEMAND_DATA_RD_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(36),
umask:
Tuple::One(33),
event_name:
"L2_RQSTS.DEMAND_DATA_RD_MISS",
brief_description:
"Demand Data Read miss L2, no rejects",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NON_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NON_DRAM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
137440788484,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.ANY_SNOOP",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.ANY_SNOOP",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
273808359426,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
2214592513,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("DTLB_LOAD_MISSES.WALK_ACTIVE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(8),
umask:
Tuple::One(16),
event_name:
"DTLB_LOAD_MISSES.WALK_ACTIVE",
brief_description:
"Cycles when at least one PMH is busy with a page walk for a load.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
17180000257,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT.SNOOP_NOT_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT.SNOOP_NOT_NEEDED",
brief_description:
"Counts streaming stores that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
4296804352,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_RQSTS.DEMAND_DATA_RD_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(36),
umask:
Tuple::One(65),
event_name:
"L2_RQSTS.DEMAND_DATA_RD_HIT",
brief_description:
"Demand Data Read requests that hit L2 cache",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("IDQ.ALL_MITE_CYCLES_4_UOPS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(121),
umask:
Tuple::One(36),
event_name:
"IDQ.ALL_MITE_CYCLES_4_UOPS",
brief_description:
"Cycles MITE is delivering 4 Uops",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
4,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_MISS",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
9596600320,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.SNOOP_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.SNOOP_HITM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
68720525440,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_REQUESTS.ALL_REQUESTS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(176),
umask:
Tuple::One(128),
event_name:
"OFFCORE_REQUESTS.ALL_REQUESTS",
brief_description:
"Any memory transaction that reached the SQ.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
IntelPerformanceCounterDescription{event_code:
Tuple::One(156),
umask:
Tuple::One(1),
event_name:
"IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
brief_description:
"Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
true,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SPL_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SPL_HIT",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
1140883456,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
8657043460,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NON_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NON_DRAM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
138445586434,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
273871306752,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SPL_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SPL_HIT",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
1073873152,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("LD_BLOCKS.NO_SR",
IntelPerformanceCounterDescription{event_code:
Tuple::One(3),
umask:
Tuple::One(8),
event_name:
"LD_BLOCKS.NO_SR",
brief_description:
"The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_HIT_NO_FWD",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_HIT_NO_FWD",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
17180426240,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SPL_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SPL_HIT",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
1074266113,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NON_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NON_DRAM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
137440002052,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
8657076224,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("EXE_ACTIVITY.EXE_BOUND_0_PORTS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(166),
umask:
Tuple::One(1),
event_name:
"EXE_ACTIVITY.EXE_BOUND_0_PORTS",
brief_description:
"Cycles where no uops were executed, the Reservation Station was not empty, the Store Buffer was full and there was no outstanding load.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
17246980096,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_S.ANY_SNOOP",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_S.ANY_SNOOP",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
273805215744,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
3154116612,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.SUPPLIER_NONE.SPL_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.SUPPLIER_NONE.SPL_HIT",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
1073874944,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_MISS",
brief_description:
"Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and the snoops sent to sibling cores return clean response.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
8591769856,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HIT_NO_FWD",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HIT_NO_FWD",
brief_description:
"Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
17181704448,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NONE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NONE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
2147614976,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
4295098369,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NON_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NON_DRAM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
137439084672,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NONE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NONE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
2147614722,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("MACHINE_CLEARS.SMC",
IntelPerformanceCounterDescription{event_code:
Tuple::One(195),
umask:
Tuple::One(4),
event_name:
"MACHINE_CLEARS.SMC",
brief_description:
"Self-modifying code (SMC) detected.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
5301600257,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
5301600384,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("DTLB_STORE_MISSES.STLB_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(73),
umask:
Tuple::One(32),
event_name:
"DTLB_STORE_MISSES.STLB_HIT",
brief_description:
"Stores that miss the DTLB and hit the STLB.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_NON_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_NON_DRAM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
137439510528,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(199),
umask:
Tuple::One(8),
event_name:
"FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
brief_description:
"Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("TX_EXEC.MISC3",
IntelPerformanceCounterDescription{event_code:
Tuple::One(93),
umask:
Tuple::One(4),
event_name:
"TX_EXEC.MISC3",
brief_description:
"Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("ICACHE_16B.IFDATA_STALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(128),
umask:
Tuple::One(4),
event_name:
"ICACHE_16B.IFDATA_STALL",
brief_description:
"Cycles where a code fetch is stalled due to L1 instruction cache miss.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MACHINE_CLEARS.COUNT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(195),
umask:
Tuple::One(1),
event_name:
"MACHINE_CLEARS.COUNT",
brief_description:
"Number of machine clears (nukes) of any type.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
false,
any_thread:
false,
edge_detect:
true,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_RQSTS.REFERENCES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(36),
umask:
Tuple::One(255),
event_name:
"L2_RQSTS.REFERENCES",
brief_description:
"All L2 requests",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT.SNOOP_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT.SNOOP_MISS",
brief_description:
"Counts streaming stores that hit in the L3 and the snoops sent to sibling cores return clean response.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
8591771648,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("LONGEST_LAT_CACHE.MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(46),
umask:
Tuple::One(65),
event_name:
"LONGEST_LAT_CACHE.MISS",
brief_description:
"Core-originated cacheable demand requests missed L3",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_HITM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
69726109697,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("FRONTEND_RETIRED.ITLB_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(198),
umask:
Tuple::One(1),
event_name:
"FRONTEND_RETIRED.ITLB_MISS",
brief_description:
"Retired Instructions who experienced iTLB true miss.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100007,
msr_index:
MSRIndex::One(247),
msr_value:
20,
taken_alone:
true,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
273871273985,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("FRONTEND_RETIRED.L1I_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(198),
umask:
Tuple::One(1),
event_name:
"FRONTEND_RETIRED.L1I_MISS",
brief_description:
"Retired Instructions who experienced Instruction L1 Cache true miss.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100007,
msr_index:
MSRIndex::One(247),
msr_value:
18,
taken_alone:
true,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
IntelPerformanceCounterDescription{event_code:
Tuple::One(73),
umask:
Tuple::One(1),
event_name:
"DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
brief_description:
"Store misses in all DTLB levels that cause page walks",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_HITM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
68719607936,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.SNOOP_NONE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.SNOOP_NONE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
2148008192,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_DISPATCHED_PORT.PORT_5",
IntelPerformanceCounterDescription{event_code:
Tuple::One(161),
umask:
Tuple::One(32),
event_name:
"UOPS_DISPATCHED_PORT.PORT_5",
brief_description:
"Cycles per thread when uops are executed in port 5",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.L4_HIT_LOCAL_L4.ANY_SNOOP",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.L4_HIT_LOCAL_L4.ANY_SNOOP",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
273808361472,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_MISP_RETIRED.ALL_BRANCHES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(197),
umask:
Tuple::One(0),
event_name:
"BR_MISP_RETIRED.ALL_BRANCHES",
brief_description:
"All mispredicted macro branch instructions retired.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
400009,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
4299194368,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
8657043584,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_GE_6",
IntelPerformanceCounterDescription{event_code:
Tuple::One(96),
umask:
Tuple::One(16),
event_name:
"OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_GE_6",
brief_description:
"Cycles with at least 6 Demand Data Read requests who miss L3 cache in the superQ",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
6,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("TX_EXEC.MISC1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(93),
umask:
Tuple::One(1),
event_name:
"TX_EXEC.MISC1",
brief_description:
"Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("ARITH.DIVIDER_ACTIVE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(20),
umask:
Tuple::One(1),
event_name:
"ARITH.DIVIDER_ACTIVE",
brief_description:
"Cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
false,
any_thread:
false,
edge_detect:
true,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.SPL_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.SPL_HIT",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
1074266240,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
17184063616,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_MISS",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
9596567808,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT.SPL_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT.SPL_HIT",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
1075578880,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_ISSUED.STALL_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(14),
umask:
Tuple::One(1),
event_name:
"UOPS_ISSUED.STALL_CYCLES",
brief_description:
"Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
true,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_INST_RETIRED.ALL_STORES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(208),
umask:
Tuple::One(130),
event_name:
"MEM_INST_RETIRED.ALL_STORES",
brief_description:
"All retired store instructions.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
true,
l1_hit_indication:
true,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.SUPPLIER_NONE.SNOOP_NOT_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.SUPPLIER_NONE.SNOOP_NOT_NEEDED",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
4295100416,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_E.SNOOP_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_E.SNOOP_HITM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
68720003072,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("MACHINE_CLEARS.MEMORY_ORDERING",
IntelPerformanceCounterDescription{event_code:
Tuple::One(195),
umask:
Tuple::One(2),
event_name:
"MACHINE_CLEARS.MEMORY_ORDERING",
brief_description:
"Counts the number of machine clears due to memory order conflicts.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("IDQ.MS_UOPS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(121),
umask:
Tuple::One(48),
event_name:
"IDQ.MS_UOPS",
brief_description:
"Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.SNOOP_NON_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.SNOOP_NON_DRAM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
137440002304,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
273804427265,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
17184063489,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_MISS",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
8590983169,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("HLE_RETIRED.ABORTED_MEM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(200),
umask:
Tuple::One(8),
event_name:
"HLE_RETIRED.ABORTED_MEM",
brief_description:
"Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
273804296196,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS.SPL_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS.SPL_HIT",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
2080376832,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(96),
umask:
Tuple::One(16),
event_name:
"OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD",
brief_description:
"Counts number of Offcore outstanding Demand Data Read requests who miss L3 cache in the superQ every cycle.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("HLE_RETIRED.START",
IntelPerformanceCounterDescription{event_code:
Tuple::One(200),
umask:
Tuple::One(1),
event_name:
"HLE_RETIRED.START",
brief_description:
"Number of times an HLE execution started.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
17246978052,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_NON_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_NON_DRAM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
137439477762,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS.SNOOP_NOT_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS.SNOOP_NOT_NEEDED",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
5301602304,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("RTM_RETIRED.ABORTED_TIMER",
IntelPerformanceCounterDescription{event_code:
Tuple::One(201),
umask:
Tuple::One(16),
event_name:
"RTM_RETIRED.ABORTED_TIMER",
brief_description:
"Number of times an RTM execution aborted due to uncommon conditions.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NOT_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NOT_NEEDED",
brief_description:
"Counts any other requests that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
4296835072,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT.SNOOP_NONE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT.SNOOP_NONE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
2149320704,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("EXE_ACTIVITY.4_PORTS_UTIL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(166),
umask:
Tuple::One(16),
event_name:
"EXE_ACTIVITY.4_PORTS_UTIL",
brief_description:
"Cycles total of 4 uops are executed on all ports and Reservation Station was not empty.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("HLE_RETIRED.ABORTED_MEMTYPE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(200),
umask:
Tuple::One(64),
event_name:
"HLE_RETIRED.ABORTED_MEMTYPE",
brief_description:
"Number of times an HLE execution aborted due to incompatible memory type",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NON_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NON_DRAM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
137439084548,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
2149318660,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_MISS",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
8594161664,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SPL_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SPL_HIT",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
1074266116,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.L3_HIT.ANY_SNOOP",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.L3_HIT.ANY_SNOOP",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
273806032896,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
4362076288,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(210),
umask:
Tuple::One(8),
event_name:
"MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE",
brief_description:
"Retired load instructions which data sources were hits in L3 without snoops required",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
true,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_HITM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
68720033792,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SPL_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SPL_HIT",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
1074790402,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
8590065792,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("ITLB_MISSES.MISS_CAUSES_A_WALK",
IntelPerformanceCounterDescription{event_code:
Tuple::One(133),
umask:
Tuple::One(1),
event_name:
"ITLB_MISSES.MISS_CAUSES_A_WALK",
brief_description:
"Misses at all ITLB levels that cause page walks",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("LOCK_CYCLES.CACHE_LOCK_DURATION",
IntelPerformanceCounterDescription{event_code:
Tuple::One(99),
umask:
Tuple::One(2),
event_name:
"LOCK_CYCLES.CACHE_LOCK_DURATION",
brief_description:
"Cycles when L1D is locked",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_HITM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
69726109698,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
IntelPerformanceCounterDescription{event_code:
Tuple::One(205),
umask:
Tuple::One(1),
event_name:
"MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
brief_description:
"Counts loads when the latency from first dispatch to completion is greater than 256 cycles.",
public_description:
Some("Counts loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
503,
msr_index:
MSRIndex::One(246),
msr_value:
256,
taken_alone:
true,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOnly,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6",
IntelPerformanceCounterDescription{event_code:
Tuple::One(96),
umask:
Tuple::One(1),
event_name:
"OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6",
brief_description:
"Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
6,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_HITM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
68719607809,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NON_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NON_DRAM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
137440821248,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
137443180544,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NONE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NONE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
3154149376,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_MISS",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
8590983172,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.SNOOP_HIT_NO_FWD",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.SNOOP_HIT_NO_FWD",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
17180393600,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_MISS",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
8590458881,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("IDQ.MS_DSB_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(121),
umask:
Tuple::One(16),
event_name:
"IDQ.MS_DSB_CYCLES",
brief_description:
"Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.SPL_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.SPL_HIT",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
1074004224,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NONE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NONE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
2147614724,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.SNOOP_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.SNOOP_MISS",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
8590196864,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SPL_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SPL_HIT",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
1077936132,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.L4_HIT_LOCAL_L4.ANY_SNOOP",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.L4_HIT_LOCAL_L4.ANY_SNOOP",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
273808359680,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED",
brief_description:
"Counts all demand data writes (RFOs) that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
4296802306,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_M.SNOOP_NON_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_M.SNOOP_NON_DRAM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
137439217664,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_RQSTS.ALL_DEMAND_DATA_RD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(36),
umask:
Tuple::One(225),
event_name:
"L2_RQSTS.ALL_DEMAND_DATA_RD",
brief_description:
"Demand Data Read requests",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NOT_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NOT_NEEDED",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
4295131136,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("IDQ.MITE_UOPS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(121),
umask:
Tuple::One(4),
event_name:
"IDQ.MITE_UOPS",
brief_description:
"Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_MISP_RETIRED.ALL_BRANCHES_PEBS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(197),
umask:
Tuple::One(4),
event_name:
"BR_MISP_RETIRED.ALL_BRANCHES_PEBS",
brief_description:
"Mispredicted macro branch instructions retired.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
400009,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOnly,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(199),
umask:
Tuple::One(32),
event_name:
"FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
brief_description:
"Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired. Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_MISP_RETIRED.NEAR_TAKEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(197),
umask:
Tuple::One(32),
event_name:
"BR_MISP_RETIRED.NEAR_TAKEN",
brief_description:
"number of near branch instructions retired that were mispredicted and taken.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
400009,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
273806000129,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.SNOOP_NON_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.SNOOP_NON_DRAM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
137439478016,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS.SNOOP_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS.SNOOP_MISS",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
9596569600,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SPL_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SPL_HIT",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
1075576833,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("FRONTEND_RETIRED.LATENCY_GE_128",
IntelPerformanceCounterDescription{event_code:
Tuple::One(198),
umask:
Tuple::One(1),
event_name:
"FRONTEND_RETIRED.LATENCY_GE_128",
brief_description:
"Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100007,
msr_index:
MSRIndex::One(247),
msr_value:
4227078,
taken_alone:
true,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_S.SNOOP_NOT_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_S.SNOOP_NOT_NEEDED",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
4296017920,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NONE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NONE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
2149318658,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_S.SPL_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_S.SPL_HIT",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
1074792448,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_NONE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_NONE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
2148040704,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.SNOOP_HIT_NO_FWD",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.SNOOP_HIT_NO_FWD",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
17180918016,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SPL_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SPL_HIT",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
1077968896,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.SNOOP_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.SNOOP_HITM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
68720525568,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(198),
umask:
Tuple::One(1),
event_name:
"FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1",
brief_description:
"Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100007,
msr_index:
MSRIndex::One(247),
msr_value:
1049094,
taken_alone:
true,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS.ANY_SNOOP",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS.ANY_SNOOP",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
274810800128,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
137506062592,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("INT_MISC.RECOVERY_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(13),
umask:
Tuple::One(1),
event_name:
"INT_MISC.RECOVERY_CYCLES",
brief_description:
"Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_ISSUED.SLOW_LEA",
IntelPerformanceCounterDescription{event_code:
Tuple::One(14),
umask:
Tuple::One(32),
event_name:
"UOPS_ISSUED.SLOW_LEA",
brief_description:
"Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_HIT_NO_FWD",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_HIT_NO_FWD",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
18186502146,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.SPL_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.SPL_HIT",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
1074266368,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_HITM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
68723703808,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("CYCLE_ACTIVITY.CYCLES_L2_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(163),
umask:
Tuple::One(1),
event_name:
"CYCLE_ACTIVITY.CYCLES_L2_MISS",
brief_description:
"Cycles while L2 cache miss demand load is outstanding.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NON_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NON_DRAM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
137440788482,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.L3_MISS.ANY_SNOOP",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.L3_MISS.ANY_SNOOP",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
274810830848,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
2149318657,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NOT_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NOT_NEEDED",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
4295491585,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SPL_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SPL_HIT",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
1073872900,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_S.SNOOP_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_S.SNOOP_MISS",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
8590985216,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_HITM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
68720558080,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_HIT_NO_FWD",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_HIT_NO_FWD",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
17180917764,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
137443147777,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("CPU_CLK_UNHALTED.THREAD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(0),
umask:
Tuple::One(2),
event_name:
"CPU_CLK_UNHALTED.THREAD",
brief_description:
"Core cycles when the thread is not in halt state",
public_description:
None,
counter:
Counter::Fixed(4),
counter_ht_off:
Counter::Fixed(4),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
137443149824,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("EXE_ACTIVITY.1_PORTS_UTIL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(166),
umask:
Tuple::One(2),
event_name:
"EXE_ACTIVITY.1_PORTS_UTIL",
brief_description:
"Cycles total of 1 uop is executed on all ports and Reservation Station was not empty.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
137506062337,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
17246978176,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED",
brief_description:
"Counts demand data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
4296802305,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("CPU_CLK_UNHALTED.THREAD_P",
IntelPerformanceCounterDescription{event_code:
Tuple::One(60),
umask:
Tuple::One(0),
event_name:
"CPU_CLK_UNHALTED.THREAD_P",
brief_description:
"Thread cycles when thread is not in halt state",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
68721311746,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
68786585604,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(60),
umask:
Tuple::One(2),
event_name:
"CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE",
brief_description:
"Count XClk pulses when this thread is unhalted and the other thread is halted.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_HITM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
68719608064,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(210),
umask:
Tuple::One(2),
event_name:
"MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT",
brief_description:
"Retired load instructions which data sources were L3 and cross-core snoop hits in on-pkg core cache",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
20011,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
true,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_DISPATCHED_PORT.PORT_6",
IntelPerformanceCounterDescription{event_code:
Tuple::One(161),
umask:
Tuple::One(64),
event_name:
"UOPS_DISPATCHED_PORT.PORT_6",
brief_description:
"Cycles per thread when uops are executed in port 6",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_HITM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
68719771648,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
9596567556,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("HLE_RETIRED.ABORTED_UNFRIENDLY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(200),
umask:
Tuple::One(32),
event_name:
"HLE_RETIRED.ABORTED_UNFRIENDLY",
brief_description:
"Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("RESOURCE_STALLS.ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(162),
umask:
Tuple::One(1),
event_name:
"RESOURCE_STALLS.ANY",
brief_description:
"Resource-related stall cycles",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
4299161728,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NONE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NONE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
2149351424,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_RQSTS.MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(36),
umask:
Tuple::One(63),
event_name:
"L2_RQSTS.MISS",
brief_description:
"All requests that miss L2 cache",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_INST_RETIRED.ALL_BRANCHES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(196),
umask:
Tuple::One(0),
event_name:
"BR_INST_RETIRED.ALL_BRANCHES",
brief_description:
"All (macro) branch instructions retired.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
400009,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SPL_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SPL_HIT",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
1077936130,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NON_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NON_DRAM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
137439477761,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_S.SNOOP_NONE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_S.SNOOP_NONE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
2148534272,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_NONE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_NONE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
2148532226,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.SNOOP_HIT_NO_FWD",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.SNOOP_HIT_NO_FWD",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
17180393728,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_HITM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
68720001028,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("ITLB.ITLB_FLUSH",
IntelPerformanceCounterDescription{event_code:
Tuple::One(174),
umask:
Tuple::One(1),
event_name:
"ITLB.ITLB_FLUSH",
brief_description:
"Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100007,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("TX_EXEC.MISC2",
IntelPerformanceCounterDescription{event_code:
Tuple::One(93),
umask:
Tuple::One(2),
event_name:
"TX_EXEC.MISC2",
brief_description:
"Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SPL_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SPL_HIT",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
1140850689,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("EXE_ACTIVITY.3_PORTS_UTIL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(166),
umask:
Tuple::One(8),
event_name:
"EXE_ACTIVITY.3_PORTS_UTIL",
brief_description:
"Cycles total of 3 uops are executed on all ports and Reservation Station was not empty.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_HITM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
68719738881,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
2214594560,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_HITM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
68719640576,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
273806000132,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
273804689412,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("EPT.WALK_PENDING",
IntelPerformanceCounterDescription{event_code:
Tuple::One(79),
umask:
Tuple::One(16),
event_name:
"EPT.WALK_PENDING",
brief_description:
"Counts 1 per cycle for each PMH that is busy with a EPT (Extended Page Table) walk for any request type.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_2",
IntelPerformanceCounterDescription{event_code:
Tuple::One(198),
umask:
Tuple::One(1),
event_name:
"FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_2",
brief_description:
"Retired instructions that are fetched after an interval where the front-end had at least 2 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100007,
msr_index:
MSRIndex::One(247),
msr_value:
2097670,
taken_alone:
true,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_E.SNOOP_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_E.SNOOP_MISS",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
8590460928,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("FRONTEND_RETIRED.LATENCY_GE_4",
IntelPerformanceCounterDescription{event_code:
Tuple::One(198),
umask:
Tuple::One(1),
event_name:
"FRONTEND_RETIRED.LATENCY_GE_4",
brief_description:
"Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100007,
msr_index:
MSRIndex::One(247),
msr_value:
4195334,
taken_alone:
true,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
137443147904,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("HLE_RETIRED.ABORTED_EVENTS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(200),
umask:
Tuple::One(128),
event_name:
"HLE_RETIRED.ABORTED_EVENTS",
brief_description:
"Number of times an HLE execution aborted due to unfriendly events (such as interrupts).",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.SNOOP_NONE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.SNOOP_NONE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
2148532480,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.L3_HIT.SPL_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.L3_HIT.SPL_HIT",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
1075609600,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
4299161856,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_HIT_NO_FWD",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_HIT_NO_FWD",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
17180131330,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
8590065665,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("TX_EXEC.MISC4",
IntelPerformanceCounterDescription{event_code:
Tuple::One(93),
umask:
Tuple::One(8),
event_name:
"TX_EXEC.MISC4",
brief_description:
"Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NON_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NON_DRAM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
137439215620,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("ITLB_MISSES.WALK_COMPLETED",
IntelPerformanceCounterDescription{event_code:
Tuple::One(133),
umask:
Tuple::One(14),
event_name:
"ITLB_MISSES.WALK_COMPLETED",
brief_description:
"Code miss in all TLB levels causes a page walk that completes. (All page sizes)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_MISS",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
8590065668,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_NOT_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_NOT_NEEDED",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
4296048640,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_REQUESTS.DEMAND_CODE_RD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(176),
umask:
Tuple::One(2),
event_name:
"OFFCORE_REQUESTS.DEMAND_CODE_RD",
brief_description:
"Cacheable and noncachaeble code read requests",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.ANY_SNOOP",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.ANY_SNOOP",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
273804328960,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_S.SNOOP_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_S.SNOOP_HITM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
68720527360,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED",
brief_description:
"Counts all demand code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
4296802308,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_INST_RETIRED.NEAR_TAKEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(196),
umask:
Tuple::One(32),
event_name:
"BR_INST_RETIRED.NEAR_TAKEN",
brief_description:
"Taken branch instructions retired.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
400009,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
273871273988,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
2147614721,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.SNOOP_NOT_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.SNOOP_NOT_NEEDED",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
4296016000,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NONE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NONE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
2148532228,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_NONE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_NONE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
2151677954,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_M.SNOOP_NONE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_M.SNOOP_NONE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
2147747840,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("L1D_PEND_MISS.PENDING_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(72),
umask:
Tuple::One(1),
event_name:
"L1D_PEND_MISS.PENDING_CYCLES",
brief_description:
"Cycles with L1D load Misses outstanding.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SPL_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SPL_HIT",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
1140850944,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
brief_description:
"Counts demand data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
17181704193,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_MISS",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
8590098432,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
8657045504,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HITM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
68721312000,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_INST_RETIRED.ALL_BRANCHES_PEBS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(196),
umask:
Tuple::One(4),
event_name:
"BR_INST_RETIRED.ALL_BRANCHES_PEBS",
brief_description:
"All (macro) branch instructions retired.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
400009,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOnly,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.L3_HIT_M.ANY_SNOOP",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.L3_HIT_M.ANY_SNOOP",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
273804460032,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_HITM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
69726109824,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("RS_EVENTS.EMPTY_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(94),
umask:
Tuple::One(1),
event_name:
"RS_EVENTS.EMPTY_CYCLES",
brief_description:
"Cycles when Reservation Station (RS) is empty for the thread",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NONE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NONE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
2148007937,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
18186502272,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_MISS",
brief_description:
"Counts all demand data writes (RFOs) that hit in the L3 and the snoops sent to sibling cores return clean response.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
8591769602,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_NONE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_NONE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
2148007938,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NOT_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NOT_NEEDED",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
4295229441,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_HIT_NO_FWD",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_HIT_NO_FWD",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
17180950528,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_MISS",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
8590196737,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NON_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NON_DRAM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
137439117312,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("TX_MEM.ABORT_CONFLICT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(84),
umask:
Tuple::One(1),
event_name:
"TX_MEM.ABORT_CONFLICT",
brief_description:
"Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(96),
umask:
Tuple::One(8),
event_name:
"OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
brief_description:
"Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_INST_RETIRED.CONDITIONAL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(196),
umask:
Tuple::One(1),
event_name:
"BR_INST_RETIRED.CONDITIONAL",
brief_description:
"Conditional branch instructions retired.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
400009,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_E.SNOOP_NONE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_E.SNOOP_NONE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
2148009984,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_HITM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
68719607810,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_NONE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_NONE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
2151678080,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.L3_HIT_M.SPL_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.L3_HIT_M.SPL_HIT",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
1074036736,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
brief_description:
"Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
17181704320,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_NOT_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_NOT_NEEDED",
brief_description:
"Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
4296802560,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("TLB_FLUSH.STLB_ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(189),
umask:
Tuple::One(32),
event_name:
"TLB_FLUSH.STLB_ANY",
brief_description:
"STLB flush attempts",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100007,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.L3_HIT_E.ANY_SNOOP",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.L3_HIT_E.ANY_SNOOP",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
273804722176,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
137506062464,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_LINES_IN.ALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(241),
umask:
Tuple::One(31),
event_name:
"L2_LINES_IN.ALL",
brief_description:
"L2 cache lines filling L2",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
17184096256,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_MISS",
brief_description:
"Counts any other requests that hit in the L3 and the snoops sent to sibling cores return clean response.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
8591802368,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
IntelPerformanceCounterDescription{event_code:
Tuple::One(205),
umask:
Tuple::One(1),
event_name:
"MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
brief_description:
"Counts loads when the latency from first dispatch to completion is greater than 32 cycles.",
public_description:
Some("Counts loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100007,
msr_index:
MSRIndex::One(246),
msr_value:
32,
taken_alone:
true,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOnly,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("LSD.UOPS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(168),
umask:
Tuple::One(1),
event_name:
"LSD.UOPS",
brief_description:
"Number of Uops delivered by the LSD.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
17246978304,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
17184063490,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("ICACHE_64B.IFTAG_STALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(131),
umask:
Tuple::One(4),
event_name:
"ICACHE_64B.IFTAG_STALL",
brief_description:
"Cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_EXECUTED.X87",
IntelPerformanceCounterDescription{event_code:
Tuple::One(177),
umask:
Tuple::One(16),
event_name:
"UOPS_EXECUTED.X87",
brief_description:
"Counts the number of x87 uops dispatched.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_HIT_NO_FWD",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_HIT_NO_FWD",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
18186502400,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_EXECUTED.CORE_CYCLES_GE_3",
IntelPerformanceCounterDescription{event_code:
Tuple::One(177),
umask:
Tuple::One(2),
event_name:
"UOPS_EXECUTED.CORE_CYCLES_GE_3",
brief_description:
"Cycles at least 3 micro-op is executed from any thread on physical core",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
3,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("ICACHE_64B.IFTAG_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(131),
umask:
Tuple::One(1),
event_name:
"ICACHE_64B.IFTAG_HIT",
brief_description:
"Instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(84),
umask:
Tuple::One(32),
event_name:
"TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT",
brief_description:
"Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.ANY_SNOOP",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.ANY_SNOOP",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
274810798082,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_NOT_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_NOT_NEEDED",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
5301600512,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.SUPPLIER_NONE.SNOOP_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.SUPPLIER_NONE.SNOOP_HITM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
68719609856,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_HITM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
68719738884,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("HW_INTERRUPTS.RECEIVED",
IntelPerformanceCounterDescription{event_code:
Tuple::One(203),
umask:
Tuple::One(1),
event_name:
"HW_INTERRUPTS.RECEIVED",
brief_description:
"Number of hardware interrupts received by the processor.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
68786618368,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE",
brief_description:
"Counts all demand code reads that have any response type.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
65540,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.SUPPLIER_NONE.SNOOP_NONE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.SUPPLIER_NONE.SNOOP_NONE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
2147616768,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.SNOOP_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.SNOOP_MISS",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
8590983424,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE",
brief_description:
"Counts demand data reads that have any response type.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
65537,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_NON_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_NON_DRAM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
137440788736,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SPL_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SPL_HIT",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
1140850690,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT.SNOOP_HIT_NO_FWD",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT.SNOOP_HIT_NO_FWD",
brief_description:
"Counts streaming stores that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
17181706240,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_EXECUTED.CORE_CYCLES_GE_1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(177),
umask:
Tuple::One(2),
event_name:
"UOPS_EXECUTED.CORE_CYCLES_GE_1",
brief_description:
"Cycles at least 1 micro-op is executed from any thread on physical core",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("CPU_CLK_THREAD_UNHALTED.REF_XCLK",
IntelPerformanceCounterDescription{event_code:
Tuple::One(60),
umask:
Tuple::One(1),
event_name:
"CPU_CLK_THREAD_UNHALTED.REF_XCLK",
brief_description:
"Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NONE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NONE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
3154116610,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("ILD_STALL.LCP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(135),
umask:
Tuple::One(1),
event_name:
"ILD_STALL.LCP",
brief_description:
"Stalls caused by changing prefix length of the instruction.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
4362108928,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_HITM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
68723671042,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SPL_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SPL_HIT",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
1074790404,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE",
brief_description:
"Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("RESOURCE_STALLS.SB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(162),
umask:
Tuple::One(8),
event_name:
"RESOURCE_STALLS.SB",
brief_description:
"Cycles stalled due to no store buffers available. (not including draining form sync).",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_NONE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_NONE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
2151677956,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.SNOOP_NONE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.SNOOP_NONE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
2147745920,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("DTLB_LOAD_MISSES.WALK_PENDING",
IntelPerformanceCounterDescription{event_code:
Tuple::One(8),
umask:
Tuple::One(16),
event_name:
"DTLB_LOAD_MISSES.WALK_PENDING",
brief_description:
"Counts 1 per cycle for each PMH that is busy with a page walk for a load.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("RS_EVENTS.EMPTY_END",
IntelPerformanceCounterDescription{event_code:
Tuple::One(94),
umask:
Tuple::One(1),
event_name:
"RS_EVENTS.EMPTY_END",
brief_description:
"Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
true,
any_thread:
false,
edge_detect:
true,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(7),
umask:
Tuple::One(1),
event_name:
"LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",
brief_description:
"False dependencies in MOB due to partial compare on address.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_MISS",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
8591015936,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_ISSUED.ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(14),
umask:
Tuple::One(1),
event_name:
"UOPS_ISSUED.ANY",
brief_description:
"Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
8657043712,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
68721311745,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(84),
umask:
Tuple::One(8),
event_name:
"TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY",
brief_description:
"Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_LOAD_RETIRED.L2_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(209),
umask:
Tuple::One(2),
event_name:
"MEM_LOAD_RETIRED.L2_HIT",
brief_description:
"Retired load instructions with L2 cache hits as data sources",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
true,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
2214592640,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_RQSTS.PF_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(36),
umask:
Tuple::One(216),
event_name:
"L2_RQSTS.PF_HIT",
brief_description:
"Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cache",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(210),
umask:
Tuple::One(4),
event_name:
"MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM",
brief_description:
"Retired load instructions which data sources were HitM responses from shared L3",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
20011,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
true,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_MISS",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
8590196740,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("ITLB_MISSES.STLB_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(133),
umask:
Tuple::One(32),
event_name:
"ITLB_MISSES.STLB_HIT",
brief_description:
"Intruction fetch requests that miss the ITLB and hit the STLB.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_HIT_NO_FWD",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_HIT_NO_FWD",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
17180393473,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_INST_RETIRED.NEAR_CALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(196),
umask:
Tuple::One(2),
event_name:
"BR_INST_RETIRED.NEAR_CALL",
brief_description:
"Direct and indirect near call instructions retired.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100007,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
9596567553,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("LONGEST_LAT_CACHE.REFERENCE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(46),
umask:
Tuple::One(79),
event_name:
"LONGEST_LAT_CACHE.REFERENCE",
brief_description:
"Core-originated cacheable demand requests that refer to L3",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SPL_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SPL_HIT",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
1075576836,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
17180000258,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_LOAD_RETIRED.FB_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(209),
umask:
Tuple::One(64),
event_name:
"MEM_LOAD_RETIRED.FB_HIT",
brief_description:
"Retired load instructions which data sources were load missed L1 but hit FB due to preceding miss to the same cache line with data not ready",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100007,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
true,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH",
IntelPerformanceCounterDescription{event_code:
Tuple::One(84),
umask:
Tuple::One(16),
event_name:
"TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH",
brief_description:
"Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_INST_RETIRED.LOCK_LOADS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(208),
umask:
Tuple::One(33),
event_name:
"MEM_INST_RETIRED.LOCK_LOADS",
brief_description:
"Retired load instructions with locked access.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100007,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
true,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NON_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NON_DRAM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
137439084546,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
4362076162,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_NON_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_NON_DRAM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
137439248384,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_DISPATCHED_PORT.PORT_1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(161),
umask:
Tuple::One(2),
event_name:
"UOPS_DISPATCHED_PORT.PORT_1",
brief_description:
"Cycles per thread when uops are executed in port 1",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(156),
umask:
Tuple::One(1),
event_name:
"IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
brief_description:
"Cycles with less than 2 uops delivered by the front end.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
2,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.ANY_SNOOP",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.ANY_SNOOP",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
273804427520,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.L4_HIT_LOCAL_L4.SNOOP_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.L4_HIT_LOCAL_L4.SNOOP_MISS",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
8594129152,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_M.SNOOP_NOT_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_M.SNOOP_NOT_NEEDED",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
4295231488,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("FRONTEND_RETIRED.LATENCY_GE_512",
IntelPerformanceCounterDescription{event_code:
Tuple::One(198),
umask:
Tuple::One(1),
event_name:
"FRONTEND_RETIRED.LATENCY_GE_512",
brief_description:
"Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100007,
msr_index:
MSRIndex::One(247),
msr_value:
4325382,
taken_alone:
true,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_HITM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
68720525313,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_RQSTS.RFO_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(36),
umask:
Tuple::One(34),
event_name:
"L2_RQSTS.RFO_MISS",
brief_description:
"RFO requests that miss L2 cache",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.SNOOP_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.SNOOP_HITM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
68719739136,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("LD_BLOCKS.STORE_FORWARD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(3),
umask:
Tuple::One(2),
event_name:
"LD_BLOCKS.STORE_FORWARD",
brief_description:
"loads blocked by overlapping with store buffer that cannot be forwarded .",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_MISS",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
8590491648,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NON_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NON_DRAM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
137439084545,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
273871273986,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
68786585602,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("CPU_CLK_UNHALTED.REF_TSC",
IntelPerformanceCounterDescription{event_code:
Tuple::One(0),
umask:
Tuple::One(3),
event_name:
"CPU_CLK_UNHALTED.REF_TSC",
brief_description:
"Reference cycles when the core is not in halt state.",
public_description:
None,
counter:
Counter::Fixed(8),
counter_ht_off:
Counter::Fixed(8),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
4362076416,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOP",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOP",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
273804296194,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_HITM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
69726109700,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("IDQ.MS_SWITCHES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(121),
umask:
Tuple::One(48),
event_name:
"IDQ.MS_SWITCHES",
brief_description:
"Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
false,
any_thread:
false,
edge_detect:
true,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE",
brief_description:
"Counts streaming stores that have any response type.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
67584,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.SNOOP_NONE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.SNOOP_NONE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
2148008064,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(60),
umask:
Tuple::One(1),
event_name:
"CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY",
brief_description:
"Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
true,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SPL_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SPL_HIT",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
2080375040,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
273804689409,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NOT_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NOT_NEEDED",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
5301600258,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
IntelPerformanceCounterDescription{event_code:
Tuple::One(205),
umask:
Tuple::One(1),
event_name:
"MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
brief_description:
"Counts loads when the latency from first dispatch to completion is greater than 16 cycles.",
public_description:
Some("Counts loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
20011,
msr_index:
MSRIndex::One(246),
msr_value:
16,
taken_alone:
true,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOnly,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
4362076161,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("CYCLE_ACTIVITY.STALLS_TOTAL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(163),
umask:
Tuple::One(4),
event_name:
"CYCLE_ACTIVITY.STALLS_TOTAL",
brief_description:
"Total execution stalls.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
4,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_NONE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_NONE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
2151710720,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("TX_MEM.ABORT_CAPACITY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(84),
umask:
Tuple::One(2),
event_name:
"TX_MEM.ABORT_CAPACITY",
brief_description:
"Number of times a transactional abort was signaled due to a data capacity limitation for transactional reads or writes.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
2147614848,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.SNOOP_NOT_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.SNOOP_NOT_NEEDED",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
4295229568,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("IDQ.ALL_DSB_CYCLES_ANY_UOPS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(121),
umask:
Tuple::One(24),
event_name:
"IDQ.ALL_DSB_CYCLES_ANY_UOPS",
brief_description:
"Cycles Decode Stream Buffer (DSB) is delivering any Uop",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OTHER_ASSISTS.ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(193),
umask:
Tuple::One(63),
event_name:
"OTHER_ASSISTS.ANY",
brief_description:
"Number of times a microcode assist is invoked by HW other than FP-assist. Examples include AD (page Access Dirty) and AVX* related assists.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.SPL_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.SPL_HIT",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
1074004096,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NONE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NONE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
2148007940,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_MISS",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
8594129024,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SPL_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SPL_HIT",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
1140850692,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_RQSTS.ALL_CODE_RD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(36),
umask:
Tuple::One(228),
event_name:
"L2_RQSTS.ALL_CODE_RD",
brief_description:
"L2 code requests",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_HITM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
68719607812,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SPL_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SPL_HIT",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
1077936129,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_HIT_NO_FWD",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_HIT_NO_FWD",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
17180393474,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_NONE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_NONE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
2149318912,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("IDQ.ALL_MITE_CYCLES_ANY_UOPS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(121),
umask:
Tuple::One(36),
event_name:
"IDQ.ALL_MITE_CYCLES_ANY_UOPS",
brief_description:
"Cycles MITE is delivering any Uop",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_MISS",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
8594128900,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_RQSTS.ALL_DEMAND_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(36),
umask:
Tuple::One(39),
event_name:
"L2_RQSTS.ALL_DEMAND_MISS",
brief_description:
"Demand requests that miss L2 cache",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
137506062338,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("L1D_PEND_MISS.PENDING",
IntelPerformanceCounterDescription{event_code:
Tuple::One(72),
umask:
Tuple::One(1),
event_name:
"L1D_PEND_MISS.PENDING",
brief_description:
"L1D miss oustandings duration in cycles",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("EXE_ACTIVITY.BOUND_ON_STORES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(166),
umask:
Tuple::One(64),
event_name:
"EXE_ACTIVITY.BOUND_ON_STORES",
brief_description:
"Cycles where the Store Buffer was full and no outstanding load.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_RQSTS.CODE_RD_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(36),
umask:
Tuple::One(68),
event_name:
"L2_RQSTS.CODE_RD_HIT",
brief_description:
"L2 cache hits when fetching instructions, code reads.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_INST_RETIRED.NEAR_RETURN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(196),
umask:
Tuple::One(8),
event_name:
"BR_INST_RETIRED.NEAR_RETURN",
brief_description:
"Return instructions retired.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100007,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("RTM_RETIRED.ABORTED",
IntelPerformanceCounterDescription{event_code:
Tuple::One(201),
umask:
Tuple::One(4),
event_name:
"RTM_RETIRED.ABORTED",
brief_description:
"Number of times an RTM execution aborted due to any reasons (multiple categories may count as one).",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.L4_HIT_LOCAL_L4.SNOOP_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.L4_HIT_LOCAL_L4.SNOOP_HITM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
68723671296,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("ICACHE_64B.IFTAG_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(131),
umask:
Tuple::One(2),
event_name:
"ICACHE_64B.IFTAG_MISS",
brief_description:
"Instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NONE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NONE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
2147647488,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.ANY_RESPONSE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.ANY_RESPONSE",
brief_description:
"Counts any other requests that have any response type.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
98304,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
4299161602,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.ANY_SNOOP",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.ANY_SNOOP",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
273805213698,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NONE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NONE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
2147745796,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
273871274112,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_M.SNOOP_HIT_NO_FWD",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_M.SNOOP_HIT_NO_FWD",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
17180133376,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT.SNOOP_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT.SNOOP_HITM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
68721313792,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NOT_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NOT_NEEDED",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
4296015876,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.L4_HIT_LOCAL_L4.SNOOP_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.L4_HIT_LOCAL_L4.SNOOP_HITM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
68723673088,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("RTM_RETIRED.ABORTED_EVENTS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(201),
umask:
Tuple::One(128),
event_name:
"RTM_RETIRED.ABORTED_EVENTS",
brief_description:
"Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
8657043458,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
4299161601,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.SNOOP_NONE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.SNOOP_NONE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
2148532352,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
17180000512,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_HIT_NO_FWD",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_HIT_NO_FWD",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
18186534912,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SPL_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SPL_HIT",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
2080374788,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SPL_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SPL_HIT",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
1075576960,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_M.ANY_SNOOP",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_M.ANY_SNOOP",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
273804429312,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC",
IntelPerformanceCounterDescription{event_code:
Tuple::One(177),
umask:
Tuple::One(1),
event_name:
"UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC",
brief_description:
"Cycles where at least 2 uops were executed per-thread",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
2,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.SNOOP_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.SNOOP_HITM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
68719739008,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_INST_RETIRED.STLB_MISS_LOADS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(208),
umask:
Tuple::One(17),
event_name:
"MEM_INST_RETIRED.STLB_MISS_LOADS",
brief_description:
"Retired load instructions that miss the STLB.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
true,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_HITM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
69726109952,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_HIT_NO_FWD",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_HIT_NO_FWD",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
17180917761,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
17180002304,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.ANY_SNOOP",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.ANY_SNOOP",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
274810798336,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_NON_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_NON_DRAM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
137440034816,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.ANY_SNOOP",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.ANY_SNOOP",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
273808359425,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD",
brief_description:
"Counts all demand data writes (RFOs) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
17181704194,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.SNOOP_NONE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.SNOOP_NONE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
2147746048,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.SNOOP_NOT_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.SNOOP_NOT_NEEDED",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
4295491840,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(199),
umask:
Tuple::One(16),
event_name:
"FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
brief_description:
"Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.SNOOP_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.SNOOP_MISS",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
8590196992,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_LOAD_RETIRED.L2_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(209),
umask:
Tuple::One(16),
event_name:
"MEM_LOAD_RETIRED.L2_MISS",
brief_description:
"Retired load instructions missed L2 cache as data sources",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
50021,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
true,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SPL_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SPL_HIT",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
1140850816,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.ANY_SNOOP",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.ANY_SNOOP",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
273804689410,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("L1D.REPLACEMENT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(81),
umask:
Tuple::One(1),
event_name:
"L1D.REPLACEMENT",
brief_description:
"L1D data line replacements",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SPL_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SPL_HIT",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
2080374785,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_REQUESTS_BUFFER.SQ_FULL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(178),
umask:
Tuple::One(1),
event_name:
"OFFCORE_REQUESTS_BUFFER.SQ_FULL",
brief_description:
"Offcore requests buffer cannot take more entries for this thread core.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NON_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NON_DRAM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
137439215617,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_E.SNOOP_HIT_NO_FWD",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_E.SNOOP_HIT_NO_FWD",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
17180395520,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_LOAD_RETIRED.L3_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(209),
umask:
Tuple::One(32),
event_name:
"MEM_LOAD_RETIRED.L3_MISS",
brief_description:
"Retired load instructions missed L3 cache as data sources",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100007,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
true,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.ANY_SNOOP",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.ANY_SNOOP",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
273808392192,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.L4_HIT_LOCAL_L4.SNOOP_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.L4_HIT_LOCAL_L4.SNOOP_MISS",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
8594130944,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("DTLB_STORE_MISSES.WALK_PENDING",
IntelPerformanceCounterDescription{event_code:
Tuple::One(73),
umask:
Tuple::One(16),
event_name:
"DTLB_STORE_MISSES.WALK_PENDING",
brief_description:
"Counts 1 per cycle for each PMH that is busy with a page walk for a store.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_RQSTS.PF_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(36),
umask:
Tuple::One(56),
event_name:
"L2_RQSTS.PF_MISS",
brief_description:
"Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cache",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS_LOCAL_DRAM.SPL_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS_LOCAL_DRAM.SPL_HIT",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
1140852736,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
273805213697,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(156),
umask:
Tuple::One(1),
event_name:
"IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
brief_description:
"Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
3,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SPL_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SPL_HIT",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
1074003970,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_MISS",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
8594128897,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.SNOOP_NOT_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.SNOOP_NOT_NEEDED",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
4295229696,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("INST_RETIRED.ANY_P",
IntelPerformanceCounterDescription{event_code:
Tuple::One(192),
umask:
Tuple::One(0),
event_name:
"INST_RETIRED.ANY_P",
brief_description:
"Number of instructions retired. General Counter - architectural event",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.ANY_SNOOP",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.ANY_SNOOP",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
273808359428,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED",
brief_description:
"Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
4296802432,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_HIT_NO_FWD",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_HIT_NO_FWD",
brief_description:
"Counts any other requests that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
17181736960,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_HITM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
68720525316,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.L3_HIT_S.SPL_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.L3_HIT_S.SPL_HIT",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
1074823168,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
273871274240,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
IntelPerformanceCounterDescription{event_code:
Tuple::One(205),
umask:
Tuple::One(1),
event_name:
"MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
brief_description:
"Counts loads when the latency from first dispatch to completion is greater than 512 cycles.",
public_description:
Some("Counts loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
101,
msr_index:
MSRIndex::One(246),
msr_value:
512,
taken_alone:
true,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOnly,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
274810798081,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_MISS",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
9596567554,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.ANY_SNOOP",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.ANY_SNOOP",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
273804689664,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("CYCLE_ACTIVITY.STALLS_L1D_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(163),
umask:
Tuple::One(12),
event_name:
"CYCLE_ACTIVITY.STALLS_L1D_MISS",
brief_description:
"Execution stalls while L1 cache miss demand load is outstanding.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
12,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_NONE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_NONE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
2151677953,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.SNOOP_NOT_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.SNOOP_NOT_NEEDED",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
4296016128,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("FRONTEND_RETIRED.LATENCY_GE_32",
IntelPerformanceCounterDescription{event_code:
Tuple::One(198),
umask:
Tuple::One(1),
event_name:
"FRONTEND_RETIRED.LATENCY_GE_32",
brief_description:
"Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100007,
msr_index:
MSRIndex::One(247),
msr_value:
4202502,
taken_alone:
true,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
68721311748,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("INST_RETIRED.ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(0),
umask:
Tuple::One(1),
event_name:
"INST_RETIRED.ANY",
brief_description:
"Instructions retired from execution.mem",
public_description:
None,
counter:
Counter::Fixed(2),
counter_ht_off:
Counter::Fixed(2),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NOT_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NOT_NEEDED",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
5301600260,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_NOT_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_NOT_NEEDED",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
4295491586,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.SPL_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.SPL_HIT",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
1074790528,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_NON_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_NON_DRAM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
138445586560,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(96),
umask:
Tuple::One(8),
event_name:
"OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
brief_description:
"Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
68786585856,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
137506062340,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_NOT_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_NOT_NEEDED",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
4295262208,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
IntelPerformanceCounterDescription{event_code:
Tuple::One(96),
umask:
Tuple::One(4),
event_name:
"OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
brief_description:
"Cycles with offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
274810798208,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(210),
umask:
Tuple::One(1),
event_name:
"MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS",
brief_description:
"Retired load instructions which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
20011,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
true,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_NON_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_NON_DRAM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
137439215618,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.SNOOP_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.SNOOP_HITM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
68720001152,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_TRANS.L2_WB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(240),
umask:
Tuple::One(64),
event_name:
"L2_TRANS.L2_WB",
brief_description:
"L2 writebacks that access L2 cache",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE",
brief_description:
"Counts all demand data writes (RFOs) that have any response type.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
65538,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.ANY_SNOOP",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.ANY_SNOOP",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
273804296448,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_S.SNOOP_HIT_NO_FWD",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_S.SNOOP_HIT_NO_FWD",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
17180919808,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOP",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOP",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
273804427392,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_HIT_NO_FWD",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_HIT_NO_FWD",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
17180131332,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("ITLB_MISSES.WALK_PENDING",
IntelPerformanceCounterDescription{event_code:
Tuple::One(133),
umask:
Tuple::One(16),
event_name:
"ITLB_MISSES.WALK_PENDING",
brief_description:
"Counts 1 per cycle for each PMH that is busy with a page walk for an instruction fetch request.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.L3_HIT_E.SPL_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.L3_HIT_E.SPL_HIT",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
1074298880,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("DTLB_STORE_MISSES.WALK_COMPLETED",
IntelPerformanceCounterDescription{event_code:
Tuple::One(73),
umask:
Tuple::One(14),
event_name:
"DTLB_STORE_MISSES.WALK_COMPLETED",
brief_description:
"Store misses in all TLB levels causes a page walk that completes. (All page sizes)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_MISS",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
8590458882,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
17180033024,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
17184063744,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.ANY_RESPONSE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.ANY_RESPONSE",
brief_description:
"Counts all prefetch (that bring data to LLC only) data reads that have any response type.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
65664,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_NONE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_NONE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
3154116864,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("LSD.CYCLES_ACTIVE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(168),
umask:
Tuple::One(1),
event_name:
"LSD.CYCLES_ACTIVE",
brief_description:
"Cycles Uops delivered by the LSD, but didn\'t come from the decoder",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOP",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOP",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
273804689536,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NON_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NON_DRAM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
137440788481,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
2214592514,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_E.SNOOP_NOT_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_E.SNOOP_NOT_NEEDED",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
4295493632,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(199),
umask:
Tuple::One(1),
event_name:
"FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
brief_description:
"Number of SSE/AVX computational scalar double precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
3154116609,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS.SNOOP_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS.SNOOP_HITM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
69726111744,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("FRONTEND_RETIRED.LATENCY_GE_64",
IntelPerformanceCounterDescription{event_code:
Tuple::One(198),
umask:
Tuple::One(1),
event_name:
"FRONTEND_RETIRED.LATENCY_GE_64",
brief_description:
"Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100007,
msr_index:
MSRIndex::One(247),
msr_value:
4210694,
taken_alone:
true,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("CYCLE_ACTIVITY.STALLS_L2_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(163),
umask:
Tuple::One(5),
event_name:
"CYCLE_ACTIVITY.STALLS_L2_MISS",
brief_description:
"Execution stalls while L2 cache miss demand load is outstanding.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
5,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_HITM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
68723671044,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_MISS",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
8590458884,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_MISS",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
8590065920,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_HIT_NO_FWD",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_HIT_NO_FWD",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
17180393476,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("L1D_PEND_MISS.FB_FULL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(72),
umask:
Tuple::One(2),
event_name:
"L1D_PEND_MISS.FB_FULL",
brief_description:
"Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch. HWP are e",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
137443148032,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.ANY_SNOOP",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.ANY_SNOOP",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
273806000384,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("HLE_RETIRED.ABORTED_TIMER",
IntelPerformanceCounterDescription{event_code:
Tuple::One(200),
umask:
Tuple::One(16),
event_name:
"HLE_RETIRED.ABORTED_TIMER",
brief_description:
"Number of times an HLE execution aborted due to hardware timer expiration.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.SNOOP_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.SNOOP_MISS",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
8590983296,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("LSD.CYCLES_4_UOPS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(168),
umask:
Tuple::One(1),
event_name:
"LSD.CYCLES_4_UOPS",
brief_description:
"Cycles 4 Uops delivered by the LSD, but didn\'t come from the decoder",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
4,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_MISS",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
8590196738,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_INST_RETIRED.NOT_TAKEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(196),
umask:
Tuple::One(16),
event_name:
"BR_INST_RETIRED.NOT_TAKEN",
brief_description:
"Not taken branch instructions retired.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
400009,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.L4_HIT_LOCAL_L4.SNOOP_NONE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.L4_HIT_LOCAL_L4.SNOOP_NONE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
2151678208,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_NON_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_NON_DRAM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
137440788608,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("FRONTEND_RETIRED.DSB_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(198),
umask:
Tuple::One(1),
event_name:
"FRONTEND_RETIRED.DSB_MISS",
brief_description:
"Retired Instructions who experienced decode stream buffer (DSB - the decoded insturction-cache) miss.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100007,
msr_index:
MSRIndex::One(247),
msr_value:
17,
taken_alone:
true,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
IntelPerformanceCounterDescription{event_code:
Tuple::One(96),
umask:
Tuple::One(4),
event_name:
"OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
brief_description:
"Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_RQSTS.ALL_PF",
IntelPerformanceCounterDescription{event_code:
Tuple::One(36),
umask:
Tuple::One(248),
event_name:
"L2_RQSTS.ALL_PF",
brief_description:
"Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_HITM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
68720525314,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NOT_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NOT_NEEDED",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
5301633024,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_3",
IntelPerformanceCounterDescription{event_code:
Tuple::One(198),
umask:
Tuple::One(1),
event_name:
"FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_3",
brief_description:
"Retired instructions that are fetched after an interval where the front-end had at least 3 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100007,
msr_index:
MSRIndex::One(247),
msr_value:
3146246,
taken_alone:
true,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
4362076164,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.SNOOP_NON_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.SNOOP_NON_DRAM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
137439477888,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_EXECUTED.CORE_CYCLES_GE_4",
IntelPerformanceCounterDescription{event_code:
Tuple::One(177),
umask:
Tuple::One(2),
event_name:
"UOPS_EXECUTED.CORE_CYCLES_GE_4",
brief_description:
"Cycles at least 4 micro-op is executed from any thread on physical core",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
4,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("INST_RETIRED.PREC_DIST",
IntelPerformanceCounterDescription{event_code:
Tuple::One(192),
umask:
Tuple::One(1),
event_name:
"INST_RETIRED.PREC_DIST",
brief_description:
"Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution",
public_description:
None,
counter:
Counter::Programmable(2),
counter_ht_off:
Counter::Programmable(2),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOnly,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
17247010816,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS.SNOOP_NONE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS.SNOOP_NONE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
3154118656,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(156),
umask:
Tuple::One(1),
event_name:
"IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
brief_description:
"Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
4,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT.ANY_SNOOP",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT.ANY_SNOOP",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
273806002176,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC",
IntelPerformanceCounterDescription{event_code:
Tuple::One(177),
umask:
Tuple::One(1),
event_name:
"UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC",
brief_description:
"Cycles where at least 3 uops were executed per-thread",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
3,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NON_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NON_DRAM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
138445586436,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("L1D_PEND_MISS.PENDING_CYCLES_ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(72),
umask:
Tuple::One(1),
event_name:
"L1D_PEND_MISS.PENDING_CYCLES_ANY",
brief_description:
"Cycles with L1D load Misses outstanding from any thread on physical core",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
false,
any_thread:
true,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
4295098496,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("RTM_RETIRED.COMMIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(201),
umask:
Tuple::One(2),
event_name:
"RTM_RETIRED.COMMIT",
brief_description:
"Number of times an RTM execution successfully committed",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_HITM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
68721311872,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_NONE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_NONE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
2148564992,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SPL_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SPL_HIT",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
1074003972,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
8657043457,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
273804296320,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_NON_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_NON_DRAM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
138445586688,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("DTLB_LOAD_MISSES.WALK_COMPLETED",
IntelPerformanceCounterDescription{event_code:
Tuple::One(8),
umask:
Tuple::One(14),
event_name:
"DTLB_LOAD_MISSES.WALK_COMPLETED",
brief_description:
"Load miss in all TLB levels causes a page walk that completes. (All page sizes)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.SNOOP_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.SNOOP_HITM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
68720001280,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_RQSTS.ALL_RFO",
IntelPerformanceCounterDescription{event_code:
Tuple::One(36),
umask:
Tuple::One(226),
event_name:
"L2_RQSTS.ALL_RFO",
brief_description:
"RFO requests to L2 cache",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("DTLB_STORE_MISSES.WALK_ACTIVE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(73),
umask:
Tuple::One(16),
event_name:
"DTLB_STORE_MISSES.WALK_ACTIVE",
brief_description:
"Cycles when at least one PMH is busy with a page walk for a store.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
273806000256,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("CYCLE_ACTIVITY.STALLS_L3_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(163),
umask:
Tuple::One(6),
event_name:
"CYCLE_ACTIVITY.STALLS_L3_MISS",
brief_description:
"Execution stalls while L3 cache miss demand load is outstanding.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
6,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NOT_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NOT_NEEDED",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
4295491588,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.ANY_SNOOP",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.ANY_SNOOP",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
273804427266,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_HITM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
68721344512,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
17180000384,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
273804296193,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_INST_RETIRED.SPLIT_LOADS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(208),
umask:
Tuple::One(65),
event_name:
"MEM_INST_RETIRED.SPLIT_LOADS",
brief_description:
"Retired load instructions that split across a cacheline boundary.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
true,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_E.ANY_SNOOP",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_E.ANY_SNOOP",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
273804691456,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NON_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NON_DRAM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
138445586433,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
137506064384,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("TX_EXEC.MISC5",
IntelPerformanceCounterDescription{event_code:
Tuple::One(93),
umask:
Tuple::One(16),
event_name:
"TX_EXEC.MISC5",
brief_description:
"Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_RQSTS.ALL_DEMAND_REFERENCES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(36),
umask:
Tuple::One(231),
event_name:
"L2_RQSTS.ALL_DEMAND_REFERENCES",
brief_description:
"Demand requests to L2 cache",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NOT_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NOT_NEEDED",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
4295098370,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(96),
umask:
Tuple::One(1),
event_name:
"OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
brief_description:
"Offcore outstanding Demand Data Read transactions in uncore queue.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.L4_HIT_LOCAL_L4.SPL_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.L4_HIT_LOCAL_L4.SPL_HIT",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
1077936256,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("FRONTEND_RETIRED.LATENCY_GE_256",
IntelPerformanceCounterDescription{event_code:
Tuple::One(198),
umask:
Tuple::One(1),
event_name:
"FRONTEND_RETIRED.LATENCY_GE_256",
brief_description:
"Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100007,
msr_index:
MSRIndex::One(247),
msr_value:
4259846,
taken_alone:
true,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(199),
umask:
Tuple::One(2),
event_name:
"FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
brief_description:
"Number of SSE/AVX computational scalar single precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.L4_HIT_LOCAL_L4.SPL_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.L4_HIT_LOCAL_L4.SPL_HIT",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
1077938176,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_NONE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_NONE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
2147745794,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
2214592768,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.L3_MISS.SPL_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.L3_MISS.SPL_HIT",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
2080407552,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS",
brief_description:
"Counts all demand code reads that hit in the L3 and the snoops sent to sibling cores return clean response.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
8591769604,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
4295098372,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SPL_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SPL_HIT",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
1075576834,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_EXECUTED.CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(177),
umask:
Tuple::One(2),
event_name:
"UOPS_EXECUTED.CORE",
brief_description:
"Number of uops executed on the core.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_E.SNOOP_NON_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_E.SNOOP_NON_DRAM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
137439479808,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NON_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NON_DRAM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
137440002049,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("TLB_FLUSH.DTLB_THREAD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(189),
umask:
Tuple::One(1),
event_name:
"TLB_FLUSH.DTLB_THREAD",
brief_description:
"DTLB flush attempts of the thread-specific entries",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100007,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(199),
umask:
Tuple::One(4),
event_name:
"FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
brief_description:
"Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired. Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("BACLEARS.ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(230),
umask:
Tuple::One(1),
event_name:
"BACLEARS.ANY",
brief_description:
"Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT.SNOOP_NON_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT.SNOOP_NON_DRAM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
137440790528,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("LOAD_HIT_PRE.SW_PF",
IntelPerformanceCounterDescription{event_code:
Tuple::One(76),
umask:
Tuple::One(1),
event_name:
"LOAD_HIT_PRE.SW_PF",
brief_description:
"Demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
IntelPerformanceCounterDescription{event_code:
Tuple::One(205),
umask:
Tuple::One(1),
event_name:
"MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
brief_description:
"Counts loads when the latency from first dispatch to completion is greater than 64 cycles.",
public_description:
Some("Counts loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
2003,
msr_index:
MSRIndex::One(246),
msr_value:
64,
taken_alone:
true,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOnly,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_INST_RETIRED.SPLIT_STORES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(208),
umask:
Tuple::One(66),
event_name:
"MEM_INST_RETIRED.SPLIT_STORES",
brief_description:
"Retired store instructions that split across a cacheline boundary.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
true,
l1_hit_indication:
true,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("RTM_RETIRED.ABORTED_UNFRIENDLY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(201),
umask:
Tuple::One(32),
event_name:
"RTM_RETIRED.ABORTED_UNFRIENDLY",
brief_description:
"Number of times an RTM execution aborted due to HLE-unfriendly instructions",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("IDQ_UOPS_NOT_DELIVERED.CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(156),
umask:
Tuple::One(1),
event_name:
"IDQ_UOPS_NOT_DELIVERED.CORE",
brief_description:
"Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
137443147778,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("CYCLE_ACTIVITY.CYCLES_L1D_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(163),
umask:
Tuple::One(8),
event_name:
"CYCLE_ACTIVITY.CYCLES_L1D_MISS",
brief_description:
"Cycles while L1 cache miss demand load is outstanding.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
8,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.SUPPLIER_NONE.SNOOP_NON_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.SUPPLIER_NONE.SNOOP_NON_DRAM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
137439086592,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_M.SPL_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.L3_HIT_M.SPL_HIT",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
1074006016,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
2214625280,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
68786587648,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("INT_MISC.CLEAR_RESTEER_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(13),
umask:
Tuple::One(128),
event_name:
"INT_MISC.CLEAR_RESTEER_CYCLES",
brief_description:
"Cycles the issue-stage is waiting for front-end to fetch from resteered path following branch misprediction or machine clear events.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_HITM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
68720001026,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
137506095104,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.SPL_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.SPL_HIT",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
1074790656,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SPL_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SPL_HIT",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
2080374786,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_HITM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
68719738882,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_DISPATCHED_PORT.PORT_0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(161),
umask:
Tuple::One(1),
event_name:
"UOPS_DISPATCHED_PORT.PORT_0",
brief_description:
"Cycles per thread when uops are executed in port 0",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_INST_RETIRED.FAR_BRANCH",
IntelPerformanceCounterDescription{event_code:
Tuple::One(196),
umask:
Tuple::One(64),
event_name:
"BR_INST_RETIRED.FAR_BRANCH",
brief_description:
"Far branch instructions retired.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100007,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(96),
umask:
Tuple::One(1),
event_name:
"OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
brief_description:
"Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
68786585728,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,})]),}