pub const NEHALEMEP_CORE: Map<&'static str, IntelPerformanceCounterDescription> = ::phf::Map{key: 5621513170501782519,
disps:
::phf::Slice::Static(&[(0, 4), (0, 13), (0, 273), (1, 27),
(0, 359), (0, 195), (0, 19), (0, 13),
(0, 0), (0, 37), (1, 2), (0, 121),
(0, 132), (0, 21), (2, 258), (1, 534),
(2, 520), (0, 156), (0, 2), (0, 6),
(0, 5), (0, 29), (1, 154), (0, 43),
(0, 1), (0, 2), (0, 4), (0, 3), (0, 1),
(0, 1), (4, 369), (0, 8), (0, 146),
(0, 4), (0, 418), (0, 339), (0, 11),
(0, 320), (1, 278), (0, 27), (4, 364),
(3, 460), (0, 5), (0, 3), (5, 480),
(0, 239), (0, 72), (1, 0), (0, 315),
(0, 3), (2, 555), (0, 449), (0, 16),
(0, 160), (1, 0), (0, 12), (2, 450),
(0, 22), (0, 533), (0, 33), (0, 2),
(0, 0), (5, 485), (4, 198), (0, 462),
(0, 68), (0, 0), (0, 66), (0, 440),
(0, 149), (0, 7), (0, 2), (0, 127),
(0, 76), (1, 36), (0, 2), (1, 159),
(0, 42), (4, 67), (0, 4), (0, 269),
(0, 339), (0, 21), (0, 8), (4, 463),
(0, 286), (1, 1), (0, 95), (0, 154),
(0, 14), (0, 16), (1, 237), (0, 212),
(7, 242), (9, 42), (2, 553), (0, 172),
(0, 24), (0, 11), (15, 271), (0, 6),
(10, 117), (5, 409), (1, 75), (0, 0),
(3, 86), (0, 254), (0, 61), (6, 355),
(1, 255), (0, 417), (2, 41)]),
entries:
::phf::Slice::Static(&[("FP_MMX_TRANS.TO_FP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(204),
umask:
Tuple::One(1),
event_name:
"FP_MMX_TRANS.TO_FP",
brief_description:
"Transitions from MMX to Floating Point instructions",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_DATA.REMOTE_CACHE_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_DATA.REMOTE_CACHE_HITM",
brief_description:
"Offcore data reads that HITM in a remote cache",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
2065,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_IFETCH.REMOTE_CACHE_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_IFETCH.REMOTE_CACHE_HIT",
brief_description:
"Offcore prefetch code reads that HIT in a remote cache",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
4160,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_DATA_RD.REMOTE_CACHE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_DATA_RD.REMOTE_CACHE_DRAM",
brief_description:
"Offcore demand data reads satisfied by a remote cache or remote DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
14337,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE",
brief_description:
"Offcore code reads satisfied by the LLC and not found in a sibling core",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
324,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_IFETCH.ANY_CACHE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_IFETCH.ANY_CACHE_DRAM",
brief_description:
"Offcore demand code reads satisfied by any cache or DRAM.",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
32516,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_INST_EXEC.ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(136),
umask:
Tuple::One(127),
event_name:
"BR_INST_EXEC.ANY",
brief_description:
"Branch instructions executed",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_INST_EXEC.NEAR_CALLS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(136),
umask:
Tuple::One(48),
event_name:
"BR_INST_EXEC.NEAR_CALLS",
brief_description:
"Call branches executed",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
20000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L1I.HITS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(128),
umask:
Tuple::One(1),
event_name:
"L1I.HITS",
brief_description:
"L1I instruction fetch hits",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_DATA.LOCAL_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_DATA.LOCAL_DRAM",
brief_description:
"Offcore data reads satisfied by the local DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
16401,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("ITLB_FLUSH",
IntelPerformanceCounterDescription{event_code:
Tuple::One(174),
umask:
Tuple::One(1),
event_name:
"ITLB_FLUSH",
brief_description:
"ITLB flushes",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.OTHER.LOCAL_CACHE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.OTHER.LOCAL_CACHE_DRAM",
brief_description:
"Offcore other requests satisfied by the LLC or local DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
18304,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("SIMD_INT_128.PACKED_MPY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(18),
umask:
Tuple::One(1),
event_name:
"SIMD_INT_128.PACKED_MPY",
brief_description:
"128 bit SIMD integer multiply operations",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_DATA.ANY_CACHE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_DATA.ANY_CACHE_DRAM",
brief_description:
"Offcore data reads satisfied by any cache or DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
32529,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("RESOURCE_STALLS.ROB_FULL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(162),
umask:
Tuple::One(16),
event_name:
"RESOURCE_STALLS.ROB_FULL",
brief_description:
"ROB full stall cycles",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PREFETCH.ANY_LOCATION",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PREFETCH.ANY_LOCATION",
brief_description:
"All offcore prefetch requests",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
65392,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_RQSTS.RFOS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(36),
umask:
Tuple::One(12),
event_name:
"L2_RQSTS.RFOS",
brief_description:
"L2 RFO requests",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_IFETCH.REMOTE_CACHE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_IFETCH.REMOTE_CACHE",
brief_description:
"Offcore prefetch code reads satisfied by a remote cache",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
6208,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("SEG_RENAME_STALLS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(212),
umask:
Tuple::One(1),
event_name:
"SEG_RENAME_STALLS",
brief_description:
"Segment rename stall cycles",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_REQUEST.LOCAL_CACHE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_REQUEST.LOCAL_CACHE_DRAM",
brief_description:
"Offcore requests satisfied by the LLC or local DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
18431,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("ILD_STALL.MRU",
IntelPerformanceCounterDescription{event_code:
Tuple::One(135),
umask:
Tuple::One(2),
event_name:
"ILD_STALL.MRU",
brief_description:
"Stall cycles due to BPU MRU bypass",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_DATA.LLC_HIT_NO_OTHER_CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_DATA.LLC_HIT_NO_OTHER_CORE",
brief_description:
"Offcore data reads satisfied by the LLC and not found in a sibling core",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
273,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("LOAD_DISPATCH.RS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(19),
umask:
Tuple::One(1),
event_name:
"LOAD_DISPATCH.RS",
brief_description:
"Loads dispatched that bypass the MOB",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("CACHE_LOCK_CYCLES.L1D",
IntelPerformanceCounterDescription{event_code:
Tuple::One(99),
umask:
Tuple::One(2),
event_name:
"CACHE_LOCK_CYCLES.L1D",
brief_description:
"Cycles L1D locked",
public_description:
None,
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_LINES_OUT.PREFETCH_CLEAN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(242),
umask:
Tuple::One(4),
event_name:
"L2_LINES_OUT.PREFETCH_CLEAN",
brief_description:
"L2 lines evicted by a prefetch request",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("BPU_CLEARS.LATE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(232),
umask:
Tuple::One(2),
event_name:
"BPU_CLEARS.LATE",
brief_description:
"Late Branch Prediction Unit clears",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_IFETCH.REMOTE_CACHE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_IFETCH.REMOTE_CACHE",
brief_description:
"Offcore demand code reads satisfied by a remote cache",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
6148,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("SIMD_INT_128.PACK",
IntelPerformanceCounterDescription{event_code:
Tuple::One(18),
umask:
Tuple::One(4),
event_name:
"SIMD_INT_128.PACK",
brief_description:
"128 bit SIMD integer pack operations",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE",
brief_description:
"Offcore prefetch data reads satisfied by the LLC and not found in a sibling core",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
272,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("L1D_WB_L2.S_STATE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(40),
umask:
Tuple::One(2),
event_name:
"L1D_WB_L2.S_STATE",
brief_description:
"L1 writebacks to L2 in S state",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PREFETCH.LLC_HIT_NO_OTHER_CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PREFETCH.LLC_HIT_NO_OTHER_CORE",
brief_description:
"Offcore prefetch requests satisfied by the LLC and not found in a sibling core",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
368,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_RQSTS.PREFETCH_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(36),
umask:
Tuple::One(128),
event_name:
"L2_RQSTS.PREFETCH_MISS",
brief_description:
"L2 prefetch misses",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("DTLB_MISSES.STLB_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(73),
umask:
Tuple::One(16),
event_name:
"DTLB_MISSES.STLB_HIT",
brief_description:
"DTLB first level misses but second level hit",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("BACLEAR.CLEAR",
IntelPerformanceCounterDescription{event_code:
Tuple::One(230),
umask:
Tuple::One(1),
event_name:
"BACLEAR.CLEAR",
brief_description:
"BACLEAR asserted, regardless of cause",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_DATA.ANY_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_DATA.ANY_DRAM",
brief_description:
"Offcore demand data requests satisfied by any DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
24579,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("SB_DRAIN.ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(4),
umask:
Tuple::One(7),
event_name:
"SB_DRAIN.ANY",
brief_description:
"All Store buffer stall cycles",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_RFO.ANY_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_RFO.ANY_DRAM",
brief_description:
"Offcore prefetch RFO requests satisfied by any DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
24608,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_REQUEST.REMOTE_CACHE_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_REQUEST.REMOTE_CACHE_HITM",
brief_description:
"Offcore requests that HITM in a remote cache",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
2303,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PREFETCH.LLC_HIT_OTHER_CORE_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PREFETCH.LLC_HIT_OTHER_CORE_HITM",
brief_description:
"Offcore prefetch requests satisfied by the LLC and HITM in a sibling core",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
1136,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_RFO.IO_CSR_MMIO",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_RFO.IO_CSR_MMIO",
brief_description:
"Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
32770,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("CPU_CLK_UNHALTED.REF_P",
IntelPerformanceCounterDescription{event_code:
Tuple::One(60),
umask:
Tuple::One(1),
event_name:
"CPU_CLK_UNHALTED.REF_P",
brief_description:
"Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("SNOOP_RESPONSE.HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(184),
umask:
Tuple::One(4),
event_name:
"SNOOP_RESPONSE.HITM",
brief_description:
"Thread responded HITM to snoop",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("SIMD_INT_64.SHUFFLE_MOVE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(253),
umask:
Tuple::One(64),
event_name:
"SIMD_INT_64.SHUFFLE_MOVE",
brief_description:
"SIMD integer 64 bit shuffle/move operations",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_REQUEST.ANY_CACHE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_REQUEST.ANY_CACHE_DRAM",
brief_description:
"Offcore requests satisfied by any cache or DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
32767,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_LINES_IN.E_STATE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(241),
umask:
Tuple::One(4),
event_name:
"L2_LINES_IN.E_STATE",
brief_description:
"L2 lines allocated in the E state",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_REQUEST.ANY_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_REQUEST.ANY_DRAM",
brief_description:
"Offcore requests satisfied by any DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
24831,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_DATA_RD.REMOTE_CACHE_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_DATA_RD.REMOTE_CACHE_HIT",
brief_description:
"Offcore prefetch data reads that HIT in a remote cache",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
4112,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("CPU_CLK_UNHALTED.REF",
IntelPerformanceCounterDescription{event_code:
Tuple::One(0),
umask:
Tuple::One(0),
event_name:
"CPU_CLK_UNHALTED.REF",
brief_description:
"Reference cycles when thread is not halted (fixed counter)",
public_description:
None,
counter:
Counter::Fixed(8),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_DATA.LOCAL_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_DATA.LOCAL_DRAM",
brief_description:
"Offcore prefetch data requests satisfied by the local DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
16432,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_ISSUED.CORE_STALL_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(14),
umask:
Tuple::One(1),
event_name:
"UOPS_ISSUED.CORE_STALL_CYCLES",
brief_description:
"Cycles no Uops were issued on any thread",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
true,
any_thread:
true,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("SIMD_INT_64.PACK",
IntelPerformanceCounterDescription{event_code:
Tuple::One(253),
umask:
Tuple::One(4),
event_name:
"SIMD_INT_64.PACK",
brief_description:
"SIMD integer 64 bit pack operations",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("RAT_STALLS.ROB_READ_PORT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(210),
umask:
Tuple::One(4),
event_name:
"RAT_STALLS.ROB_READ_PORT",
brief_description:
"ROB read port stalls cycles",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_IFETCH.LOCAL_CACHE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_IFETCH.LOCAL_CACHE",
brief_description:
"Offcore prefetch code reads satisfied by the LLC",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
1856,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE",
brief_description:
"Offcore requests satisfied by the LLC and not found in a sibling core",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
511,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(203),
umask:
Tuple::One(8),
event_name:
"MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM",
brief_description:
"Retired loads that hit sibling core\'s L2 in modified or unmodified states (Precise Event)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
40000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MACRO_INSTS.FUSIONS_DECODED",
IntelPerformanceCounterDescription{event_code:
Tuple::One(166),
umask:
Tuple::One(1),
event_name:
"MACRO_INSTS.FUSIONS_DECODED",
brief_description:
"Macro-fused instructions decoded",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_IFETCH.ANY_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_IFETCH.ANY_DRAM",
brief_description:
"Offcore demand code reads satisfied by any DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
24580,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_UNCORE_RETIRED.LOCAL_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(15),
umask:
Tuple::One(32),
event_name:
"MEM_UNCORE_RETIRED.LOCAL_DRAM",
brief_description:
"Load instructions retired with a data source of local DRAM or locally homed remote hitm (Precise Event)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
10000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L1D_CACHE_LOCK.S_STATE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(66),
umask:
Tuple::One(2),
event_name:
"L1D_CACHE_LOCK.S_STATE",
brief_description:
"L1 data cache load locks in S state",
public_description:
None,
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("LONGEST_LAT_CACHE.MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(46),
umask:
Tuple::One(65),
event_name:
"LONGEST_LAT_CACHE.MISS",
brief_description:
"Longest latency cache miss",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_RQSTS.PREFETCHES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(36),
umask:
Tuple::One(192),
event_name:
"L2_RQSTS.PREFETCHES",
brief_description:
"All L2 prefetches",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_INST_EXEC.NON_CALLS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(136),
umask:
Tuple::One(7),
event_name:
"BR_INST_EXEC.NON_CALLS",
brief_description:
"All non call branches executed",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_LINES_OUT.ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(242),
umask:
Tuple::One(15),
event_name:
"L2_LINES_OUT.ANY",
brief_description:
"L2 lines evicted",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_RFO.REMOTE_CACHE_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_RFO.REMOTE_CACHE_HITM",
brief_description:
"Offcore prefetch RFO requests that HITM in a remote cache",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
2080,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_IFETCH.LOCAL_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_IFETCH.LOCAL_DRAM",
brief_description:
"Offcore demand code reads satisfied by the local DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
16388,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DATA_IN.ANY_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DATA_IN.ANY_DRAM",
brief_description:
"Offcore request = all data, response = any DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
24627,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("DTLB_MISSES.ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(73),
umask:
Tuple::One(1),
event_name:
"DTLB_MISSES.ANY",
brief_description:
"DTLB misses",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L1D_CACHE_LOCK.HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(66),
umask:
Tuple::One(1),
event_name:
"L1D_CACHE_LOCK.HIT",
brief_description:
"L1 data cache load lock hits",
public_description:
None,
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_UNCORE_RETIRED.UNCACHEABLE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(15),
umask:
Tuple::One(128),
event_name:
"MEM_UNCORE_RETIRED.UNCACHEABLE",
brief_description:
"Load instructions retired IO (Precise Event)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
4000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_RETIRED.MACRO_FUSED",
IntelPerformanceCounterDescription{event_code:
Tuple::One(194),
umask:
Tuple::One(4),
event_name:
"UOPS_RETIRED.MACRO_FUSED",
brief_description:
"Macro-fused Uops retired (Precise Event)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_RFO.REMOTE_CACHE_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_RFO.REMOTE_CACHE_HITM",
brief_description:
"Offcore RFO requests that HITM in a remote cache",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
2082,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_MISP_EXEC.DIRECT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(137),
umask:
Tuple::One(2),
event_name:
"BR_MISP_EXEC.DIRECT",
brief_description:
"Mispredicted unconditional branches executed",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
20000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_RFO.LLC_HIT_OTHER_CORE_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_RFO.LLC_HIT_OTHER_CORE_HIT",
brief_description:
"Offcore RFO requests satisfied by the LLC and HIT in a sibling core",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
546,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_MISP_EXEC.ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(137),
umask:
Tuple::One(127),
event_name:
"BR_MISP_EXEC.ANY",
brief_description:
"Mispredicted branches executed",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
20000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_WRITE.RFO.I_STATE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(39),
umask:
Tuple::One(1),
event_name:
"L2_WRITE.RFO.I_STATE",
brief_description:
"L2 demand store RFOs in I state (misses)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("CPU_CLK_UNHALTED.TOTAL_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(60),
umask:
Tuple::One(0),
event_name:
"CPU_CLK_UNHALTED.TOTAL_CYCLES",
brief_description:
"Total CPU cycles",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
2,
invert:
true,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM",
brief_description:
"Offcore demand data requests satisfied by the LLC and HITM in a sibling core",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
1027,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DATA_IFETCH.REMOTE_CACHE_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DATA_IFETCH.REMOTE_CACHE_HITM",
brief_description:
"Offcore code or data read requests that HITM in a remote cache",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
2167,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_INST_RETIRED.LOADS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(11),
umask:
Tuple::One(1),
event_name:
"MEM_INST_RETIRED.LOADS",
brief_description:
"Instructions retired which contains a load (Precise Event)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DATA_IFETCH.REMOTE_CACHE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DATA_IFETCH.REMOTE_CACHE",
brief_description:
"Offcore code or data read requests satisfied by a remote cache",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
6263,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_REQUEST.ANY_LOCATION",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_REQUEST.ANY_LOCATION",
brief_description:
"All offcore requests",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
65535,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_IFETCH.LOCAL_CACHE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_IFETCH.LOCAL_CACHE_DRAM",
brief_description:
"Offcore code reads satisfied by the LLC or local DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
18244,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_IFETCH.ANY_LOCATION",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_IFETCH.ANY_LOCATION",
brief_description:
"All offcore prefetch code reads",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
65344,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_RFO.LOCAL_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_RFO.LOCAL_DRAM",
brief_description:
"Offcore RFO requests satisfied by the local DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
16418,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_DATA_RD.ANY_LLC_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_DATA_RD.ANY_LLC_MISS",
brief_description:
"Offcore prefetch data reads that missed the LLC",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
63504,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DATA_IN.REMOTE_CACHE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DATA_IN.REMOTE_CACHE_DRAM",
brief_description:
"Offcore request = all data, response = remote cache or dram",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
14387,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_DATA.LLC_HIT_OTHER_CORE_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_DATA.LLC_HIT_OTHER_CORE_HIT",
brief_description:
"Offcore data reads satisfied by the LLC and HIT in a sibling core",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
529,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_DATA_RQSTS.PREFETCH.MESI",
IntelPerformanceCounterDescription{event_code:
Tuple::One(38),
umask:
Tuple::One(240),
event_name:
"L2_DATA_RQSTS.PREFETCH.MESI",
brief_description:
"All L2 data prefetches",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("SIMD_INT_128.UNPACK",
IntelPerformanceCounterDescription{event_code:
Tuple::One(18),
umask:
Tuple::One(8),
event_name:
"SIMD_INT_128.UNPACK",
brief_description:
"128 bit SIMD integer unpack operations",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_REQUEST.IO_CSR_MMIO",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_REQUEST.IO_CSR_MMIO",
brief_description:
"Offcore requests satisfied by the IO, CSR, MMIO unit",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
33023,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_RFO.REMOTE_CACHE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_RFO.REMOTE_CACHE_DRAM",
brief_description:
"Offcore RFO requests satisfied by a remote cache or remote DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
14370,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_IFETCH.IO_CSR_MMIO",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_IFETCH.IO_CSR_MMIO",
brief_description:
"Offcore demand code reads satisfied by the IO, CSR, MMIO unit",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
32772,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_DATA_RQSTS.DEMAND.E_STATE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(38),
umask:
Tuple::One(4),
event_name:
"L2_DATA_RQSTS.DEMAND.E_STATE",
brief_description:
"L2 data demand loads in E state",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("CPU_CLK_UNHALTED.THREAD_P",
IntelPerformanceCounterDescription{event_code:
Tuple::One(60),
umask:
Tuple::One(0),
event_name:
"CPU_CLK_UNHALTED.THREAD_P",
brief_description:
"Cycles when thread is not halted (programmable counter)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.OTHER.ANY_LLC_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.OTHER.ANY_LLC_MISS",
brief_description:
"Offcore other requests that missed the LLC",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
63616,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_DATA_RD.REMOTE_CACHE_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_DATA_RD.REMOTE_CACHE_HIT",
brief_description:
"Offcore demand data reads that HIT in a remote cache",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
4097,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PREFETCH.REMOTE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PREFETCH.REMOTE_DRAM",
brief_description:
"Offcore prefetch requests satisfied by a remote DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
8304,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_DATA_RD.REMOTE_CACHE_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_DATA_RD.REMOTE_CACHE_HITM",
brief_description:
"Offcore demand data reads that HITM in a remote cache",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
2049,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("FP_COMP_OPS_EXE.SSE_FP_SCALAR",
IntelPerformanceCounterDescription{event_code:
Tuple::One(16),
umask:
Tuple::One(32),
event_name:
"FP_COMP_OPS_EXE.SSE_FP_SCALAR",
brief_description:
"SSE FP scalar Uops",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DATA_IN.REMOTE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DATA_IN.REMOTE_DRAM",
brief_description:
"Offcore data reads, RFO\'s and prefetches statisfied by the remote DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
8243,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_INST_EXEC.DIRECT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(136),
umask:
Tuple::One(2),
event_name:
"BR_INST_EXEC.DIRECT",
brief_description:
"Unconditional branches executed",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_RFO.REMOTE_CACHE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_RFO.REMOTE_CACHE",
brief_description:
"Offcore RFO requests satisfied by a remote cache",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
6178,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("MACHINE_CLEARS.MEM_ORDER",
IntelPerformanceCounterDescription{event_code:
Tuple::One(195),
umask:
Tuple::One(2),
event_name:
"MACHINE_CLEARS.MEM_ORDER",
brief_description:
"Execution pipeline restart due to Memory ordering conflicts",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
20000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_DATA.ANY_LLC_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_DATA.ANY_LLC_MISS",
brief_description:
"Offcore prefetch data requests that missed the LLC",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
63536,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_RQSTS.IFETCH_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(36),
umask:
Tuple::One(16),
event_name:
"L2_RQSTS.IFETCH_HIT",
brief_description:
"L2 instruction fetch hits",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_RQSTS.MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(36),
umask:
Tuple::One(170),
event_name:
"L2_RQSTS.MISS",
brief_description:
"All L2 misses",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_WRITE.RFO.HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(39),
umask:
Tuple::One(14),
event_name:
"L2_WRITE.RFO.HIT",
brief_description:
"All L2 demand store RFOs that hit the cache",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("SIMD_INT_64.PACKED_LOGICAL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(253),
umask:
Tuple::One(16),
event_name:
"SIMD_INT_64.PACKED_LOGICAL",
brief_description:
"SIMD integer 64 bit logical operations",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("DTLB_LOAD_MISSES.WALK_COMPLETED",
IntelPerformanceCounterDescription{event_code:
Tuple::One(8),
umask:
Tuple::One(2),
event_name:
"DTLB_LOAD_MISSES.WALK_COMPLETED",
brief_description:
"DTLB load miss page walks complete",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT",
brief_description:
"Offcore code reads satisfied by the LLC and HIT in a sibling core",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
580,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("RESOURCE_STALLS.STORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(162),
umask:
Tuple::One(8),
event_name:
"RESOURCE_STALLS.STORE",
brief_description:
"Store buffer stall cycles",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16",
IntelPerformanceCounterDescription{event_code:
Tuple::One(11),
umask:
Tuple::One(16),
event_name:
"MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16",
brief_description:
"Memory instructions retired above 16 clocks (Precise Event)",
public_description:
None,
counter:
Counter::Programmable(8),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
10000,
msr_index:
MSRIndex::One(246),
msr_value:
16,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOnly,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L1D_WB_L2.I_STATE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(40),
umask:
Tuple::One(1),
event_name:
"L1D_WB_L2.I_STATE",
brief_description:
"L1 writebacks to L2 in I state (misses)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("FP_COMP_OPS_EXE.SSE_FP_PACKED",
IntelPerformanceCounterDescription{event_code:
Tuple::One(16),
umask:
Tuple::One(16),
event_name:
"FP_COMP_OPS_EXE.SSE_FP_PACKED",
brief_description:
"SSE FP packed Uops",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_WRITE.LOCK.S_STATE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(39),
umask:
Tuple::One(32),
event_name:
"L2_WRITE.LOCK.S_STATE",
brief_description:
"L2 demand lock RFOs in S state",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_DATA.REMOTE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_DATA.REMOTE_DRAM",
brief_description:
"Offcore data reads satisfied by a remote DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
8209,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_EXECUTED.CORE_STALL_COUNT_NO_PORT5",
IntelPerformanceCounterDescription{event_code:
Tuple::One(177),
umask:
Tuple::One(31),
event_name:
"UOPS_EXECUTED.CORE_STALL_COUNT_NO_PORT5",
brief_description:
"Uops executed on ports 0-4 (core count)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
true,
any_thread:
true,
edge_detect:
true,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_REQUEST.ANY_LLC_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_REQUEST.ANY_LLC_MISS",
brief_description:
"Offcore requests that missed the LLC",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
63743,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_REQUEST.REMOTE_CACHE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_REQUEST.REMOTE_CACHE",
brief_description:
"Offcore requests satisfied by a remote cache",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
6399,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_RFO.LLC_HIT_OTHER_CORE_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_RFO.LLC_HIT_OTHER_CORE_HITM",
brief_description:
"Offcore RFO requests satisfied by the LLC and HITM in a sibling core",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
1058,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_DATA_RD.ANY_LOCATION",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_DATA_RD.ANY_LOCATION",
brief_description:
"All offcore demand data reads",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
65281,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PREFETCH.REMOTE_CACHE_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PREFETCH.REMOTE_CACHE_HIT",
brief_description:
"Offcore prefetch requests that HIT in a remote cache",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
4208,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_REQUEST.REMOTE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_REQUEST.REMOTE_DRAM",
brief_description:
"Offcore requests satisfied by a remote DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
8447,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_DATA.REMOTE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_DATA.REMOTE_DRAM",
brief_description:
"Offcore demand data requests satisfied by a remote DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
8195,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("CACHE_LOCK_CYCLES.L1D_L2",
IntelPerformanceCounterDescription{event_code:
Tuple::One(99),
umask:
Tuple::One(1),
event_name:
"CACHE_LOCK_CYCLES.L1D_L2",
brief_description:
"Cycles L1D and L2 locked",
public_description:
None,
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("LOAD_HIT_PRE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(76),
umask:
Tuple::One(1),
event_name:
"LOAD_HIT_PRE",
brief_description:
"Load operations conflicting with software prefetches",
public_description:
None,
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_RFO.LOCAL_CACHE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_RFO.LOCAL_CACHE",
brief_description:
"Offcore RFO requests satisfied by the LLC",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
1826,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_EXECUTED.PORT4_CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(177),
umask:
Tuple::One(16),
event_name:
"UOPS_EXECUTED.PORT4_CORE",
brief_description:
"Uops executed on port 4 (core count)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
true,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_TRANSACTIONS.L1D_WB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(240),
umask:
Tuple::One(16),
event_name:
"L2_TRANSACTIONS.L1D_WB",
brief_description:
"L1D writeback to L2 transactions",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT",
brief_description:
"Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
514,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DATA_IFETCH.REMOTE_CACHE_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DATA_IFETCH.REMOTE_CACHE_HIT",
brief_description:
"Offcore code or data read requests that HIT in a remote cache",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
4215,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_DATA_RD.LOCAL_CACHE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_DATA_RD.LOCAL_CACHE",
brief_description:
"Offcore demand data reads satisfied by the LLC",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
1793,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM",
brief_description:
"Offcore demand data reads satisfied by the LLC and HITM in a sibling core",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
1025,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_RFO.IO_CSR_MMIO",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_RFO.IO_CSR_MMIO",
brief_description:
"Offcore RFO requests satisfied by the IO, CSR, MMIO unit",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
32802,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_DATA_RD.REMOTE_CACHE_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_DATA_RD.REMOTE_CACHE_HITM",
brief_description:
"Offcore prefetch data reads that HITM in a remote cache",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
2064,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.COREWB.LLC_HIT_NO_OTHER_CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.COREWB.LLC_HIT_NO_OTHER_CORE",
brief_description:
"Offcore writebacks to the LLC and not found in a sibling core",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
264,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_DATA_RD.LOCAL_CACHE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_DATA_RD.LOCAL_CACHE",
brief_description:
"Offcore prefetch data reads satisfied by the LLC",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
1808,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_UNCORE_RETIRED.REMOTE_CACHE_LOCAL_HOME_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(15),
umask:
Tuple::One(8),
event_name:
"MEM_UNCORE_RETIRED.REMOTE_CACHE_LOCAL_HOME_HIT",
brief_description:
"Load instructions retired remote cache HIT data source (Precise Event)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
20000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("LARGE_ITLB.HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(130),
umask:
Tuple::One(1),
event_name:
"LARGE_ITLB.HIT",
brief_description:
"Large ITLB hit",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("LOAD_DISPATCH.ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(19),
umask:
Tuple::One(7),
event_name:
"LOAD_DISPATCH.ANY",
brief_description:
"All loads dispatched",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM",
brief_description:
"Offcore code reads satisfied by the LLC and HITM in a sibling core",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
1092,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("UOP_UNFUSION",
IntelPerformanceCounterDescription{event_code:
Tuple::One(219),
umask:
Tuple::One(1),
event_name:
"UOP_UNFUSION",
brief_description:
"Uop unfusions due to FP exceptions",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PREFETCH.LOCAL_CACHE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PREFETCH.LOCAL_CACHE",
brief_description:
"Offcore prefetch requests satisfied by the LLC",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
1904,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_LINES_OUT.DEMAND_DIRTY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(242),
umask:
Tuple::One(2),
event_name:
"L2_LINES_OUT.DEMAND_DIRTY",
brief_description:
"L2 modified lines evicted by a demand request",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("DTLB_LOAD_MISSES.PDE_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(8),
umask:
Tuple::One(32),
event_name:
"DTLB_LOAD_MISSES.PDE_MISS",
brief_description:
"DTLB load miss caused by low part of address",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_DATA_RQSTS.DEMAND.I_STATE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(38),
umask:
Tuple::One(1),
event_name:
"L2_DATA_RQSTS.DEMAND.I_STATE",
brief_description:
"L2 data demand loads in I state (misses)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_IFETCH.REMOTE_CACHE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_IFETCH.REMOTE_CACHE_DRAM",
brief_description:
"Offcore demand code reads satisfied by a remote cache or remote DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
14340,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_INST_EXEC.COND",
IntelPerformanceCounterDescription{event_code:
Tuple::One(136),
umask:
Tuple::One(1),
event_name:
"BR_INST_EXEC.COND",
brief_description:
"Conditional branch instructions executed",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_INST_EXEC.DIRECT_NEAR_CALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(136),
umask:
Tuple::One(16),
event_name:
"BR_INST_EXEC.DIRECT_NEAR_CALL",
brief_description:
"Unconditional call branches executed",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
20000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.COREWB.ANY_CACHE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.COREWB.ANY_CACHE_DRAM",
brief_description:
"Offcore writebacks to any cache or DRAM.",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
32520,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("ILD_STALL.IQ_FULL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(135),
umask:
Tuple::One(4),
event_name:
"ILD_STALL.IQ_FULL",
brief_description:
"Instruction Queue full stall cycles",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_RQSTS.LOADS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(36),
umask:
Tuple::One(3),
event_name:
"L2_RQSTS.LOADS",
brief_description:
"L2 requests",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DATA_IN.LOCAL_CACHE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DATA_IN.LOCAL_CACHE_DRAM",
brief_description:
"Offcore request = all data, response = local cache or dram",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
18227,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_DATA.LLC_HIT_NO_OTHER_CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_DATA.LLC_HIT_NO_OTHER_CORE",
brief_description:
"Offcore prefetch data requests satisfied by the LLC and not found in a sibling core",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
304,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_INST_RETIRED.STORES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(11),
umask:
Tuple::One(2),
event_name:
"MEM_INST_RETIRED.STORES",
brief_description:
"Instructions retired which contains a store (Precise Event)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.COREWB.REMOTE_CACHE_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.COREWB.REMOTE_CACHE_HITM",
brief_description:
"Offcore writebacks that HITM in a remote cache",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
2056,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_TRANSACTIONS.ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(240),
umask:
Tuple::One(128),
event_name:
"L2_TRANSACTIONS.ANY",
brief_description:
"All L2 transactions",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_REQUESTS_SQ_FULL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(178),
umask:
Tuple::One(1),
event_name:
"OFFCORE_REQUESTS_SQ_FULL",
brief_description:
"Offcore requests blocked due to Super Queue full",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_DATA.REMOTE_CACHE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_DATA.REMOTE_CACHE_DRAM",
brief_description:
"Offcore prefetch data requests satisfied by a remote cache or remote DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
14384,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_WRITE.RFO.MESI",
IntelPerformanceCounterDescription{event_code:
Tuple::One(39),
umask:
Tuple::One(15),
event_name:
"L2_WRITE.RFO.MESI",
brief_description:
"All L2 demand store RFOs",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_LINES_IN.ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(241),
umask:
Tuple::One(7),
event_name:
"L2_LINES_IN.ANY",
brief_description:
"L2 lines alloacated",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_DATA_RQSTS.DEMAND.S_STATE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(38),
umask:
Tuple::One(2),
event_name:
"L2_DATA_RQSTS.DEMAND.S_STATE",
brief_description:
"L2 data demand loads in S state",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_DATA.REMOTE_CACHE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_DATA.REMOTE_CACHE",
brief_description:
"Offcore demand data requests satisfied by a remote cache",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
6147,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_DATA.LOCAL_CACHE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_DATA.LOCAL_CACHE_DRAM",
brief_description:
"Offcore prefetch data requests satisfied by the LLC or local DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
18224,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_INST_RETIRED.NEAR_CALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(196),
umask:
Tuple::One(2),
event_name:
"BR_INST_RETIRED.NEAR_CALL",
brief_description:
"Retired near call instructions (Precise Event)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
20000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_RQSTS.RFO_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(36),
umask:
Tuple::One(4),
event_name:
"L2_RQSTS.RFO_HIT",
brief_description:
"L2 RFO hits",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_DATA_RQSTS.PREFETCH.S_STATE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(38),
umask:
Tuple::One(32),
event_name:
"L2_DATA_RQSTS.PREFETCH.S_STATE",
brief_description:
"L2 data prefetches in the S state",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L1D_PREFETCH.MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(78),
umask:
Tuple::One(2),
event_name:
"L1D_PREFETCH.MISS",
brief_description:
"L1D hardware prefetch misses",
public_description:
None,
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_EXECUTED.PORT3_CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(177),
umask:
Tuple::One(8),
event_name:
"UOPS_EXECUTED.PORT3_CORE",
brief_description:
"Uops executed on port 3 (core count)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
true,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_MISP_EXEC.TAKEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(137),
umask:
Tuple::One(64),
event_name:
"BR_MISP_EXEC.TAKEN",
brief_description:
"Mispredicted taken branches executed",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
20000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM",
brief_description:
"Offcore demand RFO requests satisfied by the LLC and HITM in a sibling core",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
1026,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_RFO.LLC_HIT_NO_OTHER_CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_RFO.LLC_HIT_NO_OTHER_CORE",
brief_description:
"Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
288,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PREFETCH.LOCAL_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PREFETCH.LOCAL_DRAM",
brief_description:
"Offcore prefetch requests satisfied by the local DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
16496,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("L1D_WB_L2.E_STATE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(40),
umask:
Tuple::One(4),
event_name:
"L1D_WB_L2.E_STATE",
brief_description:
"L1 writebacks to L2 in E state",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_STORE_RETIRED.DTLB_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(12),
umask:
Tuple::One(1),
event_name:
"MEM_STORE_RETIRED.DTLB_MISS",
brief_description:
"Retired stores that miss the DTLB (Precise Event)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("IO_TRANSACTIONS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(108),
umask:
Tuple::One(1),
event_name:
"IO_TRANSACTIONS",
brief_description:
"I/O transactions",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5",
IntelPerformanceCounterDescription{event_code:
Tuple::One(177),
umask:
Tuple::One(31),
event_name:
"UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5",
brief_description:
"Cycles no Uops issued on ports 0-4 (core count)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
true,
any_thread:
true,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_DATA.ANY_LLC_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_DATA.ANY_LLC_MISS",
brief_description:
"Offcore data reads that missed the LLC",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
63505,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("L1I.CYCLES_STALLED",
IntelPerformanceCounterDescription{event_code:
Tuple::One(128),
umask:
Tuple::One(4),
event_name:
"L1I.CYCLES_STALLED",
brief_description:
"L1I instruction fetch stall cycles",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("ITLB_MISSES.ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(133),
umask:
Tuple::One(1),
event_name:
"ITLB_MISSES.ANY",
brief_description:
"ITLB miss",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("SSEX_UOPS_RETIRED.PACKED_SINGLE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(199),
umask:
Tuple::One(1),
event_name:
"SSEX_UOPS_RETIRED.PACKED_SINGLE",
brief_description:
"SIMD Packed-Single Uops retired (Precise Event)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_DATA.ANY_LOCATION",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_DATA.ANY_LOCATION",
brief_description:
"All offcore data reads",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
65297,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("CPU_CLK_UNHALTED.THREAD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(0),
umask:
Tuple::One(0),
event_name:
"CPU_CLK_UNHALTED.THREAD",
brief_description:
"Cycles when thread is not halted (fixed counter)",
public_description:
None,
counter:
Counter::Fixed(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_DATA_RD.IO_CSR_MMIO",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_DATA_RD.IO_CSR_MMIO",
brief_description:
"Offcore demand data reads satisfied by the IO, CSR, MMIO unit",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
32769,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("SNOOP_RESPONSE.HITE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(184),
umask:
Tuple::One(2),
event_name:
"SNOOP_RESPONSE.HITE",
brief_description:
"Thread responded HITE to snoop",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DATA_IFETCH.LOCAL_CACHE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DATA_IFETCH.LOCAL_CACHE_DRAM",
brief_description:
"Offcore code or data read requests satisfied by the LLC or local DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
18295,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.COREWB.REMOTE_CACHE_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.COREWB.REMOTE_CACHE_HIT",
brief_description:
"Offcore writebacks that HIT in a remote cache",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
4104,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_MISP_EXEC.INDIRECT_NEAR_CALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(137),
umask:
Tuple::One(32),
event_name:
"BR_MISP_EXEC.INDIRECT_NEAR_CALL",
brief_description:
"Mispredicted indirect call branches executed",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MACHINE_CLEARS.CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(195),
umask:
Tuple::One(1),
event_name:
"MACHINE_CLEARS.CYCLES",
brief_description:
"Cycles machine clear asserted",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
20000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_RFO.ANY_CACHE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_RFO.ANY_CACHE_DRAM",
brief_description:
"Offcore demand RFO requests satisfied by any cache or DRAM.",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
32514,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_DATA.LOCAL_CACHE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_DATA.LOCAL_CACHE_DRAM",
brief_description:
"Offcore demand data requests satisfied by the LLC or local DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
18179,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM",
brief_description:
"Offcore demand code reads satisfied by the LLC and HITM in a sibling core",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
1028,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_DATA_RQSTS.PREFETCH.I_STATE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(38),
umask:
Tuple::One(16),
event_name:
"L2_DATA_RQSTS.PREFETCH.I_STATE",
brief_description:
"L2 data prefetches in the I state (misses)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("FP_ASSIST.OUTPUT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(247),
umask:
Tuple::One(2),
event_name:
"FP_ASSIST.OUTPUT",
brief_description:
"X87 Floating point assists for invalid output value (Precise Event)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
20000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_DATA.ANY_CACHE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_DATA.ANY_CACHE_DRAM",
brief_description:
"Offcore prefetch data requests satisfied by any cache or DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
32560,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_REQUESTS.L1D_WRITEBACK",
IntelPerformanceCounterDescription{event_code:
Tuple::One(176),
umask:
Tuple::One(64),
event_name:
"OFFCORE_REQUESTS.L1D_WRITEBACK",
brief_description:
"Offcore L1 data cache writebacks",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_DATA.LLC_HIT_OTHER_CORE_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_DATA.LLC_HIT_OTHER_CORE_HITM",
brief_description:
"Offcore data reads satisfied by the LLC and HITM in a sibling core",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
1041,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_RFO.REMOTE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_RFO.REMOTE_DRAM",
brief_description:
"Offcore RFO requests satisfied by a remote DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
8226,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_IFETCH.ANY_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_IFETCH.ANY_DRAM",
brief_description:
"Offcore prefetch code reads satisfied by any DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
24640,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_MISP_EXEC.COND",
IntelPerformanceCounterDescription{event_code:
Tuple::One(137),
umask:
Tuple::One(1),
event_name:
"BR_MISP_EXEC.COND",
brief_description:
"Mispredicted conditional branches executed",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
20000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_TRANSACTIONS.PREFETCH",
IntelPerformanceCounterDescription{event_code:
Tuple::One(240),
umask:
Tuple::One(8),
event_name:
"L2_TRANSACTIONS.PREFETCH",
brief_description:
"L2 prefetch transactions",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_WRITE.RFO.S_STATE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(39),
umask:
Tuple::One(2),
event_name:
"L2_WRITE.RFO.S_STATE",
brief_description:
"L2 demand store RFOs in S state",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_DECODED.ESP_SYNC",
IntelPerformanceCounterDescription{event_code:
Tuple::One(209),
umask:
Tuple::One(8),
event_name:
"UOPS_DECODED.ESP_SYNC",
brief_description:
"Stack pointer sync operations",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_DATA.REMOTE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_DATA.REMOTE_DRAM",
brief_description:
"Offcore prefetch data requests satisfied by a remote DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
8240,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_RFO.ANY_LOCATION",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_RFO.ANY_LOCATION",
brief_description:
"All offcore prefetch RFO requests",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
65312,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("SSEX_UOPS_RETIRED.SCALAR_SINGLE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(199),
umask:
Tuple::One(2),
event_name:
"SSEX_UOPS_RETIRED.SCALAR_SINGLE",
brief_description:
"SIMD Scalar-Single Uops retired (Precise Event)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.COREWB.ANY_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.COREWB.ANY_DRAM",
brief_description:
"Offcore writebacks to any DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
24584,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.OTHER.REMOTE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.OTHER.REMOTE_DRAM",
brief_description:
"Offcore other requests satisfied by a remote DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
8320,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_INST_RETIRED.CONDITIONAL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(196),
umask:
Tuple::One(1),
event_name:
"BR_INST_RETIRED.CONDITIONAL",
brief_description:
"Retired conditional branch instructions (Precise Event)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("SQ_MISC.SPLIT_LOCK",
IntelPerformanceCounterDescription{event_code:
Tuple::One(244),
umask:
Tuple::One(16),
event_name:
"SQ_MISC.SPLIT_LOCK",
brief_description:
"Super Queue lock splits across a cache line",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.COREWB.ANY_LLC_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.COREWB.ANY_LLC_MISS",
brief_description:
"Offcore writebacks that missed the LLC",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
63496,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_RFO.ANY_CACHE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_RFO.ANY_CACHE_DRAM",
brief_description:
"Offcore prefetch RFO requests satisfied by any cache or DRAM.",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
32544,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("ES_REG_RENAMES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(213),
umask:
Tuple::One(1),
event_name:
"ES_REG_RENAMES",
brief_description:
"ES segment renames",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_DATA_RD.REMOTE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_DATA_RD.REMOTE_DRAM",
brief_description:
"Offcore prefetch data reads satisfied by a remote DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
8208,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("L1D_PREFETCH.TRIGGERS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(78),
umask:
Tuple::One(4),
event_name:
"L1D_PREFETCH.TRIGGERS",
brief_description:
"L1D hardware prefetch requests triggered",
public_description:
None,
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_DATA.REMOTE_CACHE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_DATA.REMOTE_CACHE",
brief_description:
"Offcore data reads satisfied by a remote cache",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
6161,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_DATA_RD.REMOTE_CACHE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_DATA_RD.REMOTE_CACHE",
brief_description:
"Offcore prefetch data reads satisfied by a remote cache",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
6160,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_IFETCH.LOCAL_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_IFETCH.LOCAL_DRAM",
brief_description:
"Offcore code reads satisfied by the local DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
16452,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_IFETCH.ANY_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_IFETCH.ANY_DRAM",
brief_description:
"Offcore code reads satisfied by any DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
24644,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_INST_RETIRED.ALL_BRANCHES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(196),
umask:
Tuple::One(4),
event_name:
"BR_INST_RETIRED.ALL_BRANCHES",
brief_description:
"Retired branch instructions (Precise Event)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192",
IntelPerformanceCounterDescription{event_code:
Tuple::One(11),
umask:
Tuple::One(16),
event_name:
"MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192",
brief_description:
"Memory instructions retired above 8192 clocks (Precise Event)",
public_description:
None,
counter:
Counter::Programmable(8),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
10,
msr_index:
MSRIndex::One(246),
msr_value:
8192,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOnly,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("SIMD_INT_64.UNPACK",
IntelPerformanceCounterDescription{event_code:
Tuple::One(253),
umask:
Tuple::One(8),
event_name:
"SIMD_INT_64.UNPACK",
brief_description:
"SIMD integer 64 bit unpack operations",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_IFETCH.REMOTE_CACHE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_IFETCH.REMOTE_CACHE_DRAM",
brief_description:
"Offcore prefetch code reads satisfied by a remote cache or remote DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
14400,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("FP_ASSIST.ALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(247),
umask:
Tuple::One(1),
event_name:
"FP_ASSIST.ALL",
brief_description:
"X87 Floating point assists (Precise Event)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
20000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_DATA.LOCAL_CACHE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_DATA.LOCAL_CACHE_DRAM",
brief_description:
"Offcore data reads satisfied by the LLC or local DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
18193,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT",
brief_description:
"Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
576,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_DATA.ANY_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_DATA.ANY_DRAM",
brief_description:
"Offcore prefetch data requests satisfied by any DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
24624,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("L1D_CACHE_LD.S_STATE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(64),
umask:
Tuple::One(2),
event_name:
"L1D_CACHE_LD.S_STATE",
brief_description:
"L1 data cache read in S state",
public_description:
None,
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_TRANSACTIONS.FILL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(240),
umask:
Tuple::One(32),
event_name:
"L2_TRANSACTIONS.FILL",
brief_description:
"L2 fill transactions",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.OTHER.ANY_CACHE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.OTHER.ANY_CACHE_DRAM",
brief_description:
"Offcore other requests satisfied by any cache or DRAM.",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
32640,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_IFETCH.REMOTE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_IFETCH.REMOTE_DRAM",
brief_description:
"Offcore code reads satisfied by a remote DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
8260,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_INST_EXEC.INDIRECT_NON_CALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(136),
umask:
Tuple::One(4),
event_name:
"BR_INST_EXEC.INDIRECT_NON_CALL",
brief_description:
"Indirect non call branches executed",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
20000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DATA_IN.LLC_HIT_NO_OTHER_CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DATA_IN.LLC_HIT_NO_OTHER_CORE",
brief_description:
"Offcore data reads, RFO\'s and prefetches statisfied by the LLC and not found in a sibling core",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
307,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_DATA_RQSTS.PREFETCH.M_STATE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(38),
umask:
Tuple::One(128),
event_name:
"L2_DATA_RQSTS.PREFETCH.M_STATE",
brief_description:
"L2 data prefetches in M state",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_LOAD_RETIRED.L2_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(203),
umask:
Tuple::One(2),
event_name:
"MEM_LOAD_RETIRED.L2_HIT",
brief_description:
"Retired loads that hit the L2 cache (Precise Event)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_IFETCH.IO_CSR_MMIO",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_IFETCH.IO_CSR_MMIO",
brief_description:
"Offcore code reads satisfied by the IO, CSR, MMIO unit",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
32836,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE",
brief_description:
"Offcore demand data requests satisfied by the LLC and not found in a sibling core",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
259,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("STORE_BLOCKS.AT_RET",
IntelPerformanceCounterDescription{event_code:
Tuple::One(6),
umask:
Tuple::One(4),
event_name:
"STORE_BLOCKS.AT_RET",
brief_description:
"Loads delayed with at-Retirement block code",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DATA_IFETCH.ANY_LLC_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DATA_IFETCH.ANY_LLC_MISS",
brief_description:
"Offcore code or data read requests that missed the LLC",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
63607,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_ISSUED.ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(14),
umask:
Tuple::One(1),
event_name:
"UOPS_ISSUED.ANY",
brief_description:
"Uops issued",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("FP_ASSIST.INPUT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(247),
umask:
Tuple::One(4),
event_name:
"FP_ASSIST.INPUT",
brief_description:
"X87 Floating poiint assists for invalid input value (Precise Event)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
20000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT",
brief_description:
"Offcore code or data read requests satisfied by the LLC and HIT in a sibling core",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
631,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.OTHER.ANY_LOCATION",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.OTHER.ANY_LOCATION",
brief_description:
"All offcore other requests",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
65408,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_DATA.LOCAL_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_DATA.LOCAL_DRAM",
brief_description:
"Offcore demand data requests satisfied by the local DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
16387,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("L1D_CACHE_LD.M_STATE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(64),
umask:
Tuple::One(8),
event_name:
"L1D_CACHE_LD.M_STATE",
brief_description:
"L1 data cache read in M state",
public_description:
None,
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PREFETCH.REMOTE_CACHE_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PREFETCH.REMOTE_CACHE_HITM",
brief_description:
"Offcore prefetch requests that HITM in a remote cache",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
2160,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_IFETCH.REMOTE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_IFETCH.REMOTE_DRAM",
brief_description:
"Offcore demand code reads satisfied by a remote DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
8196,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_RFO.LLC_HIT_NO_OTHER_CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_RFO.LLC_HIT_NO_OTHER_CORE",
brief_description:
"Offcore RFO requests satisfied by the LLC and not found in a sibling core",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
290,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("RAT_STALLS.SCOREBOARD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(210),
umask:
Tuple::One(8),
event_name:
"RAT_STALLS.SCOREBOARD",
brief_description:
"Scoreboard stall cycles",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("SIMD_INT_128.SHUFFLE_MOVE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(18),
umask:
Tuple::One(64),
event_name:
"SIMD_INT_128.SHUFFLE_MOVE",
brief_description:
"128 bit SIMD integer shuffle/move operations",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_IFETCH.ANY_LLC_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_IFETCH.ANY_LLC_MISS",
brief_description:
"Offcore prefetch code reads that missed the LLC",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
63552,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("SIMD_INT_128.PACKED_ARITH",
IntelPerformanceCounterDescription{event_code:
Tuple::One(18),
umask:
Tuple::One(32),
event_name:
"SIMD_INT_128.PACKED_ARITH",
brief_description:
"128 bit SIMD integer arithmetic operations",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_EXECUTED.PORT015",
IntelPerformanceCounterDescription{event_code:
Tuple::One(177),
umask:
Tuple::One(64),
event_name:
"UOPS_EXECUTED.PORT015",
brief_description:
"Uops issued on ports 0, 1 or 5",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_LINES_IN.S_STATE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(241),
umask:
Tuple::One(2),
event_name:
"L2_LINES_IN.S_STATE",
brief_description:
"L2 lines allocated in the S state",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("ITLB_MISS_RETIRED",
IntelPerformanceCounterDescription{event_code:
Tuple::One(200),
umask:
Tuple::One(32),
event_name:
"ITLB_MISS_RETIRED",
brief_description:
"Retired instructions that missed the ITLB (Precise Event)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("INST_RETIRED.TOTAL_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(192),
umask:
Tuple::One(1),
event_name:
"INST_RETIRED.TOTAL_CYCLES",
brief_description:
"Total cycles (Precise Event)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
16,
invert:
true,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DATA_IFETCH.ANY_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DATA_IFETCH.ANY_DRAM",
brief_description:
"Offcore code or data read requests satisfied by any DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
24695,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128",
IntelPerformanceCounterDescription{event_code:
Tuple::One(11),
umask:
Tuple::One(16),
event_name:
"MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128",
brief_description:
"Memory instructions retired above 128 clocks (Precise Event)",
public_description:
None,
counter:
Counter::Programmable(8),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
1000,
msr_index:
MSRIndex::One(246),
msr_value:
128,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOnly,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("INST_DECODED.DEC0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(24),
umask:
Tuple::One(1),
event_name:
"INST_DECODED.DEC0",
brief_description:
"Instructions that must be decoded by decoder 0",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DATA_IFETCH.LOCAL_CACHE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DATA_IFETCH.LOCAL_CACHE",
brief_description:
"Offcore code or data read requests satisfied by the LLC",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
1911,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_REQUEST.LOCAL_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_REQUEST.LOCAL_DRAM",
brief_description:
"Offcore requests satisfied by the local DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
16639,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("LOAD_DISPATCH.RS_DELAYED",
IntelPerformanceCounterDescription{event_code:
Tuple::One(19),
umask:
Tuple::One(2),
event_name:
"LOAD_DISPATCH.RS_DELAYED",
brief_description:
"Loads dispatched from stage 305",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_INST_EXEC.RETURN_NEAR",
IntelPerformanceCounterDescription{event_code:
Tuple::One(136),
umask:
Tuple::One(8),
event_name:
"BR_INST_EXEC.RETURN_NEAR",
brief_description:
"Indirect return branches executed",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
20000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_RFO.LOCAL_CACHE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_RFO.LOCAL_CACHE",
brief_description:
"Offcore demand RFO requests satisfied by the LLC",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
1794,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_RFO.REMOTE_CACHE_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_RFO.REMOTE_CACHE_HIT",
brief_description:
"Offcore prefetch RFO requests that HIT in a remote cache",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
4128,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("L1D_CACHE_LD.I_STATE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(64),
umask:
Tuple::One(1),
event_name:
"L1D_CACHE_LD.I_STATE",
brief_description:
"L1 data cache read in I state (misses)",
public_description:
None,
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DATA_IFETCH.REMOTE_CACHE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DATA_IFETCH.REMOTE_CACHE_DRAM",
brief_description:
"Offcore code or data read requests satisfied by a remote cache or remote DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
14455,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("L1D_PREFETCH.REQUESTS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(78),
umask:
Tuple::One(1),
event_name:
"L1D_PREFETCH.REQUESTS",
brief_description:
"L1D hardware prefetch requests",
public_description:
None,
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_DATA.LLC_HIT_OTHER_CORE_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_DATA.LLC_HIT_OTHER_CORE_HITM",
brief_description:
"Offcore prefetch data requests satisfied by the LLC and HITM in a sibling core",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
1072,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_DATA.ANY_LLC_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_DATA.ANY_LLC_MISS",
brief_description:
"Offcore demand data requests that missed the LLC",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
63491,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_IFETCH.REMOTE_CACHE_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_IFETCH.REMOTE_CACHE_HITM",
brief_description:
"Offcore prefetch code reads that HITM in a remote cache",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
2112,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("DTLB_LOAD_MISSES.ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(8),
umask:
Tuple::One(1),
event_name:
"DTLB_LOAD_MISSES.ANY",
brief_description:
"DTLB load misses",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_RQSTS.LD_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(36),
umask:
Tuple::One(1),
event_name:
"L2_RQSTS.LD_HIT",
brief_description:
"L2 load hits",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_REQUEST.LOCAL_CACHE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_REQUEST.LOCAL_CACHE",
brief_description:
"Offcore requests satisfied by the LLC",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
2047,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("RESOURCE_STALLS.LOAD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(162),
umask:
Tuple::One(2),
event_name:
"RESOURCE_STALLS.LOAD",
brief_description:
"Load buffer stall cycles",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_DATA_RQSTS.DEMAND.MESI",
IntelPerformanceCounterDescription{event_code:
Tuple::One(38),
umask:
Tuple::One(15),
event_name:
"L2_DATA_RQSTS.DEMAND.MESI",
brief_description:
"L2 data demand requests",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("RESOURCE_STALLS.MXCSR",
IntelPerformanceCounterDescription{event_code:
Tuple::One(162),
umask:
Tuple::One(64),
event_name:
"RESOURCE_STALLS.MXCSR",
brief_description:
"MXCSR rename stall cycles",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_REQUEST.REMOTE_CACHE_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_REQUEST.REMOTE_CACHE_HIT",
brief_description:
"Offcore requests that HIT in a remote cache",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
4351,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM",
brief_description:
"Offcore prefetch code reads satisfied by the LLC and HITM in a sibling core",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
1088,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_EXECUTED.CORE_ACTIVE_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(177),
umask:
Tuple::One(63),
event_name:
"UOPS_EXECUTED.CORE_ACTIVE_CYCLES",
brief_description:
"Cycles Uops executed on any port (core count)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
false,
any_thread:
true,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PREFETCH.LOCAL_CACHE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PREFETCH.LOCAL_CACHE_DRAM",
brief_description:
"Offcore prefetch requests satisfied by the LLC or local DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
18288,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_DECODED.MS_CYCLES_ACTIVE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(209),
umask:
Tuple::One(2),
event_name:
"UOPS_DECODED.MS_CYCLES_ACTIVE",
brief_description:
"Uops decoded by Microcode Sequencer",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_IFETCH.REMOTE_CACHE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_IFETCH.REMOTE_CACHE_DRAM",
brief_description:
"Offcore code reads satisfied by a remote cache or remote DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
14404,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_TRANSACTIONS.RFO",
IntelPerformanceCounterDescription{event_code:
Tuple::One(240),
umask:
Tuple::One(2),
event_name:
"L2_TRANSACTIONS.RFO",
brief_description:
"L2 RFO transactions",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L1D.M_EVICT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(81),
umask:
Tuple::One(4),
event_name:
"L1D.M_EVICT",
brief_description:
"L1D cache lines replaced in M state",
public_description:
None,
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PREFETCH.LLC_HIT_OTHER_CORE_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PREFETCH.LLC_HIT_OTHER_CORE_HIT",
brief_description:
"Offcore prefetch requests satisfied by the LLC and HIT in a sibling core",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
624,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("L1D_CACHE_LOCK.M_STATE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(66),
umask:
Tuple::One(8),
event_name:
"L1D_CACHE_LOCK.M_STATE",
brief_description:
"L1 data cache load locks in M state",
public_description:
None,
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_DATA.LOCAL_CACHE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_DATA.LOCAL_CACHE",
brief_description:
"Offcore prefetch data requests satisfied by the LLC",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
1840,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("TWO_UOP_INSTS_DECODED",
IntelPerformanceCounterDescription{event_code:
Tuple::One(25),
umask:
Tuple::One(1),
event_name:
"TWO_UOP_INSTS_DECODED",
brief_description:
"Two Uop instructions decoded",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PREFETCH.REMOTE_CACHE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PREFETCH.REMOTE_CACHE_DRAM",
brief_description:
"Offcore prefetch requests satisfied by a remote cache or remote DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
14448,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_DATA_RD.ANY_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_DATA_RD.ANY_DRAM",
brief_description:
"Offcore prefetch data reads satisfied by any DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
24592,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("SSEX_UOPS_RETIRED.PACKED_DOUBLE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(199),
umask:
Tuple::One(4),
event_name:
"SSEX_UOPS_RETIRED.PACKED_DOUBLE",
brief_description:
"SIMD Packed-Double Uops retired (Precise Event)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_RETIRED.ACTIVE_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(194),
umask:
Tuple::One(1),
event_name:
"UOPS_RETIRED.ACTIVE_CYCLES",
brief_description:
"Cycles Uops are being retired",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_RFO.LOCAL_CACHE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_RFO.LOCAL_CACHE_DRAM",
brief_description:
"Offcore prefetch RFO requests satisfied by the LLC or local DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
18208,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("BPU_CLEARS.EARLY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(232),
umask:
Tuple::One(1),
event_name:
"BPU_CLEARS.EARLY",
brief_description:
"Early Branch Prediciton Unit clears",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_DECODED.STALL_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(209),
umask:
Tuple::One(1),
event_name:
"UOPS_DECODED.STALL_CYCLES",
brief_description:
"Cycles no Uops are decoded",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
true,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_DATA_RD.REMOTE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_DATA_RD.REMOTE_DRAM",
brief_description:
"Offcore demand data reads satisfied by a remote DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
8193,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_UNCORE_RETIRED.REMOTE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(15),
umask:
Tuple::One(16),
event_name:
"MEM_UNCORE_RETIRED.REMOTE_DRAM",
brief_description:
"Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
10000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_INST_RETIRED.NEAR_CALL_R3",
IntelPerformanceCounterDescription{event_code:
Tuple::One(196),
umask:
Tuple::One(2),
event_name:
"BR_INST_RETIRED.NEAR_CALL_R3",
brief_description:
"Retired near call instructions Ring 3 only(Precise Event)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
20000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE",
brief_description:
"Offcore demand RFO requests satisfied by the LLC and not found in a sibling core",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
258,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DATA_IFETCH.REMOTE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DATA_IFETCH.REMOTE_DRAM",
brief_description:
"Offcore code or data read requests satisfied by a remote DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
8311,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_IFETCH.ANY_CACHE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_IFETCH.ANY_CACHE_DRAM",
brief_description:
"Offcore code reads satisfied by any cache or DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
32580,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_RFO.ANY_LLC_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_RFO.ANY_LLC_MISS",
brief_description:
"Offcore RFO requests that missed the LLC",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
63522,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_DATA.REMOTE_CACHE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_DATA.REMOTE_CACHE_DRAM",
brief_description:
"Offcore demand data requests satisfied by a remote cache or remote DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
14339,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_REQUEST.REMOTE_CACHE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_REQUEST.REMOTE_CACHE_DRAM",
brief_description:
"Offcore requests satisfied by a remote cache or remote DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
14591,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("L1D.M_REPL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(81),
umask:
Tuple::One(2),
event_name:
"L1D.M_REPL",
brief_description:
"L1D cache lines allocated in the M state",
public_description:
None,
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_RFO.REMOTE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_RFO.REMOTE_DRAM",
brief_description:
"Offcore demand RFO requests satisfied by a remote DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
8194,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("SSEX_UOPS_RETIRED.VECTOR_INTEGER",
IntelPerformanceCounterDescription{event_code:
Tuple::One(199),
umask:
Tuple::One(16),
event_name:
"SSEX_UOPS_RETIRED.VECTOR_INTEGER",
brief_description:
"SIMD Vector Integer Uops retired (Precise Event)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_RQSTS.LD_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(36),
umask:
Tuple::One(2),
event_name:
"L2_RQSTS.LD_MISS",
brief_description:
"L2 load misses",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64",
IntelPerformanceCounterDescription{event_code:
Tuple::One(11),
umask:
Tuple::One(16),
event_name:
"MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64",
brief_description:
"Memory instructions retired above 64 clocks (Precise Event)",
public_description:
None,
counter:
Counter::Programmable(8),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000,
msr_index:
MSRIndex::One(246),
msr_value:
64,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOnly,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("BPU_MISSED_CALL_RET",
IntelPerformanceCounterDescription{event_code:
Tuple::One(229),
umask:
Tuple::One(1),
event_name:
"BPU_MISSED_CALL_RET",
brief_description:
"Branch prediction unit missed call or return",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE",
brief_description:
"Offcore demand code reads satisfied by the LLC and not found in a sibling core",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
260,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_DATA_RD.ANY_CACHE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_DATA_RD.ANY_CACHE_DRAM",
brief_description:
"Offcore demand data reads satisfied by any cache or DRAM.",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
32513,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_DATA_RQSTS.ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(38),
umask:
Tuple::One(255),
event_name:
"L2_DATA_RQSTS.ANY",
brief_description:
"All L2 data requests",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.COREWB.LOCAL_CACHE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.COREWB.LOCAL_CACHE_DRAM",
brief_description:
"Offcore writebacks to the LLC or local DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
18184,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_DATA.LOCAL_CACHE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_DATA.LOCAL_CACHE",
brief_description:
"Offcore data reads satisfied by the LLC",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
1809,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_LOAD_RETIRED.DTLB_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(203),
umask:
Tuple::One(128),
event_name:
"MEM_LOAD_RETIRED.DTLB_MISS",
brief_description:
"Retired loads that miss the DTLB (Precise Event)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_RFO.LLC_HIT_OTHER_CORE_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_RFO.LLC_HIT_OTHER_CORE_HIT",
brief_description:
"Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
544,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("ILD_STALL.LCP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(135),
umask:
Tuple::One(1),
event_name:
"ILD_STALL.LCP",
brief_description:
"Length Change Prefix stall cycles",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_RETIRED.ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(194),
umask:
Tuple::One(1),
event_name:
"UOPS_RETIRED.ANY",
brief_description:
"Uops retired (Precise Event)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5",
IntelPerformanceCounterDescription{event_code:
Tuple::One(177),
umask:
Tuple::One(31),
event_name:
"UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5",
brief_description:
"Cycles Uops executed on ports 0-4 (core count)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
false,
any_thread:
true,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DATA_IN.ANY_CACHE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DATA_IN.ANY_CACHE_DRAM",
brief_description:
"Offcore request = all data, response = any cache_dram",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
32563,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_IFETCH.IO_CSR_MMIO",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_IFETCH.IO_CSR_MMIO",
brief_description:
"Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
32832,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("L1D_CACHE_LOCK.E_STATE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(66),
umask:
Tuple::One(4),
event_name:
"L1D_CACHE_LOCK.E_STATE",
brief_description:
"L1 data cache load locks in E state",
public_description:
None,
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_WRITE.LOCK.MESI",
IntelPerformanceCounterDescription{event_code:
Tuple::One(39),
umask:
Tuple::One(240),
event_name:
"L2_WRITE.LOCK.MESI",
brief_description:
"All demand L2 lock RFOs",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_DATA.LLC_HIT_OTHER_CORE_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_DATA.LLC_HIT_OTHER_CORE_HIT",
brief_description:
"Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
560,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_RETIRED.STALL_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(194),
umask:
Tuple::One(1),
event_name:
"UOPS_RETIRED.STALL_CYCLES",
brief_description:
"Cycles Uops are not retiring (Precise Event)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
true,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_IFETCH.REMOTE_CACHE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_IFETCH.REMOTE_CACHE",
brief_description:
"Offcore code reads satisfied by a remote cache",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
6212,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("BACLEAR.BAD_TARGET",
IntelPerformanceCounterDescription{event_code:
Tuple::One(230),
umask:
Tuple::One(2),
event_name:
"BACLEAR.BAD_TARGET",
brief_description:
"BACLEAR asserted with bad target address",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_ISSUED.FUSED",
IntelPerformanceCounterDescription{event_code:
Tuple::One(14),
umask:
Tuple::One(2),
event_name:
"UOPS_ISSUED.FUSED",
brief_description:
"Fused Uops issued",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_RFO.REMOTE_CACHE_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_RFO.REMOTE_CACHE_HITM",
brief_description:
"Offcore demand RFO requests that HITM in a remote cache",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
2050,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.COREWB.IO_CSR_MMIO",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.COREWB.IO_CSR_MMIO",
brief_description:
"Offcore writebacks to the IO, CSR, MMIO unit.",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
32776,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("SIMD_INT_64.PACKED_MPY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(253),
umask:
Tuple::One(1),
event_name:
"SIMD_INT_64.PACKED_MPY",
brief_description:
"SIMD integer 64 bit packed multiply operations",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.COREWB.REMOTE_CACHE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.COREWB.REMOTE_CACHE",
brief_description:
"Offcore writebacks to a remote cache",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
6152,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DATA_IFETCH.ANY_LOCATION",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DATA_IFETCH.ANY_LOCATION",
brief_description:
"All offcore code or data read requests",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
65399,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("SIMD_INT_64.PACKED_ARITH",
IntelPerformanceCounterDescription{event_code:
Tuple::One(253),
umask:
Tuple::One(32),
event_name:
"SIMD_INT_64.PACKED_ARITH",
brief_description:
"SIMD integer 64 bit arithmetic operations",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_LOAD_RETIRED.L1D_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(203),
umask:
Tuple::One(1),
event_name:
"MEM_LOAD_RETIRED.L1D_HIT",
brief_description:
"Retired loads that hit the L1 data cache (Precise Event)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_IFETCH.LOCAL_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_IFETCH.LOCAL_DRAM",
brief_description:
"Offcore prefetch code reads satisfied by the local DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
16448,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("L1D_CACHE_LD.MESI",
IntelPerformanceCounterDescription{event_code:
Tuple::One(64),
umask:
Tuple::One(15),
event_name:
"L1D_CACHE_LD.MESI",
brief_description:
"L1 data cache reads",
public_description:
None,
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("ILD_STALL.ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(135),
umask:
Tuple::One(15),
event_name:
"ILD_STALL.ANY",
brief_description:
"Any Instruction Length Decoder stall cycles",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_EXECUTED.PORT0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(177),
umask:
Tuple::One(1),
event_name:
"UOPS_EXECUTED.PORT0",
brief_description:
"Uops executed on port 0",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_ISSUED.CYCLES_ALL_THREADS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(14),
umask:
Tuple::One(1),
event_name:
"UOPS_ISSUED.CYCLES_ALL_THREADS",
brief_description:
"Cycles Uops were issued on either thread",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
false,
any_thread:
true,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_IFETCH.ANY_LOCATION",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_IFETCH.ANY_LOCATION",
brief_description:
"All offcore code reads",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
65348,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DATA_IN.ANY_LLC_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DATA_IN.ANY_LLC_MISS",
brief_description:
"Offcore request = all data, response = any LLC miss",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
63539,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.OTHER.IO_CSR_MMIO",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.OTHER.IO_CSR_MMIO",
brief_description:
"Offcore other requests satisfied by the IO, CSR, MMIO unit",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
32896,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_DATA_RD.ANY_CACHE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_DATA_RD.ANY_CACHE_DRAM",
brief_description:
"Offcore prefetch data reads satisfied by any cache or DRAM.",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
32528,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("BACLEAR_FORCE_IQ",
IntelPerformanceCounterDescription{event_code:
Tuple::One(167),
umask:
Tuple::One(1),
event_name:
"BACLEAR_FORCE_IQ",
brief_description:
"Instruction queue forced BACLEAR",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_RFO.LOCAL_CACHE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_RFO.LOCAL_CACHE_DRAM",
brief_description:
"Offcore RFO requests satisfied by the LLC or local DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
18210,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_IFETCH.REMOTE_CACHE_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_IFETCH.REMOTE_CACHE_HITM",
brief_description:
"Offcore code reads that HITM in a remote cache",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
2116,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PREFETCH.ANY_LLC_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PREFETCH.ANY_LLC_MISS",
brief_description:
"Offcore prefetch requests that missed the LLC",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
63600,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512",
IntelPerformanceCounterDescription{event_code:
Tuple::One(11),
umask:
Tuple::One(16),
event_name:
"MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512",
brief_description:
"Memory instructions retired above 512 clocks (Precise Event)",
public_description:
None,
counter:
Counter::Programmable(8),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200,
msr_index:
MSRIndex::One(246),
msr_value:
512,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOnly,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.OTHER.LLC_HIT_NO_OTHER_CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.OTHER.LLC_HIT_NO_OTHER_CORE",
brief_description:
"Offcore other requests satisfied by the LLC and not found in a sibling core",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
384,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_EXECUTED.PORT2_CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(177),
umask:
Tuple::One(4),
event_name:
"UOPS_EXECUTED.PORT2_CORE",
brief_description:
"Uops executed on port 2 (core count)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
true,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_RFO.REMOTE_CACHE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_RFO.REMOTE_CACHE_DRAM",
brief_description:
"Offcore demand RFO requests satisfied by a remote cache or remote DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
14338,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("ARITH.DIV",
IntelPerformanceCounterDescription{event_code:
Tuple::One(20),
umask:
Tuple::One(1),
event_name:
"ARITH.DIV",
brief_description:
"Divide Operations executed",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
true,
any_thread:
false,
edge_detect:
true,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_IFETCH.ANY_LLC_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_IFETCH.ANY_LLC_MISS",
brief_description:
"Offcore demand code reads that missed the LLC",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
63492,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_LOAD_RETIRED.LLC_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(203),
umask:
Tuple::One(16),
event_name:
"MEM_LOAD_RETIRED.LLC_MISS",
brief_description:
"Retired loads that miss the LLC cache (Precise Event)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
10000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_DATA.REMOTE_CACHE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_DATA.REMOTE_CACHE_DRAM",
brief_description:
"Offcore data reads satisfied by a remote cache or remote DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
14353,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_EXECUTED.PORT1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(177),
umask:
Tuple::One(2),
event_name:
"UOPS_EXECUTED.PORT1",
brief_description:
"Uops executed on port 1",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_RQSTS.IFETCH_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(36),
umask:
Tuple::One(32),
event_name:
"L2_RQSTS.IFETCH_MISS",
brief_description:
"L2 instruction fetch misses",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_RFO.IO_CSR_MMIO",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_RFO.IO_CSR_MMIO",
brief_description:
"Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
32800,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_IFETCH.LOCAL_CACHE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_IFETCH.LOCAL_CACHE",
brief_description:
"Offcore code reads satisfied by the LLC",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
1860,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("ITLB_MISSES.WALK_COMPLETED",
IntelPerformanceCounterDescription{event_code:
Tuple::One(133),
umask:
Tuple::One(2),
event_name:
"ITLB_MISSES.WALK_COMPLETED",
brief_description:
"ITLB miss page walks",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_RETIRED.TOTAL_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(194),
umask:
Tuple::One(1),
event_name:
"UOPS_RETIRED.TOTAL_CYCLES",
brief_description:
"Total cycles using precise uop retired event (Precise Event)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
16,
invert:
true,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.COREWB.LLC_HIT_OTHER_CORE_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.COREWB.LLC_HIT_OTHER_CORE_HITM",
brief_description:
"Offcore writebacks to the LLC and HITM in a sibling core",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
1032,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("DTLB_MISSES.WALK_COMPLETED",
IntelPerformanceCounterDescription{event_code:
Tuple::One(73),
umask:
Tuple::One(2),
event_name:
"DTLB_MISSES.WALK_COMPLETED",
brief_description:
"DTLB miss page walks",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_EXECUTED.CORE_STALL_COUNT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(177),
umask:
Tuple::One(63),
event_name:
"UOPS_EXECUTED.CORE_STALL_COUNT",
brief_description:
"Uops executed on any port (core count)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
true,
any_thread:
true,
edge_detect:
true,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("LOAD_DISPATCH.MOB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(19),
umask:
Tuple::One(4),
event_name:
"LOAD_DISPATCH.MOB",
brief_description:
"Loads dispatched from the MOB",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.OTHER.REMOTE_CACHE_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.OTHER.REMOTE_CACHE_HIT",
brief_description:
"Offcore other requests that HIT in a remote cache",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
4224,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("SQ_FULL_STALL_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(246),
umask:
Tuple::One(1),
event_name:
"SQ_FULL_STALL_CYCLES",
brief_description:
"Super Queue full stall cycles",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_RETIRED.RETIRE_SLOTS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(194),
umask:
Tuple::One(2),
event_name:
"UOPS_RETIRED.RETIRE_SLOTS",
brief_description:
"Retirement slots used (Precise Event)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_TRANSACTIONS.IFETCH",
IntelPerformanceCounterDescription{event_code:
Tuple::One(240),
umask:
Tuple::One(4),
event_name:
"L2_TRANSACTIONS.IFETCH",
brief_description:
"L2 instruction fetch transactions",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("FP_COMP_OPS_EXE.SSE_FP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(16),
umask:
Tuple::One(4),
event_name:
"FP_COMP_OPS_EXE.SSE_FP",
brief_description:
"SSE and SSE2 FP Uops",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L1D_CACHE_LOCK_FB_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(83),
umask:
Tuple::One(1),
event_name:
"L1D_CACHE_LOCK_FB_HIT",
brief_description:
"L1D load lock accepted in fill buffer",
public_description:
None,
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_DATA_RD.LOCAL_CACHE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_DATA_RD.LOCAL_CACHE_DRAM",
brief_description:
"Offcore demand data reads satisfied by the LLC or local DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
18177,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM",
brief_description:
"Offcore requests satisfied by the LLC and HITM in a sibling core",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
1279,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION",
IntelPerformanceCounterDescription{event_code:
Tuple::One(16),
umask:
Tuple::One(128),
event_name:
"FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION",
brief_description:
"SSE* FP double precision Uops",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE",
brief_description:
"Offcore demand data reads satisfied by the LLC and not found in a sibling core",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
257,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT",
brief_description:
"Offcore demand code reads satisfied by the LLC and HIT in a sibling core",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
516,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("FP_MMX_TRANS.ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(204),
umask:
Tuple::One(3),
event_name:
"FP_MMX_TRANS.ANY",
brief_description:
"All Floating Point to and from MMX transitions",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION",
IntelPerformanceCounterDescription{event_code:
Tuple::One(16),
umask:
Tuple::One(64),
event_name:
"FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION",
brief_description:
"SSE* FP single precision Uops",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.COREWB.ANY_LOCATION",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.COREWB.ANY_LOCATION",
brief_description:
"All offcore writebacks",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
65288,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("INST_RETIRED.MMX",
IntelPerformanceCounterDescription{event_code:
Tuple::One(192),
umask:
Tuple::One(4),
event_name:
"INST_RETIRED.MMX",
brief_description:
"Retired MMX instructions (Precise Event)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("LSD_OVERFLOW",
IntelPerformanceCounterDescription{event_code:
Tuple::One(32),
umask:
Tuple::One(1),
event_name:
"LSD_OVERFLOW",
brief_description:
"Loops that can\'t stream from the instruction queue",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_LINES_OUT.DEMAND_CLEAN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(242),
umask:
Tuple::One(1),
event_name:
"L2_LINES_OUT.DEMAND_CLEAN",
brief_description:
"L2 lines evicted by a demand request",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L1D_WB_L2.MESI",
IntelPerformanceCounterDescription{event_code:
Tuple::One(40),
umask:
Tuple::One(15),
event_name:
"L1D_WB_L2.MESI",
brief_description:
"All L1 writebacks to L2",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_MISP_EXEC.NON_CALLS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(137),
umask:
Tuple::One(7),
event_name:
"BR_MISP_EXEC.NON_CALLS",
brief_description:
"Mispredicted non call branches executed",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
20000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_RFO.ANY_LOCATION",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_RFO.ANY_LOCATION",
brief_description:
"All offcore RFO requests",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
65314,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024",
IntelPerformanceCounterDescription{event_code:
Tuple::One(11),
umask:
Tuple::One(16),
event_name:
"MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024",
brief_description:
"Memory instructions retired above 1024 clocks (Precise Event)",
public_description:
None,
counter:
Counter::Programmable(8),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100,
msr_index:
MSRIndex::One(246),
msr_value:
1024,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOnly,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM",
brief_description:
"Offcore prefetch data reads satisfied by the LLC and HITM in a sibling core",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
1040,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_IFETCH.ANY_LLC_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_IFETCH.ANY_LLC_MISS",
brief_description:
"Offcore code reads that missed the LLC",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
63556,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4",
IntelPerformanceCounterDescription{event_code:
Tuple::One(11),
umask:
Tuple::One(16),
event_name:
"MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4",
brief_description:
"Memory instructions retired above 4 clocks (Precise Event)",
public_description:
None,
counter:
Counter::Programmable(8),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
50000,
msr_index:
MSRIndex::One(246),
msr_value:
4,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOnly,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT",
brief_description:
"Offcore demand data reads satisfied by the LLC and HIT in a sibling core",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
513,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_DECODED.ESP_FOLDING",
IntelPerformanceCounterDescription{event_code:
Tuple::One(209),
umask:
Tuple::One(4),
event_name:
"UOPS_DECODED.ESP_FOLDING",
brief_description:
"Stack pointer instructions decoded",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256",
IntelPerformanceCounterDescription{event_code:
Tuple::One(11),
umask:
Tuple::One(16),
event_name:
"MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256",
brief_description:
"Memory instructions retired above 256 clocks (Precise Event)",
public_description:
None,
counter:
Counter::Programmable(8),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
500,
msr_index:
MSRIndex::One(246),
msr_value:
256,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOnly,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("FP_COMP_OPS_EXE.MMX",
IntelPerformanceCounterDescription{event_code:
Tuple::One(16),
umask:
Tuple::One(2),
event_name:
"FP_COMP_OPS_EXE.MMX",
brief_description:
"MMX Uops",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768",
IntelPerformanceCounterDescription{event_code:
Tuple::One(11),
umask:
Tuple::One(16),
event_name:
"MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768",
brief_description:
"Memory instructions retired above 32768 clocks (Precise Event)",
public_description:
None,
counter:
Counter::Programmable(8),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
3,
msr_index:
MSRIndex::One(246),
msr_value:
32768,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOnly,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_DATA_RD.LOCAL_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_DATA_RD.LOCAL_DRAM",
brief_description:
"Offcore prefetch data reads satisfied by the local DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
16400,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("LSD.INACTIVE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(168),
umask:
Tuple::One(1),
event_name:
"LSD.INACTIVE",
brief_description:
"Cycles no uops were delivered by the LSD",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
true,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DATA_IN.LOCAL_CACHE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DATA_IN.LOCAL_CACHE",
brief_description:
"Offcore request = all data, response = local cache",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
1843,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_RFO.ANY_CACHE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_RFO.ANY_CACHE_DRAM",
brief_description:
"Offcore RFO requests satisfied by any cache or DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
32546,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("SSEX_UOPS_RETIRED.SCALAR_DOUBLE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(199),
umask:
Tuple::One(8),
event_name:
"SSEX_UOPS_RETIRED.SCALAR_DOUBLE",
brief_description:
"SIMD Scalar-Double Uops retired (Precise Event)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("SNOOP_RESPONSE.HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(184),
umask:
Tuple::One(1),
event_name:
"SNOOP_RESPONSE.HIT",
brief_description:
"Thread responded HIT to snoop",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L1D_ALL_REF.CACHEABLE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(67),
umask:
Tuple::One(2),
event_name:
"L1D_ALL_REF.CACHEABLE",
brief_description:
"L1 data cacheable reads and writes",
public_description:
None,
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("INST_RETIRED.ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(0),
umask:
Tuple::One(0),
event_name:
"INST_RETIRED.ANY",
brief_description:
"Instructions retired (fixed counter)",
public_description:
None,
counter:
Counter::Fixed(2),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_DATA_RQSTS.DEMAND.M_STATE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(38),
umask:
Tuple::One(8),
event_name:
"L2_DATA_RQSTS.DEMAND.M_STATE",
brief_description:
"L2 data demand loads in M state",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DATA_IN.LOCAL_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DATA_IN.LOCAL_DRAM",
brief_description:
"Offcore data reads, RFO\'s and prefetches statisfied by the local DRAM.",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
16435,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_DATA.REMOTE_CACHE_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_DATA.REMOTE_CACHE_HIT",
brief_description:
"Offcore prefetch data requests that HIT in a remote cache",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
4144,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("FP_COMP_OPS_EXE.X87",
IntelPerformanceCounterDescription{event_code:
Tuple::One(16),
umask:
Tuple::One(1),
event_name:
"FP_COMP_OPS_EXE.X87",
brief_description:
"Computational floating-point operations executed",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("RESOURCE_STALLS.ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(162),
umask:
Tuple::One(1),
event_name:
"RESOURCE_STALLS.ANY",
brief_description:
"Resource related stall cycles",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_RFO.LOCAL_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_RFO.LOCAL_DRAM",
brief_description:
"Offcore prefetch RFO requests satisfied by the local DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
16416,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PREFETCH.ANY_CACHE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PREFETCH.ANY_CACHE_DRAM",
brief_description:
"Offcore prefetch requests satisfied by any cache or DRAM.",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
32624,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_MISP_EXEC.NEAR_CALLS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(137),
umask:
Tuple::One(48),
event_name:
"BR_MISP_EXEC.NEAR_CALLS",
brief_description:
"Mispredicted call branches executed",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_RFO.REMOTE_CACHE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_RFO.REMOTE_CACHE_DRAM",
brief_description:
"Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
14368,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_MISP_EXEC.RETURN_NEAR",
IntelPerformanceCounterDescription{event_code:
Tuple::One(137),
umask:
Tuple::One(8),
event_name:
"BR_MISP_EXEC.RETURN_NEAR",
brief_description:
"Mispredicted return branches executed",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_RFO.ANY_LOCATION",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_RFO.ANY_LOCATION",
brief_description:
"All offcore demand RFO requests",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
65282,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("L1D.M_SNOOP_EVICT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(81),
umask:
Tuple::One(8),
event_name:
"L1D.M_SNOOP_EVICT",
brief_description:
"L1D snoop eviction of cache lines in M state",
public_description:
None,
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DATA_IFETCH.IO_CSR_MMIO",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DATA_IFETCH.IO_CSR_MMIO",
brief_description:
"Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
32887,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_RQSTS.RFO_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(36),
umask:
Tuple::One(8),
event_name:
"L2_RQSTS.RFO_MISS",
brief_description:
"L2 RFO misses",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_RQSTS.PREFETCH_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(36),
umask:
Tuple::One(64),
event_name:
"L2_RQSTS.PREFETCH_HIT",
brief_description:
"L2 prefetch hits",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_MISP_EXEC.DIRECT_NEAR_CALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(137),
umask:
Tuple::One(16),
event_name:
"BR_MISP_EXEC.DIRECT_NEAR_CALL",
brief_description:
"Mispredicted non call branches executed",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L1D_WB_L2.M_STATE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(40),
umask:
Tuple::One(8),
event_name:
"L1D_WB_L2.M_STATE",
brief_description:
"L1 writebacks to L2 in M state",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_INST_EXEC.INDIRECT_NEAR_CALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(136),
umask:
Tuple::One(32),
event_name:
"BR_INST_EXEC.INDIRECT_NEAR_CALL",
brief_description:
"Indirect call branches executed",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
20000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.OTHER.REMOTE_CACHE_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.OTHER.REMOTE_CACHE_HITM",
brief_description:
"Offcore other requests that HITM in a remote cache",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
2176,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_WRITE.LOCK.HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(39),
umask:
Tuple::One(224),
event_name:
"L2_WRITE.LOCK.HIT",
brief_description:
"All demand L2 lock RFOs that hit the cache",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L1D_CACHE_LD.E_STATE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(64),
umask:
Tuple::One(4),
event_name:
"L1D_CACHE_LD.E_STATE",
brief_description:
"L1 data cache read in E state",
public_description:
None,
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.OTHER.LLC_HIT_OTHER_CORE_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.OTHER.LLC_HIT_OTHER_CORE_HIT",
brief_description:
"Offcore other requests satisfied by the LLC and HIT in a sibling core",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
640,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.COREWB.LOCAL_CACHE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.COREWB.LOCAL_CACHE",
brief_description:
"Offcore writebacks to the LLC",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
1800,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_DATA_RD.LOCAL_CACHE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_DATA_RD.LOCAL_CACHE_DRAM",
brief_description:
"Offcore prefetch data reads satisfied by the LLC or local DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
18192,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_DATA.IO_CSR_MMIO",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_DATA.IO_CSR_MMIO",
brief_description:
"Offcore data reads satisfied by the IO, CSR, MMIO unit",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
32785,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_DATA_RD.REMOTE_CACHE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_DATA_RD.REMOTE_CACHE",
brief_description:
"Offcore demand data reads satisfied by a remote cache",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
6145,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_RFO.REMOTE_CACHE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_RFO.REMOTE_CACHE",
brief_description:
"Offcore demand RFO requests satisfied by a remote cache",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
6146,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_DATA.IO_CSR_MMIO",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_DATA.IO_CSR_MMIO",
brief_description:
"Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
32816,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("RESOURCE_STALLS.FPCW",
IntelPerformanceCounterDescription{event_code:
Tuple::One(162),
umask:
Tuple::One(32),
event_name:
"RESOURCE_STALLS.FPCW",
brief_description:
"FPU control word write stall cycles",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_IFETCH.REMOTE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_IFETCH.REMOTE_DRAM",
brief_description:
"Offcore prefetch code reads satisfied by a remote DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
8256,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_EXECUTED.CORE_STALL_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(177),
umask:
Tuple::One(63),
event_name:
"UOPS_EXECUTED.CORE_STALL_CYCLES",
brief_description:
"Cycles no Uops issued on any port (core count)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
true,
any_thread:
true,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PREFETCH.IO_CSR_MMIO",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PREFETCH.IO_CSR_MMIO",
brief_description:
"Offcore prefetch requests satisfied by the IO, CSR, MMIO unit",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
32880,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_RFO.REMOTE_CACHE_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_RFO.REMOTE_CACHE_HIT",
brief_description:
"Offcore demand RFO requests that HIT in a remote cache",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
4098,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_RFO.LOCAL_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_RFO.LOCAL_DRAM",
brief_description:
"Offcore demand RFO requests satisfied by the local DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
16386,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_IFETCH.LOCAL_CACHE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_IFETCH.LOCAL_CACHE",
brief_description:
"Offcore demand code reads satisfied by the LLC",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
1796,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.COREWB.REMOTE_CACHE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.COREWB.REMOTE_CACHE_DRAM",
brief_description:
"Offcore writebacks to a remote cache or remote DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
14344,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("STORE_BLOCKS.L1D_BLOCK",
IntelPerformanceCounterDescription{event_code:
Tuple::One(6),
umask:
Tuple::One(8),
event_name:
"STORE_BLOCKS.L1D_BLOCK",
brief_description:
"Cacheable loads delayed with L1D block code",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("SIMD_INT_128.PACKED_SHIFT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(18),
umask:
Tuple::One(2),
event_name:
"SIMD_INT_128.PACKED_SHIFT",
brief_description:
"128 bit SIMD integer shift operations",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_MISP_EXEC.INDIRECT_NON_CALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(137),
umask:
Tuple::One(4),
event_name:
"BR_MISP_EXEC.INDIRECT_NON_CALL",
brief_description:
"Mispredicted indirect non call branches executed",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("SIMD_INT_64.PACKED_SHIFT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(253),
umask:
Tuple::One(2),
event_name:
"SIMD_INT_64.PACKED_SHIFT",
brief_description:
"SIMD integer 64 bit shift operations",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L1D_CACHE_ST.M_STATE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(65),
umask:
Tuple::One(8),
event_name:
"L1D_CACHE_ST.M_STATE",
brief_description:
"L1 data cache stores in M state",
public_description:
None,
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L1I.READS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(128),
umask:
Tuple::One(3),
event_name:
"L1I.READS",
brief_description:
"L1I Instruction fetches",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_RFO.ANY_LLC_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_RFO.ANY_LLC_MISS",
brief_description:
"Offcore demand RFO requests that missed the LLC",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
63490,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("INST_QUEUE_WRITES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(23),
umask:
Tuple::One(1),
event_name:
"INST_QUEUE_WRITES",
brief_description:
"Instructions written to instruction queue.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.OTHER.REMOTE_CACHE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.OTHER.REMOTE_CACHE",
brief_description:
"Offcore other requests satisfied by a remote cache",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
6272,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_LOAD_RETIRED.HIT_LFB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(203),
umask:
Tuple::One(64),
event_name:
"MEM_LOAD_RETIRED.HIT_LFB",
brief_description:
"Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L1D_CACHE_PREFETCH_LOCK_FB_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(82),
umask:
Tuple::One(1),
event_name:
"L1D_CACHE_PREFETCH_LOCK_FB_HIT",
brief_description:
"L1D prefetch load lock accepted in fill buffer",
public_description:
None,
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE",
brief_description:
"Offcore code or data read requests satisfied by the LLC and not found in a sibling core",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
375,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("RESOURCE_STALLS.OTHER",
IntelPerformanceCounterDescription{event_code:
Tuple::One(162),
umask:
Tuple::One(128),
event_name:
"RESOURCE_STALLS.OTHER",
brief_description:
"Other Resource related stall cycles",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_DATA_RD.LOCAL_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_DATA_RD.LOCAL_DRAM",
brief_description:
"Offcore demand data reads satisfied by the local DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
16385,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DATA_IFETCH.ANY_CACHE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DATA_IFETCH.ANY_CACHE_DRAM",
brief_description:
"Offcore code or data read requests satisfied by any cache or DRAM.",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
32631,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_EXECUTED.PORT234_CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(177),
umask:
Tuple::One(128),
event_name:
"UOPS_EXECUTED.PORT234_CORE",
brief_description:
"Uops issued on ports 2, 3 or 4",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
true,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_MISP_RETIRED.NEAR_CALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(197),
umask:
Tuple::One(2),
event_name:
"BR_MISP_RETIRED.NEAR_CALL",
brief_description:
"Mispredicted near retired calls (Precise Event)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_DATA.ANY_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_DATA.ANY_DRAM",
brief_description:
"Offcore data reads satisfied by any DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
24593,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("L1D.REPL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(81),
umask:
Tuple::One(1),
event_name:
"L1D.REPL",
brief_description:
"L1 data cache lines allocated",
public_description:
None,
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_DATA_RD.REMOTE_CACHE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_DATA_RD.REMOTE_CACHE_DRAM",
brief_description:
"Offcore prefetch data reads satisfied by a remote cache or remote DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
14352,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("MACRO_INSTS.DECODED",
IntelPerformanceCounterDescription{event_code:
Tuple::One(208),
umask:
Tuple::One(1),
event_name:
"MACRO_INSTS.DECODED",
brief_description:
"Instructions decoded",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_INST_DECODED",
IntelPerformanceCounterDescription{event_code:
Tuple::One(224),
umask:
Tuple::One(1),
event_name:
"BR_INST_DECODED",
brief_description:
"Branch instructions decoded",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("RAT_STALLS.REGISTERS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(210),
umask:
Tuple::One(2),
event_name:
"RAT_STALLS.REGISTERS",
brief_description:
"Partial register stall cycles",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("ARITH.MUL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(20),
umask:
Tuple::One(2),
event_name:
"ARITH.MUL",
brief_description:
"Multiply operations executed",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DATA_IN.REMOTE_CACHE_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DATA_IN.REMOTE_CACHE_HIT",
brief_description:
"Offcore data reads, RFO\'s and prefetches that HIT in a remote cache",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
4147,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_DATA_RD.ANY_LLC_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_DATA_RD.ANY_LLC_MISS",
brief_description:
"Offcore demand data reads that missed the LLC",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
63489,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_DATA.REMOTE_CACHE_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_DATA.REMOTE_CACHE_HITM",
brief_description:
"Offcore prefetch data requests that HITM in a remote cache",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
2096,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_DATA.REMOTE_CACHE_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_DATA.REMOTE_CACHE_HIT",
brief_description:
"Offcore demand data requests that HIT in a remote cache",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
4099,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.COREWB.REMOTE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.COREWB.REMOTE_DRAM",
brief_description:
"Offcore writebacks to a remote DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
8200,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("ILD_STALL.REGEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(135),
umask:
Tuple::One(8),
event_name:
"ILD_STALL.REGEN",
brief_description:
"Regen stall cycles",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.COREWB.LOCAL_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.COREWB.LOCAL_DRAM",
brief_description:
"Offcore writebacks to the local DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
16392,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PREFETCH.ANY_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PREFETCH.ANY_DRAM",
brief_description:
"Offcore prefetch requests satisfied by any DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
24688,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DATA_IFETCH.LOCAL_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DATA_IFETCH.LOCAL_DRAM",
brief_description:
"Offcore code or data read requests satisfied by the local DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
16503,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_DATA_RQSTS.PREFETCH.E_STATE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(38),
umask:
Tuple::One(64),
event_name:
"L2_DATA_RQSTS.PREFETCH.E_STATE",
brief_description:
"L2 data prefetches in E state",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("RAT_STALLS.FLAGS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(210),
umask:
Tuple::One(1),
event_name:
"RAT_STALLS.FLAGS",
brief_description:
"Flag stall cycles",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.OTHER.ANY_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.OTHER.ANY_DRAM",
brief_description:
"Offcore other requests satisfied by any DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
24704,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_DATA_RD.IO_CSR_MMIO",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_DATA_RD.IO_CSR_MMIO",
brief_description:
"Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
32784,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_RFO.LOCAL_CACHE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_RFO.LOCAL_CACHE_DRAM",
brief_description:
"Offcore demand RFO requests satisfied by the LLC or local DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
18178,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PREFETCH.REMOTE_CACHE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PREFETCH.REMOTE_CACHE",
brief_description:
"Offcore prefetch requests satisfied by a remote cache",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
6256,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_IFETCH.REMOTE_CACHE_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_IFETCH.REMOTE_CACHE_HIT",
brief_description:
"Offcore code reads that HIT in a remote cache",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
4164,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.OTHER.LOCAL_CACHE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.OTHER.LOCAL_CACHE",
brief_description:
"Offcore other requests satisfied by the LLC",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
1920,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_WRITE.LOCK.E_STATE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(39),
umask:
Tuple::One(64),
event_name:
"L2_WRITE.LOCK.E_STATE",
brief_description:
"L2 demand lock RFOs in E state",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("RESOURCE_STALLS.RS_FULL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(162),
umask:
Tuple::One(4),
event_name:
"RESOURCE_STALLS.RS_FULL",
brief_description:
"Reservation Station full stall cycles",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DATA_IN.REMOTE_CACHE_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DATA_IN.REMOTE_CACHE_HITM",
brief_description:
"Offcore data reads, RFO\'s and prefetches that HITM in a remote cache",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
2099,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_EXECUTED.PORT5",
IntelPerformanceCounterDescription{event_code:
Tuple::One(177),
umask:
Tuple::One(32),
event_name:
"UOPS_EXECUTED.PORT5",
brief_description:
"Uops executed on port 5",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_WRITE.LOCK.I_STATE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(39),
umask:
Tuple::One(16),
event_name:
"L2_WRITE.LOCK.I_STATE",
brief_description:
"L2 demand lock RFOs in I state (misses)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.OTHER.LLC_HIT_OTHER_CORE_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.OTHER.LLC_HIT_OTHER_CORE_HITM",
brief_description:
"Offcore other requests satisfied by the LLC and HITM in a sibling core",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
1152,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_DATA.REMOTE_CACHE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_DATA.REMOTE_CACHE",
brief_description:
"Offcore prefetch data requests satisfied by a remote cache",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
6192,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(11),
umask:
Tuple::One(16),
event_name:
"MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0",
brief_description:
"Memory instructions retired above 0 clocks (Precise Event)",
public_description:
None,
counter:
Counter::Programmable(8),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::One(246),
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOnly,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT",
brief_description:
"Offcore demand data requests satisfied by the LLC and HIT in a sibling core",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
515,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_RQSTS.REFERENCES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(36),
umask:
Tuple::One(255),
event_name:
"L2_RQSTS.REFERENCES",
brief_description:
"All L2 requests",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_WRITE.RFO.M_STATE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(39),
umask:
Tuple::One(8),
event_name:
"L2_WRITE.RFO.M_STATE",
brief_description:
"L2 demand store RFOs in M state",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_RFO.ANY_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_RFO.ANY_DRAM",
brief_description:
"Offcore demand RFO requests satisfied by any DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
24578,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_IFETCH.LLC_HIT_NO_OTHER_CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_IFETCH.LLC_HIT_NO_OTHER_CORE",
brief_description:
"Offcore prefetch code reads satisfied by the LLC and not found in a sibling core",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
320,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("FP_MMX_TRANS.TO_MMX",
IntelPerformanceCounterDescription{event_code:
Tuple::One(204),
umask:
Tuple::One(2),
event_name:
"FP_MMX_TRANS.TO_MMX",
brief_description:
"Transitions from Floating Point to MMX instructions",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_UNCORE_RETIRED.OTHER_CORE_L2_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(15),
umask:
Tuple::One(2),
event_name:
"MEM_UNCORE_RETIRED.OTHER_CORE_L2_HITM",
brief_description:
"Load instructions retired that HIT modified data in sibling core (Precise Event)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
40000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MACHINE_CLEARS.SMC",
IntelPerformanceCounterDescription{event_code:
Tuple::One(195),
umask:
Tuple::One(4),
event_name:
"MACHINE_CLEARS.SMC",
brief_description:
"Self-Modifying Code detected",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
20000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.OTHER.REMOTE_CACHE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.OTHER.REMOTE_CACHE_DRAM",
brief_description:
"Offcore other requests satisfied by a remote cache or remote DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
14464,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_ISSUED.STALL_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(14),
umask:
Tuple::One(1),
event_name:
"UOPS_ISSUED.STALL_CYCLES",
brief_description:
"Cycles no Uops were issued",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
true,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DATA_IN.IO_CSR_MMIO",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DATA_IN.IO_CSR_MMIO",
brief_description:
"Offcore data reads, RFO\'s and prefetches satisfied by the IO, CSR, MMIO unit",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
32819,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_INST_EXEC.TAKEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(136),
umask:
Tuple::One(64),
event_name:
"BR_INST_EXEC.TAKEN",
brief_description:
"Taken branches executed",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DATA_IN.LLC_HIT_OTHER_CORE_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DATA_IN.LLC_HIT_OTHER_CORE_HITM",
brief_description:
"Offcore data reads, RFO\'s and prefetches satisfied by the LLC and HITM in a sibling core",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
1075,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_LINES_OUT.PREFETCH_DIRTY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(242),
umask:
Tuple::One(8),
event_name:
"L2_LINES_OUT.PREFETCH_DIRTY",
brief_description:
"L2 modified lines evicted by a prefetch request",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L1I.MISSES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(128),
umask:
Tuple::One(2),
event_name:
"L1I.MISSES",
brief_description:
"L1I instruction fetch misses",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8",
IntelPerformanceCounterDescription{event_code:
Tuple::One(11),
umask:
Tuple::One(16),
event_name:
"MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8",
brief_description:
"Memory instructions retired above 8 clocks (Precise Event)",
public_description:
None,
counter:
Counter::Programmable(8),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
20000,
msr_index:
MSRIndex::One(246),
msr_value:
8,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOnly,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_DATA.IO_CSR_MMIO",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_DATA.IO_CSR_MMIO",
brief_description:
"Offcore demand data requests satisfied by the IO, CSR, MMIO unit.",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
32771,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_LOAD_RETIRED.LLC_UNSHARED_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(203),
umask:
Tuple::One(4),
event_name:
"MEM_LOAD_RETIRED.LLC_UNSHARED_HIT",
brief_description:
"Retired loads that hit valid versions in the LLC cache (Precise Event)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
40000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_DATA.ANY_CACHE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_DATA.ANY_CACHE_DRAM",
brief_description:
"Offcore demand data requests satisfied by any cache or DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
32515,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("LONGEST_LAT_CACHE.REFERENCE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(46),
umask:
Tuple::One(79),
event_name:
"LONGEST_LAT_CACHE.REFERENCE",
brief_description:
"Longest latency cache reference",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DATA_IN.ANY_LOCATION",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DATA_IN.ANY_LOCATION",
brief_description:
"Offcore request = all data, response = any location",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
65331,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM",
brief_description:
"Offcore code or data read requests satisfied by the LLC and HITM in a sibling core",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
1143,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT",
brief_description:
"Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
528,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_WRITE.LOCK.M_STATE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(39),
umask:
Tuple::One(128),
event_name:
"L2_WRITE.LOCK.M_STATE",
brief_description:
"L2 demand lock RFOs in M state",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_RFO.LLC_HIT_OTHER_CORE_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_RFO.LLC_HIT_OTHER_CORE_HITM",
brief_description:
"Offcore prefetch RFO requests satisfied by the LLC and HITM in a sibling core",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
1056,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_IFETCH.ANY_CACHE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_IFETCH.ANY_CACHE_DRAM",
brief_description:
"Offcore prefetch code reads satisfied by any cache or DRAM.",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
32576,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("DTLB_LOAD_MISSES.STLB_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(8),
umask:
Tuple::One(16),
event_name:
"DTLB_LOAD_MISSES.STLB_HIT",
brief_description:
"DTLB second level hit",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_RFO.REMOTE_CACHE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_RFO.REMOTE_CACHE",
brief_description:
"Offcore prefetch RFO requests satisfied by a remote cache",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
6176,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_IFETCH.REMOTE_CACHE_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_IFETCH.REMOTE_CACHE_HITM",
brief_description:
"Offcore demand code reads that HITM in a remote cache",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
2052,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32",
IntelPerformanceCounterDescription{event_code:
Tuple::One(11),
umask:
Tuple::One(16),
event_name:
"MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32",
brief_description:
"Memory instructions retired above 32 clocks (Precise Event)",
public_description:
None,
counter:
Counter::Programmable(8),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
5000,
msr_index:
MSRIndex::One(246),
msr_value:
32,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOnly,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L1D_CACHE_ST.S_STATE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(65),
umask:
Tuple::One(2),
event_name:
"L1D_CACHE_ST.S_STATE",
brief_description:
"L1 data cache stores in S state",
public_description:
None,
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_IFETCH.REMOTE_CACHE_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_IFETCH.REMOTE_CACHE_HIT",
brief_description:
"Offcore demand code reads that HIT in a remote cache",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
4100,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("INST_RETIRED.X87",
IntelPerformanceCounterDescription{event_code:
Tuple::One(192),
umask:
Tuple::One(2),
event_name:
"INST_RETIRED.X87",
brief_description:
"Retired floating-point operations (Precise Event)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_IFETCH.LOCAL_CACHE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_IFETCH.LOCAL_CACHE_DRAM",
brief_description:
"Offcore prefetch code reads satisfied by the LLC or local DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
18240,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("L1D_CACHE_ST.E_STATE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(65),
umask:
Tuple::One(4),
event_name:
"L1D_CACHE_ST.E_STATE",
brief_description:
"L1 data cache stores in E state",
public_description:
None,
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_DATA.REMOTE_CACHE_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_DATA.REMOTE_CACHE_HIT",
brief_description:
"Offcore data reads that HIT in a remote cache",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
4113,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_DATA_RD.ANY_LOCATION",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_DATA_RD.ANY_LOCATION",
brief_description:
"All offcore prefetch data reads",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
65296,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_DATA.ANY_LOCATION",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_DATA.ANY_LOCATION",
brief_description:
"All offcore prefetch data requests",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
65328,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_RQSTS.IFETCHES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(36),
umask:
Tuple::One(48),
event_name:
"L2_RQSTS.IFETCHES",
brief_description:
"L2 instruction fetches",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_DATA.LOCAL_CACHE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_DATA.LOCAL_CACHE",
brief_description:
"Offcore demand data requests satisfied by the LLC",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
1795,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_EXECUTED.PORT015_STALL_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(177),
umask:
Tuple::One(64),
event_name:
"UOPS_EXECUTED.PORT015_STALL_CYCLES",
brief_description:
"Cycles no Uops issued on ports 0, 1 or 5",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
true,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384",
IntelPerformanceCounterDescription{event_code:
Tuple::One(11),
umask:
Tuple::One(16),
event_name:
"MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384",
brief_description:
"Memory instructions retired above 16384 clocks (Precise Event)",
public_description:
None,
counter:
Counter::Programmable(8),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
5,
msr_index:
MSRIndex::One(246),
msr_value:
16384,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOnly,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_RFO.ANY_LLC_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_RFO.ANY_LLC_MISS",
brief_description:
"Offcore prefetch RFO requests that missed the LLC",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
63520,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_DATA.REMOTE_CACHE_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_DATA.REMOTE_CACHE_HITM",
brief_description:
"Offcore demand data requests that HITM in a remote cache",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
2051,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_TRANSACTIONS.WB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(240),
umask:
Tuple::One(64),
event_name:
"L2_TRANSACTIONS.WB",
brief_description:
"L2 writeback to LLC transactions",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("FP_COMP_OPS_EXE.SSE2_INTEGER",
IntelPerformanceCounterDescription{event_code:
Tuple::One(16),
umask:
Tuple::One(8),
event_name:
"FP_COMP_OPS_EXE.SSE2_INTEGER",
brief_description:
"SSE2 integer Uops",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("ARITH.CYCLES_DIV_BUSY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(20),
umask:
Tuple::One(1),
event_name:
"ARITH.CYCLES_DIV_BUSY",
brief_description:
"Cycles the divider is busy",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("SIMD_INT_128.PACKED_LOGICAL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(18),
umask:
Tuple::One(16),
event_name:
"SIMD_INT_128.PACKED_LOGICAL",
brief_description:
"128 bit SIMD integer logical operations",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096",
IntelPerformanceCounterDescription{event_code:
Tuple::One(11),
umask:
Tuple::One(16),
event_name:
"MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096",
brief_description:
"Memory instructions retired above 4096 clocks (Precise Event)",
public_description:
None,
counter:
Counter::Programmable(8),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
20,
msr_index:
MSRIndex::One(246),
msr_value:
4096,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOnly,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT",
brief_description:
"Offcore requests satisfied by the LLC and HIT in a sibling core",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
767,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("INST_RETIRED.ANY_P",
IntelPerformanceCounterDescription{event_code:
Tuple::One(192),
umask:
Tuple::One(1),
event_name:
"INST_RETIRED.ANY_P",
brief_description:
"Instructions retired (Programmable counter and Precise Event)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DATA_IN.LLC_HIT_OTHER_CORE_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DATA_IN.LLC_HIT_OTHER_CORE_HIT",
brief_description:
"Offcore data reads, RFO\'s and prefetches satisfied by the LLC and HIT in a sibling core",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
563,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("RAT_STALLS.ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(210),
umask:
Tuple::One(15),
event_name:
"RAT_STALLS.ANY",
brief_description:
"All RAT stall cycles",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L1D_ALL_REF.ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(67),
umask:
Tuple::One(1),
event_name:
"L1D_ALL_REF.ANY",
brief_description:
"All references to the L1 data cache",
public_description:
None,
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048",
IntelPerformanceCounterDescription{event_code:
Tuple::One(11),
umask:
Tuple::One(16),
event_name:
"MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048",
brief_description:
"Memory instructions retired above 2048 clocks (Precise Event)",
public_description:
None,
counter:
Counter::Programmable(8),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
50,
msr_index:
MSRIndex::One(246),
msr_value:
2048,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOnly,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_RFO.REMOTE_CACHE_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_RFO.REMOTE_CACHE_HIT",
brief_description:
"Offcore RFO requests that HIT in a remote cache",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
4130,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.ANY_RFO.ANY_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.ANY_RFO.ANY_DRAM",
brief_description:
"Offcore RFO requests satisfied by any DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
24610,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_IFETCH.ANY_LOCATION",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_IFETCH.ANY_LOCATION",
brief_description:
"All offcore demand code reads",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
65284,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_TRANSACTIONS.LOAD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(240),
umask:
Tuple::One(1),
event_name:
"L2_TRANSACTIONS.LOAD",
brief_description:
"L2 Load transactions",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("PARTIAL_ADDRESS_ALIAS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(7),
umask:
Tuple::One(1),
event_name:
"PARTIAL_ADDRESS_ALIAS",
brief_description:
"False dependencies due to partial address aliasing",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
200000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_DATA.ANY_LOCATION",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_DATA.ANY_LOCATION",
brief_description:
"All offcore demand data requests",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
65283,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_IFETCH.LOCAL_CACHE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_IFETCH.LOCAL_CACHE_DRAM",
brief_description:
"Offcore demand code reads satisfied by the LLC or local DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
18180,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_RFO.LOCAL_CACHE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_RFO.LOCAL_CACHE",
brief_description:
"Offcore prefetch RFO requests satisfied by the LLC",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
1824,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("LSD.ACTIVE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(168),
umask:
Tuple::One(1),
event_name:
"LSD.ACTIVE",
brief_description:
"Cycles when uops were delivered by the LSD",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.PF_RFO.REMOTE_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.PF_RFO.REMOTE_DRAM",
brief_description:
"Offcore prefetch RFO requests satisfied by a remote DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
8224,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DATA_IN.REMOTE_CACHE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DATA_IN.REMOTE_CACHE",
brief_description:
"Offcore request = all data, response = remote cache",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
6195,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("INST_QUEUE_WRITE_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(30),
umask:
Tuple::One(1),
event_name:
"INST_QUEUE_WRITE_CYCLES",
brief_description:
"Cycles instructions are written to the instruction queue",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
2000000,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE_0.DEMAND_DATA_RD.ANY_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE_0.DEMAND_DATA_RD.ANY_DRAM",
brief_description:
"Offcore demand data reads satisfied by any DRAM",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
100000,
msr_index:
MSRIndex::One(166),
msr_value:
24577,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,})]),}