pub const JAKETOWN_UNCORE: Map<&'static str, IntelPerformanceCounterDescription> = ::phf::Map{key: 1897749892740154578,
disps:
::phf::Slice::Static(&[(0, 66), (0, 5), (0, 0), (0, 45),
(1, 207), (0, 110), (0, 0), (0, 111),
(1, 166), (0, 121), (0, 33), (0, 135),
(0, 1), (0, 11), (0, 4), (0, 185),
(0, 44), (0, 19), (0, 26), (0, 25),
(0, 19), (0, 28), (6, 63), (1, 310),
(0, 1), (2, 34), (0, 0), (0, 88),
(6, 397), (0, 9), (0, 0), (0, 9),
(0, 250), (0, 22), (0, 3), (0, 43),
(0, 475), (0, 173), (0, 89), (0, 161),
(2, 40), (1, 158), (0, 33), (0, 115),
(0, 0), (0, 2), (0, 1), (0, 14),
(0, 82), (0, 9), (0, 9), (0, 33),
(0, 1), (0, 0), (0, 57), (0, 108),
(0, 41), (1, 0), (0, 89), (0, 416),
(0, 124), (1, 396), (0, 12), (0, 137),
(1, 78), (3, 333), (0, 48), (0, 221),
(0, 1), (0, 0), (0, 8), (0, 48),
(35, 262), (1, 500), (0, 282), (0, 214),
(0, 115), (0, 25), (0, 497), (0, 110),
(0, 36), (2, 137), (1, 53), (6, 376),
(0, 1), (10, 356), (4, 360), (13, 302),
(3, 4), (0, 122), (0, 5), (4, 171),
(0, 328), (1, 268), (0, 5), (0, 29),
(4, 110), (0, 0), (0, 287), (14, 26),
(32, 367), (1, 5), (1, 0), (0, 3),
(0, 185), (0, 344), (0, 28),
(25, 215)]),
entries:
::phf::Slice::Static(&[("UNC_M_RPQ_CYCLES_FULL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(18),
umask:
Tuple::One(0),
event_name:
"UNC_M_RPQ_CYCLES_FULL",
brief_description:
"Read Pending Queue Full Cycles",
public_description:
Some("Counts the number of cycles when the Read Pending Queue is full. When the RPQ is full, the HA will not be able to issue any additional read requests into the iMC. This count should be similar count in the HA which tracks the number of cycles that the HA has no RPQ credits, just somewhat smaller to account for the credit return overhead. We generally do not expect to see RPQ become full except for potentially during Write Major Mode or while running with slow DRAM. This event only tracks non-ISOC queue entries."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(30),
umask:
Tuple::One(2),
event_name:
"UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCB",
brief_description:
"VN0 Credit Consumed; NCB",
public_description:
Some("Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_C_TOR_OCCUPANCY.OPCODE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(54),
umask:
Tuple::One(1),
event_name:
"UNC_C_TOR_OCCUPANCY.OPCODE",
brief_description:
"TOR Occupancy; Opcode Match",
public_description:
Some("For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent \'filters\' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select \'MISS_OPC_MATCH\' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)"),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
Some("CBoFilter[31:23]"),
extsel:
false,}),
("UNC_Q_TxL_FLITS_G2.NCB_DATA",
IntelPerformanceCounterDescription{event_code:
Tuple::One(1),
umask:
Tuple::One(4),
event_name:
"UNC_Q_TxL_FLITS_G2.NCB_DATA",
brief_description:
"Flits Transferred - Group 2; Non-Coherent data Tx Flits",
public_description:
Some("Counts the number of flits trasmitted across the QPI Link. This is one of three \'groups\' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each \'flit\' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four \'fits\', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI \'speed\' (for example, 8.0 GT/s), the \'transfers\' here refer to \'fits\'. Therefore, in L0, the system will transfer 1 \'flit\' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as \'data\' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual \'data\' and an additional 16 bits of other information. To calculate \'data\' bandwidth, one should therefore do: data flits * 8B / time."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_H_TxR_BL_CYCLES_NE.SCHED1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(53),
umask:
Tuple::One(2),
event_name:
"UNC_H_TxR_BL_CYCLES_NE.SCHED1",
brief_description:
"BL Egress Not Empty; Scheduler 1",
public_description:
Some("BL Egress Not Empty"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_Q_DIRECT2CORE.FAILURE_CREDITS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(19),
umask:
Tuple::One(2),
event_name:
"UNC_Q_DIRECT2CORE.FAILURE_CREDITS",
brief_description:
"Direct 2 Core Spawning; Spawn Failure - Egress Credits",
public_description:
Some("Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exlusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK",
IntelPerformanceCounterDescription{event_code:
Tuple::One(69),
umask:
Tuple::One(1),
event_name:
"UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK",
brief_description:
"Cycles PHOLD Assert to Ack; Assert to ACK",
public_description:
Some("PHOLD cycles. Filter from source CoreID."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("UBOX"),
filter:
None,
extsel:
true,}),
("UNC_H_TxR_AD_CYCLES_FULL.ALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(42),
umask:
Tuple::One(3),
event_name:
"UNC_H_TxR_AD_CYCLES_FULL.ALL",
brief_description:
"AD Egress Full; All",
public_description:
Some("AD Egress Full"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_I_RxR_AK_OCCUPANCY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(12),
umask:
Tuple::One(0),
event_name:
"UNC_I_RxR_AK_OCCUPANCY",
brief_description:
"tbd",
public_description:
Some("Accumulates the occupancy of the AK Ingress in each cycles. This queue is where the IRP receives responses from R2PCIe (the ring)."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_STALLS.BGF_NCB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(53),
umask:
Tuple::One(2),
event_name:
"UNC_Q_RxL_STALLS.BGF_NCB",
brief_description:
"Stalls Sending to R3QPI; BGF Stall - SNP",
public_description:
Some("Number of stalls trying to send to R3QPI."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_I_CACHE_OWN_OCCUPANCY.ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(19),
umask:
Tuple::One(1),
event_name:
"UNC_I_CACHE_OWN_OCCUPANCY.ANY",
brief_description:
"Outstanding Write Ownership Occupancy; Any Source",
public_description:
Some("Accumulates the number of writes (and write prefetches) that are outstanding in the uncore trying to acquire ownership in each cycle. This can be used with the write transaction count to calculate the average write latency in the uncore. The occupancy increments when a write request is issued, and decrements when the data is returned."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_I_CACHE_WRITE_OCCUPANCY.ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(17),
umask:
Tuple::One(1),
event_name:
"UNC_I_CACHE_WRITE_OCCUPANCY.ANY",
brief_description:
"Outstanding Write Occupancy; Any Source",
public_description:
Some("Accumulates the number of writes (and write prefetches) that are outstanding in the uncore in each cycle. This can be used with the transaction count event to calculate the average latency in the uncore. The occupancy increments when the ownership fetch/prefetch is issued, and decrements the data is returned to the uncore."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_M_POWER_CHANNEL_DLLOFF",
IntelPerformanceCounterDescription{event_code:
Tuple::One(132),
umask:
Tuple::One(0),
event_name:
"UNC_M_POWER_CHANNEL_DLLOFF",
brief_description:
"Channel DLLOFF Cycles",
public_description:
Some("Number of cycles when all the ranks in the channel are in CKE Slow (DLLOFF) mode."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_H_TAD_REQUESTS_G0.REGION7",
IntelPerformanceCounterDescription{event_code:
Tuple::One(27),
umask:
Tuple::One(128),
event_name:
"UNC_H_TAD_REQUESTS_G0.REGION7",
brief_description:
"HA Requests to a TAD Region - Group 0; TAD Region 7",
public_description:
Some("Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for \'Monroe\' systems that use the TAD to enable individual channels to enter self-refresh to save power."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_FLITS_G1.DRS_DATA",
IntelPerformanceCounterDescription{event_code:
Tuple::One(2),
umask:
Tuple::One(8),
event_name:
"UNC_Q_RxL_FLITS_G1.DRS_DATA",
brief_description:
"Flits Received - Group 1; DRS Data Flits",
public_description:
Some("Counts the number of flits received from the QPI Link. This is one of three \'groups\' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each \'flit\' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four \'fits\', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI \'speed\' (for example, 8.0 GT/s), the \'transfers\' here refer to \'fits\'. Therefore, in L0, the system will transfer 1 \'flit\' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as \'data\' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual \'data\' and an additional 16 bits of other information. To calculate \'data\' bandwidth, one should therefore do: data flits * 8B / time."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_C_TOR_INSERTS.WB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(53),
umask:
Tuple::One(16),
event_name:
"UNC_C_TOR_INSERTS.WB",
brief_description:
"TOR Inserts; Writebacks",
public_description:
Some("Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent \'filters\' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select \'MISS_OPC_MATCH\' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_I_CACHE_READ_OCCUPANCY.SOURCE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(16),
umask:
Tuple::One(2),
event_name:
"UNC_I_CACHE_READ_OCCUPANCY.SOURCE",
brief_description:
"Outstanding Read Occupancy; Select Source",
public_description:
Some("Accumulates the number of reads that are outstanding in the uncore in each cycle. This can be used with the read transaction count to calculate the average read latency in the uncore. The occupancy increments when a read request is issued, and decrements when the data is returned."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN3",
IntelPerformanceCounterDescription{event_code:
Tuple::One(25),
umask:
Tuple::One(8),
event_name:
"UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN3",
brief_description:
"HA iMC CHN0 WPQ Credits Empty - Special; Channel 3",
public_description:
Some("Counts the number of cycles when there are no \'special\' credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC\'s WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and \'special\' requests such as ISOCH writes. This count only tracks the \'special\' credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_C_TOR_OCCUPANCY.MISS_OPCODE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(54),
umask:
Tuple::One(3),
event_name:
"UNC_C_TOR_OCCUPANCY.MISS_OPCODE",
brief_description:
"TOR Occupancy; Miss Opcode Match",
public_description:
Some("For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent \'filters\' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select \'MISS_OPC_MATCH\' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)"),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
Some("CBoFilter[31:23]"),
extsel:
false,}),
("UNC_R3_RxR_OCCUPANCY.HOM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(19),
umask:
Tuple::One(1),
event_name:
"UNC_R3_RxR_OCCUPANCY.HOM",
brief_description:
"Ingress Occupancy Accumulator; HOM",
public_description:
Some("Accumulates the occupancy of a given QPI Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency."),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_M_CAS_COUNT.RD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(4),
umask:
Tuple::One(3),
event_name:
"UNC_M_CAS_COUNT.RD",
brief_description:
"DRAM RD_CAS and WR_CAS Commands.; All DRAM Reads (RD_CAS + Underfills)",
public_description:
Some("DRAM RD_CAS and WR_CAS Commands"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_C_RxR_INT_STARVED.ISMQ",
IntelPerformanceCounterDescription{event_code:
Tuple::One(20),
umask:
Tuple::One(8),
event_name:
"UNC_C_RxR_INT_STARVED.ISMQ",
brief_description:
"Ingress Internal Starvation Cycles; ISMQ",
public_description:
Some("Counts cycles in internal starvation. This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_P_DEMOTIONS_CORE0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(30),
umask:
Tuple::One(0),
event_name:
"UNC_P_DEMOTIONS_CORE0",
brief_description:
"Core C State Demotions",
public_description:
Some("Counts the number of times when a configurable cores had a C-state demotion"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
Some("PCUFilter[7:0]"),
extsel:
false,}),
("UNC_I_RxR_BL_NCS_OCCUPANCY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(9),
umask:
Tuple::One(0),
event_name:
"UNC_I_RxR_BL_NCS_OCCUPANCY",
brief_description:
"tbd",
public_description:
Some("Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_AD_OCCUPANCY.ALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(40),
umask:
Tuple::One(3),
event_name:
"UNC_H_TxR_AD_OCCUPANCY.ALL",
brief_description:
"AD Egress Occupancy; All",
public_description:
Some("AD Egress Occupancy"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_R3_VNA_CREDITS_ACQUIRED",
IntelPerformanceCounterDescription{event_code:
Tuple::One(51),
umask:
Tuple::One(0),
event_name:
"UNC_R3_VNA_CREDITS_ACQUIRED",
brief_description:
"VNA credit Acquisitions",
public_description:
Some("Number of QPI VNA Credit acquisitions. This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder. VNA credits are used by all message classes in order to communicate across QPI. If a packet is unable to acquire credits, it will then attempt to use credts from the VN0 pool. Note that a single packet may require multiple flit buffers (i.e. when data is being transfered). Therefore, this event will increment by the number of credits acquired in each cycle. Filtering based on message class is not provided. One can count the number of packets transfered in a given message class using an qfclk event."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_C_RING_AD_USED.UP_ODD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(27),
umask:
Tuple::One(2),
event_name:
"UNC_C_RING_AD_USED.UP_ODD",
brief_description:
"AD Ring In Use; Up and Odd",
public_description:
Some("Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the \'UP\' direction is on the clockwise ring and \'DN\' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring."),
counter:
Counter::Programmable(12),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_P_DEMOTIONS_CORE4",
IntelPerformanceCounterDescription{event_code:
Tuple::One(34),
umask:
Tuple::One(0),
event_name:
"UNC_P_DEMOTIONS_CORE4",
brief_description:
"Core C State Demotions",
public_description:
Some("Counts the number of times when a configurable cores had a C-state demotion"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
Some("PCUFilter[7:0]"),
extsel:
false,}),
("UNC_Q_RxL_CRC_ERRORS.NORMAL_OP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(3),
umask:
Tuple::One(2),
event_name:
"UNC_Q_RxL_CRC_ERRORS.NORMAL_OP",
brief_description:
"CRC Errors Detected; Normal Operations",
public_description:
Some("Number of CRC errors detected in the QPI Agent. Each QPI flit incorporates 8 bits of CRC for error detection. This counts the number of flits where the CRC was able to detect an error. After an error has been detected, the QPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it)."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_C_RING_AK_USED.UP_EVEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(28),
umask:
Tuple::One(1),
event_name:
"UNC_C_RING_AK_USED.UP_EVEN",
brief_description:
"AK Ring In Use; Up and Even",
public_description:
Some("Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the \'UP\' direction is on the clockwise ring and \'DN\' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring."),
counter:
Counter::Programmable(12),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_AD_CYCLES_NE.SCHED0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(41),
umask:
Tuple::One(1),
event_name:
"UNC_H_TxR_AD_CYCLES_NE.SCHED0",
brief_description:
"AD Egress Not Empty; Scheduler 0",
public_description:
Some("AD Egress Not Empty"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_FLITS_G1.HOM_NONREQ",
IntelPerformanceCounterDescription{event_code:
Tuple::One(2),
umask:
Tuple::One(4),
event_name:
"UNC_Q_RxL_FLITS_G1.HOM_NONREQ",
brief_description:
"Flits Received - Group 1; HOM Non-Request Flits",
public_description:
Some("Counts the number of flits received from the QPI Link. This is one of three \'groups\' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each \'flit\' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four \'fits\', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI \'speed\' (for example, 8.0 GT/s), the \'transfers\' here refer to \'fits\'. Therefore, in L0, the system will transfer 1 \'flit\' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as \'data\' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual \'data\' and an additional 16 bits of other information. To calculate \'data\' bandwidth, one should therefore do: data flits * 8B / time."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_C_RING_AD_USED.DOWN_EVEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(27),
umask:
Tuple::One(4),
event_name:
"UNC_C_RING_AD_USED.DOWN_EVEN",
brief_description:
"AD Ring In Use; Down and Even",
public_description:
Some("Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the \'UP\' direction is on the clockwise ring and \'DN\' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring."),
counter:
Counter::Programmable(12),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_R2_RING_AK_USED.CCW_ODD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(8),
umask:
Tuple::One(8),
event_name:
"UNC_R2_RING_AK_USED.CCW_ODD",
brief_description:
"R2 AK Ring in Use; Counterclockwise and Odd",
public_description:
Some("Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_R3_IIO_CREDITS_ACQUIRED.NCB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(32),
umask:
Tuple::One(16),
event_name:
"UNC_R3_IIO_CREDITS_ACQUIRED.NCB",
brief_description:
"to IIO BL Credit Acquired",
public_description:
Some("Counts the number of times the NCS/NCB/DRS credit is acquried in the QPI for sending messages on BL to the IIO. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transfering data without coherency, and DRS is used for transfering data with coherency (cachable PCI transactions). This event can only track one message class at a time."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_R2_RING_BL_USED.CCW_ODD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(9),
umask:
Tuple::One(8),
event_name:
"UNC_R2_RING_BL_USED.CCW_ODD",
brief_description:
"R2 BL Ring in Use; Counterclockwise and Odd",
public_description:
Some("Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_AK_CYCLES_FULL.ALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(50),
umask:
Tuple::One(3),
event_name:
"UNC_H_TxR_AK_CYCLES_FULL.ALL",
brief_description:
"AK Egress Full; All",
public_description:
Some("AK Egress Full"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_R3_VNA_CREDITS_REJECT.NCS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(52),
umask:
Tuple::One(32),
event_name:
"UNC_R3_VNA_CREDITS_REJECT.NCS",
brief_description:
"VNA Credit Reject; NCS Message Class",
public_description:
Some("Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_C_TOR_INSERTS.MISS_OPCODE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(53),
umask:
Tuple::One(3),
event_name:
"UNC_C_TOR_INSERTS.MISS_OPCODE",
brief_description:
"TOR Inserts; Miss Opcode Match",
public_description:
Some("Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent \'filters\' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select \'MISS_OPC_MATCH\' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
Some("CBoFilter[31:23]"),
extsel:
false,}),
("UNC_R3_RING_BL_USED.CW_ODD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(9),
umask:
Tuple::One(2),
event_name:
"UNC_R3_RING_BL_USED.CW_ODD",
brief_description:
"R3 BL Ring in Use; Clockwise and Odd",
public_description:
Some("Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop."),
counter:
Counter::Programmable(7),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_R2_TxR_CYCLES_FULL.AD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(37),
umask:
Tuple::One(1),
event_name:
"UNC_R2_TxR_CYCLES_FULL.AD",
brief_description:
"Egress Cycles Full; AD",
public_description:
Some("Counts the number of cycles when the R2PCIe Egress buffer is full."),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL0P_POWER_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(16),
umask:
Tuple::One(0),
event_name:
"UNC_Q_RxL0P_POWER_CYCLES",
brief_description:
"Cycles in L0p",
public_description:
Some("Number of QPI qfclk cycles spent in L0p power mode. L0p is a mode where we disable 1/2 of the QPI lanes, decreasing our bandwidth in order to save power. It increases snoop and data transfer latencies and decreases overall bandwidth. This mode can be very useful in NUMA optimized workloads that largely only utilize QPI for snoops and their responses. Use edge detect to count the number of instances when the QPI link entered L0p. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_C_TOR_INSERTS.NID_ALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(53),
umask:
Tuple::One(72),
event_name:
"UNC_C_TOR_INSERTS.NID_ALL",
brief_description:
"TOR Inserts; NID Matched",
public_description:
Some("Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent \'filters\' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select \'MISS_OPC_MATCH\' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
Some("CBoFilter[17:10]"),
extsel:
false,}),
("UNC_H_TAD_REQUESTS_G0.REGION5",
IntelPerformanceCounterDescription{event_code:
Tuple::One(27),
umask:
Tuple::One(32),
event_name:
"UNC_H_TAD_REQUESTS_G0.REGION5",
brief_description:
"HA Requests to a TAD Region - Group 0; TAD Region 5",
public_description:
Some("Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for \'Monroe\' systems that use the TAD to enable individual channels to enter self-refresh to save power."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_C_TOR_OCCUPANCY.NID_ALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(54),
umask:
Tuple::One(72),
event_name:
"UNC_C_TOR_OCCUPANCY.NID_ALL",
brief_description:
"TOR Occupancy; NID Matched",
public_description:
Some("For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent \'filters\' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select \'MISS_OPC_MATCH\' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)"),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
Some("CBoFilter[17:10]"),
extsel:
false,}),
("UNC_P_FREQ_MAX_POWER_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(5),
umask:
Tuple::One(0),
event_name:
"UNC_P_FREQ_MAX_POWER_CYCLES",
brief_description:
"Power Strongest Upper Limit Cycles",
public_description:
Some("Counts the number of cycles when power is the upper limit on frequency."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_R3_RxR_INSERTS.NCB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(17),
umask:
Tuple::One(16),
event_name:
"UNC_R3_RxR_INSERTS.NCB",
brief_description:
"Ingress Allocations; NCB",
public_description:
Some("Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_R3_IIO_CREDITS_REJECT.NCB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(33),
umask:
Tuple::One(16),
event_name:
"UNC_R3_IIO_CREDITS_REJECT.NCB",
brief_description:
"to IIO BL Credit Rejected",
public_description:
Some("Counts the number of times that a request attempted to acquire an NCS/NCB/DRS credit in the QPI for sending messages on BL to the IIO but was rejected because no credit was available. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transfering data without coherency, and DRS is used for transfering data with coherency (cachable PCI transactions). This event can only track one message class at a time."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_R3_RxR_CYCLES_NE.NDR",
IntelPerformanceCounterDescription{event_code:
Tuple::One(16),
umask:
Tuple::One(4),
event_name:
"UNC_R3_RxR_CYCLES_NE.NDR",
brief_description:
"Ingress Cycles Not Empty; NDR",
public_description:
Some("Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_C_RxR_IPQ_RETRY.QPI_CREDITS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(49),
umask:
Tuple::One(16),
event_name:
"UNC_C_RxR_IPQ_RETRY.QPI_CREDITS",
brief_description:
"Probe Queue Retries; No QPI Credits",
public_description:
Some("Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_R2_RxR_AK_BOUNCES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(18),
umask:
Tuple::One(0),
event_name:
"UNC_R2_RxR_AK_BOUNCES",
brief_description:
"AK Ingress Bounced",
public_description:
Some("Counts the number of times when a request destined for the AK ingress bounced."),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_M_POWER_THROTTLE_CYCLES.RANK1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(65),
umask:
Tuple::One(2),
event_name:
"UNC_M_POWER_THROTTLE_CYCLES.RANK1",
brief_description:
"Throttle Cycles for Rank 0; DIMM ID",
public_description:
Some("Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_C_RxR_IPQ_RETRY.FULL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(49),
umask:
Tuple::One(2),
event_name:
"UNC_C_RxR_IPQ_RETRY.FULL",
brief_description:
"Probe Queue Retries; No Egress Credits",
public_description:
Some("Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_C_RING_SINK_STARVED.AD_CACHE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(6),
umask:
Tuple::One(1),
event_name:
"UNC_C_RING_SINK_STARVED.AD_CACHE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_H_TAD_REQUESTS_G0.REGION4",
IntelPerformanceCounterDescription{event_code:
Tuple::One(27),
umask:
Tuple::One(16),
event_name:
"UNC_H_TAD_REQUESTS_G0.REGION4",
brief_description:
"HA Requests to a TAD Region - Group 0; TAD Region 4",
public_description:
Some("Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for \'Monroe\' systems that use the TAD to enable individual channels to enter self-refresh to save power."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_R2_IIO_CREDITS_ACQUIRED.NCS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(51),
umask:
Tuple::One(32),
event_name:
"UNC_R2_IIO_CREDITS_ACQUIRED.NCS",
brief_description:
"R2PCIe IIO Credit Acquired; NCS",
public_description:
Some("Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly)."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_R2_RING_AK_USED.CW_ODD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(8),
umask:
Tuple::One(2),
event_name:
"UNC_R2_RING_AK_USED.CW_ODD",
brief_description:
"R2 AK Ring in Use; Clockwise and Odd",
public_description:
Some("Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_R3_RING_AK_USED.CCW_EVEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(8),
umask:
Tuple::One(4),
event_name:
"UNC_R3_RING_AK_USED.CCW_EVEN",
brief_description:
"R3 AK Ring in Use; Counterclockwise and Even",
public_description:
Some("Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop."),
counter:
Counter::Programmable(7),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_H_BYPASS_IMC.NOT_TAKEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(20),
umask:
Tuple::One(2),
event_name:
"UNC_H_BYPASS_IMC.NOT_TAKEN",
brief_description:
"HA to iMC Bypass; Not Taken",
public_description:
Some("Counts the number of times when the HA was able to bypass was attempted. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filted by when the bypass was taken and when it was not."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_C_RxR_INSERTS.IRQ_REJECTED",
IntelPerformanceCounterDescription{event_code:
Tuple::One(19),
umask:
Tuple::One(2),
event_name:
"UNC_C_RxR_INSERTS.IRQ_REJECTED",
brief_description:
"Ingress Allocations; IRQ Rejected",
public_description:
Some("Counts number of allocations per cycle into the specified Ingress queue."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_H_RING_AD_USED.CCW_ODD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(62),
umask:
Tuple::One(8),
event_name:
"UNC_H_RING_AD_USED.CCW_ODD",
brief_description:
"HA AD Ring in Use; Counterclockwise and Odd",
public_description:
Some("Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_CONFLICT_CYCLES.CONFLICT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(11),
umask:
Tuple::One(2),
event_name:
"UNC_H_CONFLICT_CYCLES.CONFLICT",
brief_description:
"Conflict Checks; Conflict Detected",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_R3_VNA_CREDITS_REJECT.DRS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(52),
umask:
Tuple::One(8),
event_name:
"UNC_R3_VNA_CREDITS_REJECT.DRS",
brief_description:
"VNA Credit Reject; DRS Message Class",
public_description:
Some("Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_C_RxR_INT_STARVED.IRQ",
IntelPerformanceCounterDescription{event_code:
Tuple::One(20),
umask:
Tuple::One(1),
event_name:
"UNC_C_RxR_INT_STARVED.IRQ",
brief_description:
"Ingress Internal Starvation Cycles; IRQ",
public_description:
Some("Counts cycles in internal starvation. This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_AK_INSERTS.SCHED1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(47),
umask:
Tuple::One(2),
event_name:
"UNC_H_TxR_AK_INSERTS.SCHED1",
brief_description:
"AK Egress Allocations; Scheduler 1",
public_description:
Some("AK Egress Allocations"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_P_CORE0_TRANSITION_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(3),
umask:
Tuple::One(0),
event_name:
"UNC_P_CORE0_TRANSITION_CYCLES",
brief_description:
"Core C State Transition Cycles",
public_description:
Some("Number of cycles spent performing core C state transitions. There is one event per core."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
true,}),
("UNC_R3_RxR_INSERTS.SNP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(17),
umask:
Tuple::One(2),
event_name:
"UNC_R3_RxR_INSERTS.SNP",
brief_description:
"Ingress Allocations; SNP",
public_description:
Some("Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_M_ACT_COUNT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(1),
umask:
Tuple::One(0),
event_name:
"UNC_M_ACT_COUNT",
brief_description:
"DRAM Activate Count",
public_description:
Some("Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(25),
umask:
Tuple::One(1),
event_name:
"UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN0",
brief_description:
"HA iMC CHN0 WPQ Credits Empty - Special; Channel 0",
public_description:
Some("Counts the number of cycles when there are no \'special\' credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC\'s WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and \'special\' requests such as ISOCH writes. This count only tracks the \'special\' credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL0_POWER_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(15),
umask:
Tuple::One(0),
event_name:
"UNC_Q_RxL0_POWER_CYCLES",
brief_description:
"Cycles in L0",
public_description:
Some("Number of QPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxL_FLITS_G2.NDR_AK",
IntelPerformanceCounterDescription{event_code:
Tuple::One(1),
umask:
Tuple::One(2),
event_name:
"UNC_Q_TxL_FLITS_G2.NDR_AK",
brief_description:
"Flits Transferred - Group 2; Non-Data Response Tx Flits - AK",
public_description:
Some("Counts the number of flits trasmitted across the QPI Link. This is one of three \'groups\' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each \'flit\' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four \'fits\', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI \'speed\' (for example, 8.0 GT/s), the \'transfers\' here refer to \'fits\'. Therefore, in L0, the system will transfer 1 \'flit\' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as \'data\' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual \'data\' and an additional 16 bits of other information. To calculate \'data\' bandwidth, one should therefore do: data flits * 8B / time."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_C_TOR_OCCUPANCY.MISS_ALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(54),
umask:
Tuple::One(10),
event_name:
"UNC_C_TOR_OCCUPANCY.MISS_ALL",
brief_description:
"TOR Occupancy; Miss All",
public_description:
Some("For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent \'filters\' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select \'MISS_OPC_MATCH\' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)"),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_R3_RING_AD_USED.CW_EVEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(7),
umask:
Tuple::One(1),
event_name:
"UNC_R3_RING_AD_USED.CW_EVEN",
brief_description:
"R3 AD Ring in Use; Clockwise and Even",
public_description:
Some("Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop."),
counter:
Counter::Programmable(7),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxL_FLITS_G1.HOM_NONREQ",
IntelPerformanceCounterDescription{event_code:
Tuple::One(0),
umask:
Tuple::One(4),
event_name:
"UNC_Q_TxL_FLITS_G1.HOM_NONREQ",
brief_description:
"Flits Transferred - Group 1; HOM Non-Request Flits",
public_description:
Some("Counts the number of flits trasmitted across the QPI Link. This is one of three \'groups\' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each \'flit\' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four \'fits\', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI \'speed\' (for example, 8.0 GT/s), the \'transfers\' here refer to \'fits\'. Therefore, in L0, the system will transfer 1 \'flit\' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as \'data\' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual \'data\' and an additional 16 bits of other information. To calculate \'data\' bandwidth, one should therefore do: data flits * 8B / time."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_I_RxR_BL_DRS_CYCLES_FULL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(4),
umask:
Tuple::One(0),
event_name:
"UNC_I_RxR_BL_DRS_CYCLES_FULL",
brief_description:
"tbd",
public_description:
Some("Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_C_TxR_INSERTS.AD_CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(2),
umask:
Tuple::One(16),
event_name:
"UNC_C_TxR_INSERTS.AD_CORE",
brief_description:
"Egress Allocations; AD - Corebo",
public_description:
Some("Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_I_RxR_BL_DRS_INSERTS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(1),
umask:
Tuple::One(0),
event_name:
"UNC_I_RxR_BL_DRS_INSERTS",
brief_description:
"BL Ingress Occupancy - DRS",
public_description:
Some("Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_H_TAD_REQUESTS_G0.REGION2",
IntelPerformanceCounterDescription{event_code:
Tuple::One(27),
umask:
Tuple::One(4),
event_name:
"UNC_H_TAD_REQUESTS_G0.REGION2",
brief_description:
"HA Requests to a TAD Region - Group 0; TAD Region 2",
public_description:
Some("Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for \'Monroe\' systems that use the TAD to enable individual channels to enter self-refresh to save power."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_RING_BL_USED.CCW_ODD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(64),
umask:
Tuple::One(8),
event_name:
"UNC_H_RING_BL_USED.CCW_ODD",
brief_description:
"HA BL Ring in Use; Counterclockwise and Odd",
public_description:
Some("Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_I_WRITE_ORDERING_STALL_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(26),
umask:
Tuple::One(0),
event_name:
"UNC_I_WRITE_ORDERING_STALL_CYCLES",
brief_description:
"Write Ordering Stalls",
public_description:
Some("Counts the number of cycles when there are pending write ACK\'s in the switch but the switch->IRP pipeline is not utilized."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_AK_NDR",
IntelPerformanceCounterDescription{event_code:
Tuple::One(14),
umask:
Tuple::One(0),
event_name:
"UNC_H_TxR_AK_NDR",
brief_description:
"Outbound NDR Ring Transactions",
public_description:
Some("Counts the number of outbound NDR transactions sent on the AK ring. NDR stands for \'non-data response\' and is generally used for completions that do not include data. AK NDR is used for messages to the local socket."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_I_TxR_BL_STALL_CREDIT_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(25),
umask:
Tuple::One(0),
event_name:
"UNC_I_TxR_BL_STALL_CREDIT_CYCLES",
brief_description:
"No BL Egress Credit Stalls",
public_description:
Some("Counts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_BL_CYCLES_FULL.SCHED1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(54),
umask:
Tuple::One(2),
event_name:
"UNC_H_TxR_BL_CYCLES_FULL.SCHED1",
brief_description:
"BL Egress Full; Scheduler 1",
public_description:
Some("BL Egress Full"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_BL_INSERTS.SCHED0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(51),
umask:
Tuple::One(1),
event_name:
"UNC_H_TxR_BL_INSERTS.SCHED0",
brief_description:
"BL Egress Allocations; Scheduler 0",
public_description:
Some("BL Egress Allocations"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(24),
umask:
Tuple::One(2),
event_name:
"UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN1",
brief_description:
"HA iMC CHN0 WPQ Credits Empty - Regular; Channel 1",
public_description:
Some("Counts the number of cycles when there are no \'regular\' credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC\'s WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and \'special\' requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN2",
IntelPerformanceCounterDescription{event_code:
Tuple::One(25),
umask:
Tuple::One(4),
event_name:
"UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN2",
brief_description:
"HA iMC CHN0 WPQ Credits Empty - Special; Channel 2",
public_description:
Some("Counts the number of cycles when there are no \'special\' credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC\'s WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and \'special\' requests such as ISOCH writes. This count only tracks the \'special\' credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_C_TOR_INSERTS.NID_OPCODE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(53),
umask:
Tuple::One(65),
event_name:
"UNC_C_TOR_INSERTS.NID_OPCODE",
brief_description:
"TOR Inserts; NID and Opcode Matched",
public_description:
Some("Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent \'filters\' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select \'MISS_OPC_MATCH\' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
Some("CBoFilter[31:23], CBoFilter[17:10]"),
extsel:
false,}),
("UNC_Q_RxL_BYPASSED",
IntelPerformanceCounterDescription{event_code:
Tuple::One(9),
umask:
Tuple::One(0),
event_name:
"UNC_Q_RxL_BYPASSED",
brief_description:
"Rx Flit Buffer Bypassed",
public_description:
Some("Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of flits transfered, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_R2_IIO_CREDITS_REJECT.NCB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(52),
umask:
Tuple::One(16),
event_name:
"UNC_R2_IIO_CREDITS_REJECT.NCB",
brief_description:
"R2PCIe IIO Failed to Acquire a Credit; NCB",
public_description:
Some("Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly)."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_I_CACHE_READ_OCCUPANCY.ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(16),
umask:
Tuple::One(1),
event_name:
"UNC_I_CACHE_READ_OCCUPANCY.ANY",
brief_description:
"Outstanding Read Occupancy; Any Source",
public_description:
Some("Accumulates the number of reads that are outstanding in the uncore in each cycle. This can be used with the read transaction count to calculate the average read latency in the uncore. The occupancy increments when a read request is issued, and decrements when the data is returned."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxL_FLITS_G0.IDLE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(0),
umask:
Tuple::One(1),
event_name:
"UNC_Q_TxL_FLITS_G0.IDLE",
brief_description:
"Flits Transferred - Group 0; Idle and Null Flits",
public_description:
Some("Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each \'flit\' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four \'fits\', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI \'speed\' (for example, 8.0 GT/s), the \'transfers\' here refer to \'fits\'. Therefore, in L0, the system will transfer 1 \'flit\' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as \'data\' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual \'data\' and an additional 16 bits of other information. To calculate \'data\' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_U_U2C_EVENTS.CMC",
IntelPerformanceCounterDescription{event_code:
Tuple::One(67),
umask:
Tuple::One(16),
event_name:
"UNC_U_U2C_EVENTS.CMC",
brief_description:
"Monitor Sent to T0; Correctable Machine Check",
public_description:
Some("Events coming from Uncore can be sent to one or all cores"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("UBOX"),
filter:
None,
extsel:
false,}),
("UNC_R2_TxR_NACKS.BL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(38),
umask:
Tuple::One(4),
event_name:
"UNC_R2_TxR_NACKS.BL",
brief_description:
"Egress NACK; BL",
public_description:
Some("Counts the number of times that the Egress received a NACK from the ring and could not issue a transaction."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_INSERTS_NCS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(11),
umask:
Tuple::One(0),
event_name:
"UNC_Q_RxL_INSERTS_NCS",
brief_description:
"Rx Flit Buffer Allocations - NCS",
public_description:
Some("Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCS flits."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_R3_RxR_CYCLES_NE.HOM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(16),
umask:
Tuple::One(1),
event_name:
"UNC_R3_RxR_CYCLES_NE.HOM",
brief_description:
"Ingress Cycles Not Empty; HOM",
public_description:
Some("Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_C_TxR_INSERTS.AK_CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(2),
umask:
Tuple::One(32),
event_name:
"UNC_C_TxR_INSERTS.AK_CORE",
brief_description:
"Egress Allocations; AK - Corebo",
public_description:
Some("Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_AD.NDR",
IntelPerformanceCounterDescription{event_code:
Tuple::One(15),
umask:
Tuple::One(1),
event_name:
"UNC_H_TxR_AD.NDR",
brief_description:
"Outbound NDR Ring Transactions; Non-data Responses",
public_description:
Some("Counts the number of outbound transactions on the AD ring. This can be filtered by the NDR and SNP message classes. See the filter descriptions for more details."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_AD_INSERTS.SCHED1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(39),
umask:
Tuple::One(2),
event_name:
"UNC_H_TxR_AD_INSERTS.SCHED1",
brief_description:
"AD Egress Allocations; Scheduler 1",
public_description:
Some("AD Egress Allocations"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_IMC_WRITES.FULL_ISOCH",
IntelPerformanceCounterDescription{event_code:
Tuple::One(26),
umask:
Tuple::One(4),
event_name:
"UNC_H_IMC_WRITES.FULL_ISOCH",
brief_description:
"HA to iMC Full Line Writes Issued; ISOCH Full Line",
public_description:
Some("Counts the total number of full line writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_FLITS_G0.IDLE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(1),
umask:
Tuple::One(1),
event_name:
"UNC_Q_RxL_FLITS_G0.IDLE",
brief_description:
"Flits Received - Group 0; Idle and Null Flits",
public_description:
Some("Counts the number of flits received from the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each \'flit\' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four \'fits\', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI \'speed\' (for example, 8.0 GT/s), the \'transfers\' here refer to \'fits\'. Therefore, in L0, the system will transfer 1 \'flit\' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as \'data\' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual \'data\' and an additional 16 bits of other information. To calculate \'data\' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_M_CAS_COUNT.RD_UNDERFILL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(4),
umask:
Tuple::One(2),
event_name:
"UNC_M_CAS_COUNT.RD_UNDERFILL",
brief_description:
"DRAM RD_CAS and WR_CAS Commands.; Underfill Read Issued",
public_description:
Some("DRAM RD_CAS and WR_CAS Commands"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_POWER_CKE_CYCLES.RANK0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(131),
umask:
Tuple::One(1),
event_name:
"UNC_M_POWER_CKE_CYCLES.RANK0",
brief_description:
"CKE_ON_CYCLES by Rank; DIMM ID",
public_description:
Some("Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary)."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxL0P_POWER_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(13),
umask:
Tuple::One(0),
event_name:
"UNC_Q_TxL0P_POWER_CYCLES",
brief_description:
"Cycles in L0p",
public_description:
Some("Number of QPI qfclk cycles spent in L0p power mode. L0p is a mode where we disable 1/2 of the QPI lanes, decreasing our bandwidth in order to save power. It increases snoop and data transfer latencies and decreases overall bandwidth. This mode can be very useful in NUMA optimized workloads that largely only utilize QPI for snoops and their responses. Use edge detect to count the number of instances when the QPI link entered L0p. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_R3_VN0_CREDITS_REJECT.DRS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(55),
umask:
Tuple::One(8),
event_name:
"UNC_R3_VN0_CREDITS_REJECT.DRS",
brief_description:
"VN0 Credit Acquisition Failed on DRS; DRS Message Class",
public_description:
Some("Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_CREDITS_CONSUMED_VN0.DRS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(30),
umask:
Tuple::One(1),
event_name:
"UNC_Q_RxL_CREDITS_CONSUMED_VN0.DRS",
brief_description:
"VN0 Credit Consumed; DRS",
public_description:
Some("Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_Q_RxL_FLITS_G1.SNP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(2),
umask:
Tuple::One(1),
event_name:
"UNC_Q_RxL_FLITS_G1.SNP",
brief_description:
"Flits Received - Group 1; SNP Flits",
public_description:
Some("Counts the number of flits received from the QPI Link. This is one of three \'groups\' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each \'flit\' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four \'fits\', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI \'speed\' (for example, 8.0 GT/s), the \'transfers\' here refer to \'fits\'. Therefore, in L0, the system will transfer 1 \'flit\' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as \'data\' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual \'data\' and an additional 16 bits of other information. To calculate \'data\' bandwidth, one should therefore do: data flits * 8B / time."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_R3_VN0_CREDITS_USED.HOM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(54),
umask:
Tuple::One(1),
event_name:
"UNC_R3_VN0_CREDITS_USED.HOM",
brief_description:
"VN0 Credit Used; HOM Message Class",
public_description:
Some("Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_C_TOR_OCCUPANCY.NID_MISS_ALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(54),
umask:
Tuple::One(74),
event_name:
"UNC_C_TOR_OCCUPANCY.NID_MISS_ALL",
brief_description:
"TOR Occupancy; NID Matched",
public_description:
Some("For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent \'filters\' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select \'MISS_OPC_MATCH\' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)"),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
Some("CBoFilter[17:10]"),
extsel:
false,}),
("UNC_Q_RxL_OCCUPANCY_NCS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(23),
umask:
Tuple::One(0),
event_name:
"UNC_Q_RxL_OCCUPANCY_NCS",
brief_description:
"RxQ Occupancy - NCS",
public_description:
Some("Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCS flits only."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_R2_TxR_NACKS.AK",
IntelPerformanceCounterDescription{event_code:
Tuple::One(38),
umask:
Tuple::One(2),
event_name:
"UNC_R2_TxR_NACKS.AK",
brief_description:
"Egress NACK; AK",
public_description:
Some("Counts the number of times that the Egress received a NACK from the ring and could not issue a transaction."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_BL_CYCLES_FULL.ALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(54),
umask:
Tuple::One(3),
event_name:
"UNC_H_TxR_BL_CYCLES_FULL.ALL",
brief_description:
"BL Egress Full; All",
public_description:
Some("BL Egress Full"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_C_RxR_IRQ_RETRY.FULL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(50),
umask:
Tuple::One(2),
event_name:
"UNC_C_RxR_IRQ_RETRY.FULL",
brief_description:
"Ingress Request Queue Rejects; No Egress Credits",
public_description:
None,
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_C_RING_SINK_STARVED.IV_CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(6),
umask:
Tuple::One(8),
event_name:
"UNC_C_RING_SINK_STARVED.IV_CORE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_BL_OCCUPANCY.SCHED1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(52),
umask:
Tuple::One(2),
event_name:
"UNC_H_TxR_BL_OCCUPANCY.SCHED1",
brief_description:
"BL Egress Occupancy; Scheduler 1",
public_description:
Some("BL Egress Occupancy"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_CAS_COUNT.RD_REG",
IntelPerformanceCounterDescription{event_code:
Tuple::One(4),
umask:
Tuple::One(1),
event_name:
"UNC_M_CAS_COUNT.RD_REG",
brief_description:
"DRAM RD_CAS and WR_CAS Commands.; All DRAM RD_CAS (w/ and w/out auto-pre)",
public_description:
Some("DRAM RD_CAS and WR_CAS Commands"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_P_VR_HOT_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(50),
umask:
Tuple::One(0),
event_name:
"UNC_P_VR_HOT_CYCLES",
brief_description:
"VR Hot",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_U_MSG_CHNL_SIZE_COUNT.4B",
IntelPerformanceCounterDescription{event_code:
Tuple::One(71),
umask:
Tuple::One(1),
event_name:
"UNC_U_MSG_CHNL_SIZE_COUNT.4B",
brief_description:
"MsgCh Requests by Size; 4B Requests",
public_description:
Some("Number of transactions on the message channel filtered by request size. This includes both reads and writes."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("UBOX"),
filter:
None,
extsel:
true,}),
("UNC_I_RxR_BL_NCB_CYCLES_FULL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(5),
umask:
Tuple::One(0),
event_name:
"UNC_I_RxR_BL_NCB_CYCLES_FULL",
brief_description:
"tbd",
public_description:
Some("Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_R2_IIO_CREDITS_REJECT.NCS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(52),
umask:
Tuple::One(32),
event_name:
"UNC_R2_IIO_CREDITS_REJECT.NCS",
brief_description:
"R2PCIe IIO Failed to Acquire a Credit; NCS",
public_description:
Some("Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly)."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_H_RING_BL_USED.CW_EVEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(64),
umask:
Tuple::One(1),
event_name:
"UNC_H_RING_BL_USED.CW_EVEN",
brief_description:
"HA BL Ring in Use; Clockwise and Even",
public_description:
Some("Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_R3_IIO_CREDITS_USED.DRS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(34),
umask:
Tuple::One(8),
event_name:
"UNC_R3_IIO_CREDITS_USED.DRS",
brief_description:
"to IIO BL Credit In Use",
public_description:
Some("Counts the number of cycles when the NCS/NCB/DRS credit is in use in the QPI for sending messages on BL to the IIO. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transfering data without coherency, and DRS is used for transfering data with coherency (cachable PCI transactions). This event can only track one message class at a time."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_M_ECC_CORRECTABLE_ERRORS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(9),
umask:
Tuple::One(0),
event_name:
"UNC_M_ECC_CORRECTABLE_ERRORS",
brief_description:
"ECC Correctable Errors",
public_description:
Some("Counts the number of ECC errors detected and corrected by the iMC on this channel. This counter is only useful with ECC DRAM devices. This count will increment one time for each correction regardless of the number of bits corrected. The iMC can correct up to 4 bit errors in independent channel mode and 8 bit erros in lockstep mode."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_H_RING_AK_USED.CW_ODD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(63),
umask:
Tuple::One(2),
event_name:
"UNC_H_RING_AK_USED.CW_ODD",
brief_description:
"HA AK Ring in Use; Clockwise and Odd",
public_description:
Some("Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_AK_CYCLES_NE.SCHED0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(49),
umask:
Tuple::One(1),
event_name:
"UNC_H_TxR_AK_CYCLES_NE.SCHED0",
brief_description:
"AK Egress Not Empty; Scheduler 0",
public_description:
Some("AK Egress Not Empty"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_CAS_COUNT.WR",
IntelPerformanceCounterDescription{event_code:
Tuple::One(4),
umask:
Tuple::One(12),
event_name:
"UNC_M_CAS_COUNT.WR",
brief_description:
"DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (both Modes)",
public_description:
Some("DRAM RD_CAS and WR_CAS Commands"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_H_IMC_WRITES.FULL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(26),
umask:
Tuple::One(1),
event_name:
"UNC_H_IMC_WRITES.FULL",
brief_description:
"HA to iMC Full Line Writes Issued; Full Line Non-ISOCH",
public_description:
Some("Counts the total number of full line writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_R2_RING_AD_USED.CW_ODD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(7),
umask:
Tuple::One(2),
event_name:
"UNC_R2_RING_AD_USED.CW_ODD",
brief_description:
"R2 AD Ring in Use; Clockwise and Odd",
public_description:
Some("Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_R2_TxR_CYCLES_FULL.BL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(37),
umask:
Tuple::One(4),
event_name:
"UNC_R2_TxR_CYCLES_FULL.BL",
brief_description:
"Egress Cycles Full; BL",
public_description:
Some("Counts the number of cycles when the R2PCIe Egress buffer is full."),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN2",
IntelPerformanceCounterDescription{event_code:
Tuple::One(24),
umask:
Tuple::One(4),
event_name:
"UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN2",
brief_description:
"HA iMC CHN0 WPQ Credits Empty - Regular; Channel 2",
public_description:
Some("Counts the number of cycles when there are no \'regular\' credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC\'s WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and \'special\' requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_I_TRANSACTIONS.WRITES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(21),
umask:
Tuple::One(2),
event_name:
"UNC_I_TRANSACTIONS.WRITES",
brief_description:
"Inbound Transaction Count; Writes",
public_description:
Some("Counts the number of \'Inbound\' transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_H_BYPASS_IMC.TAKEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(20),
umask:
Tuple::One(1),
event_name:
"UNC_H_BYPASS_IMC.TAKEN",
brief_description:
"HA to iMC Bypass; Taken",
public_description:
Some("Counts the number of times when the HA was able to bypass was attempted. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filted by when the bypass was taken and when it was not."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_R2_RING_AD_USED.CCW_ODD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(7),
umask:
Tuple::One(8),
event_name:
"UNC_R2_RING_AD_USED.CCW_ODD",
brief_description:
"R2 AD Ring in Use; Counterclockwise and Odd",
public_description:
Some("Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_C_ISMQ_DRD_MISS_OCC",
IntelPerformanceCounterDescription{event_code:
Tuple::One(33),
umask:
Tuple::One(0),
event_name:
"UNC_C_ISMQ_DRD_MISS_OCC",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_C_TOR_OCCUPANCY.EVICTION",
IntelPerformanceCounterDescription{event_code:
Tuple::One(54),
umask:
Tuple::One(4),
event_name:
"UNC_C_TOR_OCCUPANCY.EVICTION",
brief_description:
"TOR Occupancy; Evictions",
public_description:
Some("For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent \'filters\' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select \'MISS_OPC_MATCH\' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)"),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_M_PREEMPTION.RD_PREEMPT_RD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(8),
umask:
Tuple::One(1),
event_name:
"UNC_M_PREEMPTION.RD_PREEMPT_RD",
brief_description:
"Read Preemption Count; Read over Read Preemption",
public_description:
Some("Counts the number of times a read in the iMC preempts another read or write. Generally reads to an open page are issued ahead of requests to closed pages. This improves the page hit rate of the system. However, high priority requests can cause pages of active requests to be closed in order to get them out. This will reduce the latency of the high-priority request at the expense of lower bandwidth and increased overall average latency."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_R3_RxR_INSERTS.DRS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(17),
umask:
Tuple::One(8),
event_name:
"UNC_R3_RxR_INSERTS.DRS",
brief_description:
"Ingress Allocations; DRS",
public_description:
Some("Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_R2_RING_IV_USED.ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(10),
umask:
Tuple::One(15),
event_name:
"UNC_R2_RING_IV_USED.ANY",
brief_description:
"R2 IV Ring in Use; Any",
public_description:
Some("Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sunk into the ring stop. The IV ring is unidirectional. Whether UP or DN is used is dependent on the system programming. Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_H_TAD_REQUESTS_G0.REGION1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(27),
umask:
Tuple::One(2),
event_name:
"UNC_H_TAD_REQUESTS_G0.REGION1",
brief_description:
"HA Requests to a TAD Region - Group 0; TAD Region 1",
public_description:
Some("Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for \'Monroe\' systems that use the TAD to enable individual channels to enter self-refresh to save power."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_AK_OCCUPANCY.SCHED0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(48),
umask:
Tuple::One(1),
event_name:
"UNC_H_TxR_AK_OCCUPANCY.SCHED0",
brief_description:
"AK Egress Occupancy; Scheduler 0",
public_description:
Some("AK Egress Occupancy"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_POWER_CKE_CYCLES.RANK5",
IntelPerformanceCounterDescription{event_code:
Tuple::One(131),
umask:
Tuple::One(32),
event_name:
"UNC_M_POWER_CKE_CYCLES.RANK5",
brief_description:
"CKE_ON_CYCLES by Rank; DIMM ID",
public_description:
Some("Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary)."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxL_FLITS_G2.NCB_NONDATA",
IntelPerformanceCounterDescription{event_code:
Tuple::One(1),
umask:
Tuple::One(8),
event_name:
"UNC_Q_TxL_FLITS_G2.NCB_NONDATA",
brief_description:
"Flits Transferred - Group 2; Non-Coherent non-data Tx Flits",
public_description:
Some("Counts the number of flits trasmitted across the QPI Link. This is one of three \'groups\' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each \'flit\' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four \'fits\', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI \'speed\' (for example, 8.0 GT/s), the \'transfers\' here refer to \'fits\'. Therefore, in L0, the system will transfer 1 \'flit\' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as \'data\' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual \'data\' and an additional 16 bits of other information. To calculate \'data\' bandwidth, one should therefore do: data flits * 8B / time."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_M_MAJOR_MODES.READ",
IntelPerformanceCounterDescription{event_code:
Tuple::One(7),
umask:
Tuple::One(1),
event_name:
"UNC_M_MAJOR_MODES.READ",
brief_description:
"Cycles in a Major Mode; Read Major Mode",
public_description:
Some("Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxL_CRC_NO_CREDITS.ALMOST_FULL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(2),
umask:
Tuple::One(2),
event_name:
"UNC_Q_TxL_CRC_NO_CREDITS.ALMOST_FULL",
brief_description:
"Cycles Stalled with no LLR Credits; LLR is almost full",
public_description:
Some("Number of cycles when the Tx side ran out of Link Layer Retry credits, causing the Tx to stall."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_I_TICKLES.TOP_OF_QUEUE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(22),
umask:
Tuple::One(2),
event_name:
"UNC_I_TICKLES.TOP_OF_QUEUE",
brief_description:
"Tickle Count; Data Returned",
public_description:
Some("Counts the number of tickles that are received. This is for both explicit (from Cbo) and implicit (internal conflict) tickles."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_Q_DIRECT2CORE.FAILURE_RBT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(19),
umask:
Tuple::One(4),
event_name:
"UNC_Q_DIRECT2CORE.FAILURE_RBT",
brief_description:
"Direct 2 Core Spawning; Spawn Failure - RBT Not Set",
public_description:
Some("Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exlusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_C_RxR_EXT_STARVED.ISMQ_BIDS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(18),
umask:
Tuple::One(8),
event_name:
"UNC_C_RxR_EXT_STARVED.ISMQ_BIDS",
brief_description:
"Ingress Arbiter Blocking Cycles; ISMQ_BID",
public_description:
Some("Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxL_FLITS_G1.DRS_DATA",
IntelPerformanceCounterDescription{event_code:
Tuple::One(0),
umask:
Tuple::One(8),
event_name:
"UNC_Q_TxL_FLITS_G1.DRS_DATA",
brief_description:
"Flits Transferred - Group 1; DRS Data Flits",
public_description:
Some("Counts the number of flits trasmitted across the QPI Link. This is one of three \'groups\' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each \'flit\' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four \'fits\', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI \'speed\' (for example, 8.0 GT/s), the \'transfers\' here refer to \'fits\'. Therefore, in L0, the system will transfer 1 \'flit\' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as \'data\' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual \'data\' and an additional 16 bits of other information. To calculate \'data\' bandwidth, one should therefore do: data flits * 8B / time."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_U_U2C_EVENTS.UMC",
IntelPerformanceCounterDescription{event_code:
Tuple::One(67),
umask:
Tuple::One(32),
event_name:
"UNC_U_U2C_EVENTS.UMC",
brief_description:
"Monitor Sent to T0; Uncorrectable Machine Check",
public_description:
Some("Events coming from Uncore can be sent to one or all cores"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("UBOX"),
filter:
None,
extsel:
false,}),
("UNC_R3_RING_BL_USED.CCW_EVEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(9),
umask:
Tuple::One(4),
event_name:
"UNC_R3_RING_BL_USED.CCW_EVEN",
brief_description:
"R3 BL Ring in Use; Counterclockwise and Even",
public_description:
Some("Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop."),
counter:
Counter::Programmable(7),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_H_ADDR_OPC_MATCH.FILT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(32),
umask:
Tuple::One(3),
event_name:
"UNC_H_ADDR_OPC_MATCH.FILT",
brief_description:
"QPI Address/Opcode Match; Address & Opcode Match",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
Some("HA_AddrMatch0[31:6], HA_AddrMatch1[13:0], HA_OpcodeMatch[5:0]"),
extsel:
false,}),
("UNC_Q_L1_POWER_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(18),
umask:
Tuple::One(0),
event_name:
"UNC_Q_L1_POWER_CYCLES",
brief_description:
"Cycles in L1",
public_description:
Some("Number of QPI qfclk cycles spent in L1 power mode. L1 is a mode that totally shuts down a QPI link. Use edge detect to count the number of instances when the QPI link entered L1. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. Because L1 totally shuts down the link, it takes a good amount of time to exit this mode."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_U_MSG_CHNL_SIZE_COUNT.8B",
IntelPerformanceCounterDescription{event_code:
Tuple::One(71),
umask:
Tuple::One(2),
event_name:
"UNC_U_MSG_CHNL_SIZE_COUNT.8B",
brief_description:
"MsgCh Requests by Size; 8B Requests",
public_description:
Some("Number of transactions on the message channel filtered by request size. This includes both reads and writes."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("UBOX"),
filter:
None,
extsel:
true,}),
("UNC_H_TAD_REQUESTS_G1.REGION9",
IntelPerformanceCounterDescription{event_code:
Tuple::One(28),
umask:
Tuple::One(2),
event_name:
"UNC_H_TAD_REQUESTS_G1.REGION9",
brief_description:
"HA Requests to a TAD Region - Group 1; TAD Region 9",
public_description:
Some("Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 8 to 10. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for \'Monroe\' systems that use the TAD to enable individual channels to enter self-refresh to save power."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_TAD_REQUESTS_G0.REGION6",
IntelPerformanceCounterDescription{event_code:
Tuple::One(27),
umask:
Tuple::One(64),
event_name:
"UNC_H_TAD_REQUESTS_G0.REGION6",
brief_description:
"HA Requests to a TAD Region - Group 0; TAD Region 6",
public_description:
Some("Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for \'Monroe\' systems that use the TAD to enable individual channels to enter self-refresh to save power."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_R3_IIO_CREDITS_USED.NCS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(34),
umask:
Tuple::One(32),
event_name:
"UNC_R3_IIO_CREDITS_USED.NCS",
brief_description:
"to IIO BL Credit In Use",
public_description:
Some("Counts the number of cycles when the NCS/NCB/DRS credit is in use in the QPI for sending messages on BL to the IIO. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transfering data without coherency, and DRS is used for transfering data with coherency (cachable PCI transactions). This event can only track one message class at a time."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_OCCUPANCY_NCB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(22),
umask:
Tuple::One(0),
event_name:
"UNC_Q_RxL_OCCUPANCY_NCB",
brief_description:
"RxQ Occupancy - NCB",
public_description:
Some("Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCB flits only."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_C_RING_SINK_STARVED.BL_CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(6),
umask:
Tuple::One(4),
event_name:
"UNC_C_RING_SINK_STARVED.BL_CORE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_P_POWER_STATE_OCCUPANCY.CORES_C6",
IntelPerformanceCounterDescription{event_code:
Tuple::One(128),
umask:
Tuple::One(192),
event_name:
"UNC_P_POWER_STATE_OCCUPANCY.CORES_C6",
brief_description:
"Number of cores in C0",
public_description:
Some("This is an occupancy event that tracks the number of cores that are in C0. It can be used by itself to get the average number of cores in C0, with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_STALLS.BGF_SNP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(53),
umask:
Tuple::One(16),
event_name:
"UNC_Q_RxL_STALLS.BGF_SNP",
brief_description:
"Stalls Sending to R3QPI; BGF Stall - NCB",
public_description:
Some("Number of stalls trying to send to R3QPI."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_M_POWER_THROTTLE_CYCLES.RANK7",
IntelPerformanceCounterDescription{event_code:
Tuple::One(65),
umask:
Tuple::One(128),
event_name:
"UNC_M_POWER_THROTTLE_CYCLES.RANK7",
brief_description:
"Throttle Cycles for Rank 0; DIMM ID",
public_description:
Some("Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_C_RxR_OCCUPANCY.VFIFO",
IntelPerformanceCounterDescription{event_code:
Tuple::One(17),
umask:
Tuple::One(16),
event_name:
"UNC_C_RxR_OCCUPANCY.VFIFO",
brief_description:
"Ingress Occupancy; VFIFO",
public_description:
Some("Counts number of entries in the specified Ingress queue in each cycle."),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_I_CACHE_OWN_OCCUPANCY.SOURCE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(19),
umask:
Tuple::One(2),
event_name:
"UNC_I_CACHE_OWN_OCCUPANCY.SOURCE",
brief_description:
"Outstanding Write Ownership Occupancy; Select Source",
public_description:
Some("Accumulates the number of writes (and write prefetches) that are outstanding in the uncore trying to acquire ownership in each cycle. This can be used with the write transaction count to calculate the average write latency in the uncore. The occupancy increments when a write request is issued, and decrements when the data is returned."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_M_POWER_CKE_CYCLES.RANK3",
IntelPerformanceCounterDescription{event_code:
Tuple::One(131),
umask:
Tuple::One(8),
event_name:
"UNC_M_POWER_CKE_CYCLES.RANK3",
brief_description:
"CKE_ON_CYCLES by Rank; DIMM ID",
public_description:
Some("Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary)."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_P_VOLT_TRANS_CYCLES_DECREASE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(2),
umask:
Tuple::One(0),
event_name:
"UNC_P_VOLT_TRANS_CYCLES_DECREASE",
brief_description:
"Cycles Decreasing Voltage",
public_description:
Some("Counts the number of cycles when the system is decreasing voltage. There is no filtering supported with this event. One can use it as a simple event, or use it conjunction with the occupancy events to monitor the number of cores or threads that were impacted by the transition."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_C_RxR_OCCUPANCY.IRQ_REJECTED",
IntelPerformanceCounterDescription{event_code:
Tuple::One(17),
umask:
Tuple::One(2),
event_name:
"UNC_C_RxR_OCCUPANCY.IRQ_REJECTED",
brief_description:
"Ingress Occupancy; IRQ Rejected",
public_description:
Some("Counts number of entries in the specified Ingress queue in each cycle."),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_R2_IIO_CREDITS_REJECT.DRS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(52),
umask:
Tuple::One(8),
event_name:
"UNC_R2_IIO_CREDITS_REJECT.DRS",
brief_description:
"R2PCIe IIO Failed to Acquire a Credit; DRS",
public_description:
Some("Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly)."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_CREDITS_CONSUMED_VN0.NDR",
IntelPerformanceCounterDescription{event_code:
Tuple::One(30),
umask:
Tuple::One(32),
event_name:
"UNC_Q_RxL_CREDITS_CONSUMED_VN0.NDR",
brief_description:
"VN0 Credit Consumed; NDR",
public_description:
Some("Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_C_LLC_LOOKUP.WRITE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(52),
umask:
Tuple::One(5),
event_name:
"UNC_C_LLC_LOOKUP.WRITE",
brief_description:
"Cache Lookups; Write Requests",
public_description:
Some("Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set filter mask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
Some("CBoFilter[22:18]"),
extsel:
false,}),
("UNC_C_RING_AK_USED.DOWN_ODD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(28),
umask:
Tuple::One(8),
event_name:
"UNC_C_RING_AK_USED.DOWN_ODD",
brief_description:
"AK Ring In Use; Down and Odd",
public_description:
Some("Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the \'UP\' direction is on the clockwise ring and \'DN\' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring."),
counter:
Counter::Programmable(12),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_M_WPQ_CYCLES_FULL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(34),
umask:
Tuple::One(0),
event_name:
"UNC_M_WPQ_CYCLES_FULL",
brief_description:
"Write Pending Queue Full Cycles",
public_description:
Some("Counts the number of cycles when the Write Pending Queue is full. When the WPQ is full, the HA will not be able to issue any additional read requests into the iMC. This count should be similar count in the HA which tracks the number of cycles that the HA has no WPQ credits, just somewhat smaller to account for the credit return overhead."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_C_TOR_OCCUPANCY.ALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(54),
umask:
Tuple::One(8),
event_name:
"UNC_C_TOR_OCCUPANCY.ALL",
brief_description:
"TOR Occupancy; Any",
public_description:
Some("For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent \'filters\' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select \'MISS_OPC_MATCH\' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)"),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_M_WPQ_READ_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(35),
umask:
Tuple::One(0),
event_name:
"UNC_M_WPQ_READ_HIT",
brief_description:
"Write Pending Queue CAM Match",
public_description:
Some("Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_C_RxR_ISMQ_RETRY.RTID",
IntelPerformanceCounterDescription{event_code:
Tuple::One(51),
umask:
Tuple::One(8),
event_name:
"UNC_C_RxR_ISMQ_RETRY.RTID",
brief_description:
"ISMQ Retries; No RTIDs",
public_description:
Some("Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_M_RPQ_CYCLES_NE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(17),
umask:
Tuple::One(0),
event_name:
"UNC_M_RPQ_CYCLES_NE",
brief_description:
"Read Pending Queue Not Empty",
public_description:
Some("Counts the number of cycles that the Read Pending Queue is not empty. This can then be used to calculate the average occupancy (in conjunction with the Read Pending Queue Occupancy count). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This filter is to be used in conjunction with the occupancy filter so that one can correctly track the average occupancies for schedulable entries and scheduled requests."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_BL_CYCLES_NE.SCHED0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(53),
umask:
Tuple::One(1),
event_name:
"UNC_H_TxR_BL_CYCLES_NE.SCHED0",
brief_description:
"BL Egress Not Empty; Scheduler 0",
public_description:
Some("BL Egress Not Empty"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_P_CORE5_TRANSITION_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(8),
umask:
Tuple::One(0),
event_name:
"UNC_P_CORE5_TRANSITION_CYCLES",
brief_description:
"Core C State Transition Cycles",
public_description:
Some("Number of cycles spent performing core C state transitions. There is one event per core."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
true,}),
("UNC_M_POWER_THROTTLE_CYCLES.RANK5",
IntelPerformanceCounterDescription{event_code:
Tuple::One(65),
umask:
Tuple::One(32),
event_name:
"UNC_M_POWER_THROTTLE_CYCLES.RANK5",
brief_description:
"Throttle Cycles for Rank 0; DIMM ID",
public_description:
Some("Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_U_FILTER_MATCH.U2C_ENABLE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(65),
umask:
Tuple::One(4),
event_name:
"UNC_U_FILTER_MATCH.U2C_ENABLE",
brief_description:
"Filter Match",
public_description:
Some("Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("UBOX"),
filter:
Some("UBoxFilter[3:0]"),
extsel:
false,}),
("UNC_C_RING_AK_USED.DOWN_EVEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(28),
umask:
Tuple::One(4),
event_name:
"UNC_C_RING_AK_USED.DOWN_EVEN",
brief_description:
"AK Ring In Use; Down and Even",
public_description:
Some("Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the \'UP\' direction is on the clockwise ring and \'DN\' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring."),
counter:
Counter::Programmable(12),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_P_FREQ_MAX_OS_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(6),
umask:
Tuple::One(0),
event_name:
"UNC_P_FREQ_MAX_OS_CYCLES",
brief_description:
"OS Strongest Upper Limit Cycles",
public_description:
Some("Counts the number of cycles when the OS is the upper limit on frequency."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(34),
umask:
Tuple::One(2),
event_name:
"UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI1",
brief_description:
"Cycles without QPI Ingress Credits; AD to QPI Link 1",
public_description:
Some("Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent. This can be filtered by the different credit pools and the different links."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_R3_IIO_CREDITS_ACQUIRED.NCS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(32),
umask:
Tuple::One(32),
event_name:
"UNC_R3_IIO_CREDITS_ACQUIRED.NCS",
brief_description:
"to IIO BL Credit Acquired",
public_description:
Some("Counts the number of times the NCS/NCB/DRS credit is acquried in the QPI for sending messages on BL to the IIO. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transfering data without coherency, and DRS is used for transfering data with coherency (cachable PCI transactions). This event can only track one message class at a time."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_M_POWER_CHANNEL_PPD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(133),
umask:
Tuple::One(0),
event_name:
"UNC_M_POWER_CHANNEL_PPD",
brief_description:
"Channel PPD Cycles",
public_description:
Some("Number of cycles when all the ranks in the channel are in PPD mode. If IBT=off is enabled, then this can be used to count those cycles. If it is not enabled, then this can count the number of cycles when that could have been taken advantage of."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_POWER_CKE_CYCLES.RANK7",
IntelPerformanceCounterDescription{event_code:
Tuple::One(131),
umask:
Tuple::One(128),
event_name:
"UNC_M_POWER_CKE_CYCLES.RANK7",
brief_description:
"CKE_ON_CYCLES by Rank; DIMM ID",
public_description:
Some("Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary)."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_P_MEMORY_PHASE_SHEDDING_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(47),
umask:
Tuple::One(0),
event_name:
"UNC_P_MEMORY_PHASE_SHEDDING_CYCLES",
brief_description:
"Memory Phase Shedding Cycles",
public_description:
Some("Counts the number of cycles that the PCU has triggered memory phase shedding. This is a mode that can be run in the iMC physicals that saves power at the expense of additional latency."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_INSERTS_NCB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(10),
umask:
Tuple::One(0),
event_name:
"UNC_Q_RxL_INSERTS_NCB",
brief_description:
"Rx Flit Buffer Allocations - NCB",
public_description:
Some("Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCB flits."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_R2_RxR_CYCLES_NE.NCS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(16),
umask:
Tuple::One(32),
event_name:
"UNC_R2_RxR_CYCLES_NE.NCS",
brief_description:
"Ingress Cycles Not Empty; NCS",
public_description:
Some("Counts the number of cycles when the R2PCIe Ingress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_CREDITS_CONSUMED_VN0.SNP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(30),
umask:
Tuple::One(16),
event_name:
"UNC_Q_RxL_CREDITS_CONSUMED_VN0.SNP",
brief_description:
"VN0 Credit Consumed; SNP",
public_description:
Some("Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_M_PRE_COUNT.PAGE_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(2),
umask:
Tuple::One(1),
event_name:
"UNC_M_PRE_COUNT.PAGE_MISS",
brief_description:
"DRAM Precharge commands.; Precharges due to page miss",
public_description:
Some("Counts the number of DRAM Precharge commands sent on this channel."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_P_DEMOTIONS_CORE2",
IntelPerformanceCounterDescription{event_code:
Tuple::One(32),
umask:
Tuple::One(0),
event_name:
"UNC_P_DEMOTIONS_CORE2",
brief_description:
"Core C State Demotions",
public_description:
Some("Counts the number of times when a configurable cores had a C-state demotion"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_U_U2C_EVENTS.OTHER",
IntelPerformanceCounterDescription{event_code:
Tuple::One(67),
umask:
Tuple::One(128),
event_name:
"UNC_U_U2C_EVENTS.OTHER",
brief_description:
"Monitor Sent to T0; Other",
public_description:
Some("Events coming from Uncore can be sent to one or all cores"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("UBOX"),
filter:
None,
extsel:
false,}),
("UNC_R3_RxR_OCCUPANCY.NCB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(19),
umask:
Tuple::One(16),
event_name:
"UNC_R3_RxR_OCCUPANCY.NCB",
brief_description:
"Ingress Occupancy Accumulator; NCB",
public_description:
Some("Accumulates the occupancy of a given QPI Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency."),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_R2_TxR_NACKS.AD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(38),
umask:
Tuple::One(1),
event_name:
"UNC_R2_TxR_NACKS.AD",
brief_description:
"Egress NACK; AD",
public_description:
Some("Counts the number of times that the Egress received a NACK from the ring and could not issue a transaction."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_U_U2C_EVENTS.TRAP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(67),
umask:
Tuple::One(64),
event_name:
"UNC_U_U2C_EVENTS.TRAP",
brief_description:
"Monitor Sent to T0; Trap",
public_description:
Some("Events coming from Uncore can be sent to one or all cores"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("UBOX"),
filter:
None,
extsel:
false,}),
("UNC_R2_CLOCKTICKS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(1),
umask:
Tuple::One(0),
event_name:
"UNC_R2_CLOCKTICKS",
brief_description:
"Number of uclks in domain",
public_description:
Some("Counts the number of uclks in the R2PCIe uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the R2PCIe is close to the Ubox, they generally should not diverge by more than a handful of cycles."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_R2_RING_BL_USED.CW_ODD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(9),
umask:
Tuple::One(2),
event_name:
"UNC_R2_RING_BL_USED.CW_ODD",
brief_description:
"R2 BL Ring in Use; Clockwise and Odd",
public_description:
Some("Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_H_RING_AK_USED.CCW_ODD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(63),
umask:
Tuple::One(8),
event_name:
"UNC_H_RING_AK_USED.CCW_ODD",
brief_description:
"HA AK Ring in Use; Counterclockwise and Odd",
public_description:
Some("Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_POWER_THROTTLE_CYCLES.RANK6",
IntelPerformanceCounterDescription{event_code:
Tuple::One(65),
umask:
Tuple::One(64),
event_name:
"UNC_M_POWER_THROTTLE_CYCLES.RANK6",
brief_description:
"Throttle Cycles for Rank 0; DIMM ID",
public_description:
Some("Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_I_TxR_DATA_INSERTS_NCB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(14),
umask:
Tuple::One(0),
event_name:
"UNC_I_TxR_DATA_INSERTS_NCB",
brief_description:
"Outbound Read Requests",
public_description:
Some("Counts the number of requests issued to the switch (towards the devices)."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_Q_DIRECT2CORE.SUCCESS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(19),
umask:
Tuple::One(1),
event_name:
"UNC_Q_DIRECT2CORE.SUCCESS",
brief_description:
"Direct 2 Core Spawning; Spawn Success",
public_description:
Some("Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exlusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_C_TOR_OCCUPANCY.NID_OPCODE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(54),
umask:
Tuple::One(65),
event_name:
"UNC_C_TOR_OCCUPANCY.NID_OPCODE",
brief_description:
"TOR Occupancy; NID and Opcode Matched",
public_description:
Some("For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent \'filters\' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select \'MISS_OPC_MATCH\' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)"),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
Some("CBoFilter[31:23], CBoFilter[17:10]"),
extsel:
false,}),
("UNC_P_DEMOTIONS_CORE1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(31),
umask:
Tuple::One(0),
event_name:
"UNC_P_DEMOTIONS_CORE1",
brief_description:
"Core C State Demotions",
public_description:
Some("Counts the number of times when a configurable cores had a C-state demotion"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
Some("PCUFilter[7:0]"),
extsel:
false,}),
("UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN2",
IntelPerformanceCounterDescription{event_code:
Tuple::One(22),
umask:
Tuple::One(4),
event_name:
"UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN2",
brief_description:
"iMC RPQ Credits Empty - Special; Channel 2",
public_description:
Some("Counts the number of cycles when there are no \'special\' credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC\'s RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and \'special\' requests such as ISOCH reads. This count only tracks the \'special\' credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_OCCUPANCY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(11),
umask:
Tuple::One(0),
event_name:
"UNC_Q_RxL_OCCUPANCY",
brief_description:
"RxQ Occupancy - All Packets",
public_description:
Some("Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_CREDITS_CONSUMED_VNA",
IntelPerformanceCounterDescription{event_code:
Tuple::One(29),
umask:
Tuple::One(0),
event_name:
"UNC_Q_RxL_CREDITS_CONSUMED_VNA",
brief_description:
"VNA Credit Consumed",
public_description:
Some("Counts the number of times that an RxQ VNA credit was consumed (i.e. message uses a VNA credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_H_TxR_BL.DRS_QPI",
IntelPerformanceCounterDescription{event_code:
Tuple::One(16),
umask:
Tuple::One(4),
event_name:
"UNC_H_TxR_BL.DRS_QPI",
brief_description:
"Outbound DRS Ring Transactions to Cache; Data to QPI",
public_description:
Some("Counts the number of DRS messages sent out on the BL ring. This can be filtered by the destination."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_R2_RING_BL_USED.CW_EVEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(9),
umask:
Tuple::One(1),
event_name:
"UNC_R2_RING_BL_USED.CW_EVEN",
brief_description:
"R2 BL Ring in Use; Clockwise and Even",
public_description:
Some("Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_R3_VN0_CREDITS_REJECT.NCS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(55),
umask:
Tuple::One(32),
event_name:
"UNC_R3_VN0_CREDITS_REJECT.NCS",
brief_description:
"VN0 Credit Acquisition Failed on DRS; NCS Message Class",
public_description:
Some("Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_P_VOLT_TRANS_CYCLES_CHANGE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(3),
umask:
Tuple::One(0),
event_name:
"UNC_P_VOLT_TRANS_CYCLES_CHANGE",
brief_description:
"Cycles Changing Voltage",
public_description:
Some("Counts the number of cycles when the system is changing voltage. There is no filtering supported with this event. One can use it as a simple event, or use it conjunction with the occupancy events to monitor the number of cores or threads that were impacted by the transition. This event is calculated by or\'ing together the increasing and decreasing events."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_H_IMC_WRITES.ALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(26),
umask:
Tuple::One(15),
event_name:
"UNC_H_IMC_WRITES.ALL",
brief_description:
"HA to iMC Full Line Writes Issued; All Writes",
public_description:
Some("Counts the total number of full line writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_U_U2C_EVENTS.LIVELOCK",
IntelPerformanceCounterDescription{event_code:
Tuple::One(67),
umask:
Tuple::One(4),
event_name:
"UNC_U_U2C_EVENTS.LIVELOCK",
brief_description:
"Monitor Sent to T0; Livelock",
public_description:
Some("Events coming from Uncore can be sent to one or all cores"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("UBOX"),
filter:
None,
extsel:
false,}),
("UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN3",
IntelPerformanceCounterDescription{event_code:
Tuple::One(22),
umask:
Tuple::One(8),
event_name:
"UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN3",
brief_description:
"iMC RPQ Credits Empty - Special; Channel 3",
public_description:
Some("Counts the number of cycles when there are no \'special\' credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC\'s RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and \'special\' requests such as ISOCH reads. This count only tracks the \'special\' credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_R3_RxR_OCCUPANCY.NDR",
IntelPerformanceCounterDescription{event_code:
Tuple::One(19),
umask:
Tuple::One(4),
event_name:
"UNC_R3_RxR_OCCUPANCY.NDR",
brief_description:
"Ingress Occupancy Accumulator; NDR",
public_description:
Some("Accumulates the occupancy of a given QPI Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency."),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_CYCLES_NE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(10),
umask:
Tuple::One(0),
event_name:
"UNC_Q_RxL_CYCLES_NE",
brief_description:
"RxQ Cycles Not Empty",
public_description:
Some("Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_I_RxR_BL_NCB_INSERTS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(2),
umask:
Tuple::One(0),
event_name:
"UNC_I_RxR_BL_NCB_INSERTS",
brief_description:
"BL Ingress Occupancy - NCB",
public_description:
Some("Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_R3_RING_AD_USED.CCW_ODD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(7),
umask:
Tuple::One(8),
event_name:
"UNC_R3_RING_AD_USED.CCW_ODD",
brief_description:
"R3 AD Ring in Use; Counterclockwise and Odd",
public_description:
Some("Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop."),
counter:
Counter::Programmable(7),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_AK_CYCLES_FULL.SCHED0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(50),
umask:
Tuple::One(1),
event_name:
"UNC_H_TxR_AK_CYCLES_FULL.SCHED0",
brief_description:
"AK Egress Full; Scheduler 0",
public_description:
Some("AK Egress Full"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_I_TxR_DATA_INSERTS_NCS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(15),
umask:
Tuple::One(0),
event_name:
"UNC_I_TxR_DATA_INSERTS_NCS",
brief_description:
"Outbound Read Requests",
public_description:
Some("Counts the number of requests issued to the switch (towards the devices)."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_U_U2C_EVENTS.LTERROR",
IntelPerformanceCounterDescription{event_code:
Tuple::One(67),
umask:
Tuple::One(8),
event_name:
"UNC_U_U2C_EVENTS.LTERROR",
brief_description:
"Monitor Sent to T0; LTError",
public_description:
Some("Events coming from Uncore can be sent to one or all cores"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("UBOX"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxL_OCCUPANCY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(7),
umask:
Tuple::One(0),
event_name:
"UNC_Q_TxL_OCCUPANCY",
brief_description:
"Tx Flit Buffer Occupancy",
public_description:
Some("Accumulates the number of flits in the TxQ. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This can be used with the cycles not empty event to track average occupancy, or the allocations event to track average lifetime in the TxQ."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_I_CLOCKTICKS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(0),
umask:
Tuple::One(0),
event_name:
"UNC_I_CLOCKTICKS",
brief_description:
"Clocks in the IRP",
public_description:
Some("Number of clocks in the IRP."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_M_DRAM_REFRESH.PANIC",
IntelPerformanceCounterDescription{event_code:
Tuple::One(5),
umask:
Tuple::One(2),
event_name:
"UNC_M_DRAM_REFRESH.PANIC",
brief_description:
"Number of DRAM Refreshes Issued",
public_description:
Some("Counts the number of refreshes issued."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_P_CLOCKTICKS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(0),
umask:
Tuple::One(0),
event_name:
"UNC_P_CLOCKTICKS",
brief_description:
"pclk Cycles",
public_description:
Some("The PCU runs off a fixed 800 MHz clock. This event counts the number of pclk cycles measured while the counter was enabled. The pclk, like the Memory Controller\'s dclk, counts at a constant rate making it a good measure of actual wall time."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_P_FREQ_BAND3_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(14),
umask:
Tuple::One(0),
event_name:
"UNC_P_FREQ_BAND3_CYCLES",
brief_description:
"Frequency Residency",
public_description:
Some("Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter. One can use all four counters with this event, so it is possible to track up to 4 configurable bands. One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
Some("PCUFilter[31:24]"),
extsel:
false,}),
("UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(4),
umask:
Tuple::One(0),
event_name:
"UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES",
brief_description:
"Thermal Strongest Upper Limit Cycles",
public_description:
Some("Counts the number of cycles when thermal conditions are the upper limit on frequency. This is related to the THERMAL_THROTTLE CYCLES_ABOVE_TEMP event, which always counts cycles when we are above the thermal temperature. This event (STRONGEST_UPPER_LIMIT) is sampled at the output of the algorithm that determines the actual frequency, while THERMAL_THROTTLE looks at the input."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_AD_CYCLES_NE.SCHED1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(41),
umask:
Tuple::One(2),
event_name:
"UNC_H_TxR_AD_CYCLES_NE.SCHED1",
brief_description:
"AD Egress Not Empty; Scheduler 1",
public_description:
Some("AD Egress Not Empty"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_R2_IIO_CREDITS_USED.NCS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(50),
umask:
Tuple::One(32),
event_name:
"UNC_R2_IIO_CREDITS_USED.NCS",
brief_description:
"R2PCIe IIO Credits in Use; NCS",
public_description:
Some("Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly)."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_Q_CLOCKTICKS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(20),
umask:
Tuple::One(0),
event_name:
"UNC_Q_CLOCKTICKS",
brief_description:
"Number of qfclks",
public_description:
Some("Counts the number of clocks in the QPI LL. This clock runs at 1/8th the \'GT/s\' speed of the QPI link. For example, a 8GT/s link will have qfclk or 1GHz. JKT does not support dynamic link speeds, so this frequency is fixed."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_C_TOR_OCCUPANCY.NID_MISS_OPCODE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(54),
umask:
Tuple::One(67),
event_name:
"UNC_C_TOR_OCCUPANCY.NID_MISS_OPCODE",
brief_description:
"TOR Occupancy; NID and Opcode Matched Miss",
public_description:
Some("For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent \'filters\' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select \'MISS_OPC_MATCH\' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)"),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
Some("CBoFilter[31:23], CBoFilter[17:10]"),
extsel:
false,}),
("UNC_C_RING_AD_USED.UP_EVEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(27),
umask:
Tuple::One(1),
event_name:
"UNC_C_RING_AD_USED.UP_EVEN",
brief_description:
"AD Ring In Use; Up and Even",
public_description:
Some("Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the \'UP\' direction is on the clockwise ring and \'DN\' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring."),
counter:
Counter::Programmable(12),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_R3_RING_AK_USED.CW_ODD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(8),
umask:
Tuple::One(2),
event_name:
"UNC_R3_RING_AK_USED.CW_ODD",
brief_description:
"R3 AK Ring in Use; Clockwise and Odd",
public_description:
Some("Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop."),
counter:
Counter::Programmable(7),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_H_DIRECTORY_UPDATE.SET",
IntelPerformanceCounterDescription{event_code:
Tuple::One(13),
umask:
Tuple::One(1),
event_name:
"UNC_H_DIRECTORY_UPDATE.SET",
brief_description:
"Directory Updates; Directory Set",
public_description:
Some("Counts the number of directory updates that were required. These result in writes to the memory controller. This can be filtered by directory sets and directory clears."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_Q_VNA_CREDIT_RETURNS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(28),
umask:
Tuple::One(0),
event_name:
"UNC_Q_VNA_CREDIT_RETURNS",
brief_description:
"VNA Credits Returned",
public_description:
Some("Number of VNA credits returned."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_C_RING_AK_USED.UP_ODD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(28),
umask:
Tuple::One(2),
event_name:
"UNC_C_RING_AK_USED.UP_ODD",
brief_description:
"AK Ring In Use; Up and Odd",
public_description:
Some("Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the \'UP\' direction is on the clockwise ring and \'DN\' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring."),
counter:
Counter::Programmable(12),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_AD_CYCLES_FULL.SCHED0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(42),
umask:
Tuple::One(1),
event_name:
"UNC_H_TxR_AD_CYCLES_FULL.SCHED0",
brief_description:
"AD Egress Full; Scheduler 0",
public_description:
Some("AD Egress Full"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_R2_IIO_CREDITS_USED.DRS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(50),
umask:
Tuple::One(8),
event_name:
"UNC_R2_IIO_CREDITS_USED.DRS",
brief_description:
"R2PCIe IIO Credits in Use; DRS",
public_description:
Some("Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly)."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_M_POWER_CKE_CYCLES.RANK1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(131),
umask:
Tuple::One(2),
event_name:
"UNC_M_POWER_CKE_CYCLES.RANK1",
brief_description:
"CKE_ON_CYCLES by Rank; DIMM ID",
public_description:
Some("Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary)."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_H_DIRECT2CORE_CYCLES_DISABLED",
IntelPerformanceCounterDescription{event_code:
Tuple::One(18),
umask:
Tuple::One(0),
event_name:
"UNC_H_DIRECT2CORE_CYCLES_DISABLED",
brief_description:
"Cycles when Direct2Core was Disabled",
public_description:
Some("Number of cycles in which Direct2Core was disabled"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_RPQ_OCCUPANCY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(128),
umask:
Tuple::One(0),
event_name:
"UNC_M_RPQ_OCCUPANCY",
brief_description:
"Read Pending Queue Occupancy",
public_description:
Some("Accumulates the occupancies of the Read Pending Queue each cycle. This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_C_TOR_INSERTS.EVICTION",
IntelPerformanceCounterDescription{event_code:
Tuple::One(53),
umask:
Tuple::One(4),
event_name:
"UNC_C_TOR_INSERTS.EVICTION",
brief_description:
"TOR Inserts; Evictions",
public_description:
Some("Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent \'filters\' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select \'MISS_OPC_MATCH\' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_M_POWER_THROTTLE_CYCLES.RANK3",
IntelPerformanceCounterDescription{event_code:
Tuple::One(65),
umask:
Tuple::One(8),
event_name:
"UNC_M_POWER_THROTTLE_CYCLES.RANK3",
brief_description:
"Throttle Cycles for Rank 0; DIMM ID",
public_description:
Some("Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_POWER_THROTTLE_CYCLES.RANK4",
IntelPerformanceCounterDescription{event_code:
Tuple::One(65),
umask:
Tuple::One(16),
event_name:
"UNC_M_POWER_THROTTLE_CYCLES.RANK4",
brief_description:
"Throttle Cycles for Rank 0; DIMM ID",
public_description:
Some("Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_U_EVENT_MSG.DOORBELL_RCVD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(66),
umask:
Tuple::One(8),
event_name:
"UNC_U_EVENT_MSG.DOORBELL_RCVD",
brief_description:
"VLW Received",
public_description:
Some("Virtual Logical Wire (legacy) message were received from Uncore. Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("UBOX"),
filter:
None,
extsel:
false,}),
("UNC_R3_VNA_CREDITS_REJECT.NDR",
IntelPerformanceCounterDescription{event_code:
Tuple::One(52),
umask:
Tuple::One(4),
event_name:
"UNC_R3_VNA_CREDITS_REJECT.NDR",
brief_description:
"VNA Credit Reject; NDR Message Class",
public_description:
Some("Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_P_POWER_STATE_OCCUPANCY.CORES_C0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(128),
umask:
Tuple::One(64),
event_name:
"UNC_P_POWER_STATE_OCCUPANCY.CORES_C0",
brief_description:
"Number of cores in C0",
public_description:
Some("This is an occupancy event that tracks the number of cores that are in C0. It can be used by itself to get the average number of cores in C0, with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_C_RING_AD_USED.DOWN_ODD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(27),
umask:
Tuple::One(8),
event_name:
"UNC_C_RING_AD_USED.DOWN_ODD",
brief_description:
"AD Ring In Use; Down and Odd",
public_description:
Some("Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the \'UP\' direction is on the clockwise ring and \'DN\' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring."),
counter:
Counter::Programmable(12),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(34),
umask:
Tuple::One(1),
event_name:
"UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI0",
brief_description:
"Cycles without QPI Ingress Credits; AD to QPI Link 0",
public_description:
Some("Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent. This can be filtered by the different credit pools and the different links."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_C_RxR_ISMQ_RETRY.ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(51),
umask:
Tuple::One(1),
event_name:
"UNC_C_RxR_ISMQ_RETRY.ANY",
brief_description:
"ISMQ Retries; Any Reject",
public_description:
Some("Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_R2_RING_AK_USED.CW_EVEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(8),
umask:
Tuple::One(1),
event_name:
"UNC_R2_RING_AK_USED.CW_EVEN",
brief_description:
"R2 AK Ring in Use; Clockwise and Even",
public_description:
Some("Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_C_RxR_INSERTS.VFIFO",
IntelPerformanceCounterDescription{event_code:
Tuple::One(19),
umask:
Tuple::One(16),
event_name:
"UNC_C_RxR_INSERTS.VFIFO",
brief_description:
"Ingress Allocations; VFIFO",
public_description:
Some("Counts number of allocations per cycle into the specified Ingress queue."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_C_TOR_INSERTS.NID_MISS_OPCODE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(53),
umask:
Tuple::One(67),
event_name:
"UNC_C_TOR_INSERTS.NID_MISS_OPCODE",
brief_description:
"TOR Inserts; NID and Opcode Matched Miss",
public_description:
Some("Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent \'filters\' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select \'MISS_OPC_MATCH\' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
Some("CBoFilter[31:23], CBoFilter[17:10]"),
extsel:
false,}),
("UNC_C_RxR_OCCUPANCY.IPQ",
IntelPerformanceCounterDescription{event_code:
Tuple::One(17),
umask:
Tuple::One(4),
event_name:
"UNC_C_RxR_OCCUPANCY.IPQ",
brief_description:
"Ingress Occupancy; IPQ",
public_description:
Some("Counts number of entries in the specified Ingress queue in each cycle."),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_U_U2C_EVENTS.MONITOR_T0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(67),
umask:
Tuple::One(1),
event_name:
"UNC_U_U2C_EVENTS.MONITOR_T0",
brief_description:
"Monitor Sent to T0; Monitor T0",
public_description:
Some("Events coming from Uncore can be sent to one or all cores"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("UBOX"),
filter:
None,
extsel:
false,}),
("UNC_U_CLOCKTICKS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(0),
umask:
Tuple::One(0),
event_name:
"UNC_U_CLOCKTICKS",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("UBOX"),
filter:
None,
extsel:
false,}),
("UNC_P_FREQ_BAND2_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(13),
umask:
Tuple::One(0),
event_name:
"UNC_P_FREQ_BAND2_CYCLES",
brief_description:
"Frequency Residency",
public_description:
Some("Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter. One can use all four counters with this event, so it is possible to track up to 4 configurable bands. One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
Some("PCUFilter[23:16]"),
extsel:
false,}),
("UNC_C_LLC_LOOKUP.DATA_READ",
IntelPerformanceCounterDescription{event_code:
Tuple::One(52),
umask:
Tuple::One(3),
event_name:
"UNC_C_LLC_LOOKUP.DATA_READ",
brief_description:
"Cache Lookups; Data Read Request",
public_description:
Some("Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set filter mask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
Some("CBoFilter[22:18]"),
extsel:
false,}),
("UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(22),
umask:
Tuple::One(1),
event_name:
"UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN0",
brief_description:
"iMC RPQ Credits Empty - Special; Channel 0",
public_description:
Some("Counts the number of cycles when there are no \'special\' credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC\'s RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and \'special\' requests such as ISOCH reads. This count only tracks the \'special\' credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_C_TxR_STARVED.AK",
IntelPerformanceCounterDescription{event_code:
Tuple::One(3),
umask:
Tuple::One(2),
event_name:
"UNC_C_TxR_STARVED.AK",
brief_description:
"Injection Starvation; Onto AK Ring",
public_description:
Some("Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_C_MISC.WC_ALIASING",
IntelPerformanceCounterDescription{event_code:
Tuple::One(57),
umask:
Tuple::One(2),
event_name:
"UNC_C_MISC.WC_ALIASING",
brief_description:
"Cbo Misc; Write Combining Aliasing",
public_description:
Some("Miscellaneous events in the Cbo."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_AK_CYCLES_NE.ALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(49),
umask:
Tuple::One(3),
event_name:
"UNC_H_TxR_AK_CYCLES_NE.ALL",
brief_description:
"AK Egress Not Empty; All",
public_description:
Some("AK Egress Not Empty"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_P_DEMOTIONS_CORE7",
IntelPerformanceCounterDescription{event_code:
Tuple::One(37),
umask:
Tuple::One(0),
event_name:
"UNC_P_DEMOTIONS_CORE7",
brief_description:
"Core C State Demotions",
public_description:
Some("Counts the number of times when a configurable cores had a C-state demotion"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
Some("PCUFilter[7:0]"),
extsel:
false,}),
("UNC_H_DIRECT2CORE_COUNT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(17),
umask:
Tuple::One(0),
event_name:
"UNC_H_DIRECT2CORE_COUNT",
brief_description:
"Direct2Core Messages Sent",
public_description:
Some("Number of Direct2Core messages sent"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_CONFLICT_CYCLES.NO_CONFLICT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(11),
umask:
Tuple::One(1),
event_name:
"UNC_H_CONFLICT_CYCLES.NO_CONFLICT",
brief_description:
"Conflict Checks; No Conflict",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_I_RxR_BL_NCS_INSERTS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(3),
umask:
Tuple::One(0),
event_name:
"UNC_I_RxR_BL_NCS_INSERTS",
brief_description:
"BL Ingress Occupancy - NCS",
public_description:
Some("Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_P_DEMOTIONS_CORE5",
IntelPerformanceCounterDescription{event_code:
Tuple::One(35),
umask:
Tuple::One(0),
event_name:
"UNC_P_DEMOTIONS_CORE5",
brief_description:
"Core C State Demotions",
public_description:
Some("Counts the number of times when a configurable cores had a C-state demotion"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
Some("PCUFilter[7:0]"),
extsel:
false,}),
("UNC_Q_RxL_INSERTS_DRS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(9),
umask:
Tuple::One(0),
event_name:
"UNC_Q_RxL_INSERTS_DRS",
brief_description:
"Rx Flit Buffer Allocations - DRS",
public_description:
Some("Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only DRS flits."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_H_DIRECTORY_UPDATE.CLEAR",
IntelPerformanceCounterDescription{event_code:
Tuple::One(13),
umask:
Tuple::One(2),
event_name:
"UNC_H_DIRECTORY_UPDATE.CLEAR",
brief_description:
"Directory Updates; Directory Clear",
public_description:
Some("Counts the number of directory updates that were required. These result in writes to the memory controller. This can be filtered by directory sets and directory clears."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_R2_IIO_CREDITS_ACQUIRED.NCB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(51),
umask:
Tuple::One(16),
event_name:
"UNC_R2_IIO_CREDITS_ACQUIRED.NCB",
brief_description:
"R2PCIe IIO Credit Acquired; NCB",
public_description:
Some("Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly)."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_C_LLC_VICTIMS.NID",
IntelPerformanceCounterDescription{event_code:
Tuple::One(55),
umask:
Tuple::One(64),
event_name:
"UNC_C_LLC_VICTIMS.NID",
brief_description:
"Lines Victimized; Victimized Lines that Match NID",
public_description:
Some("Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
Some("CBoFilter[17:10]"),
extsel:
false,}),
("UNC_R3_CLOCKTICKS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(1),
umask:
Tuple::One(0),
event_name:
"UNC_R3_CLOCKTICKS",
brief_description:
"Number of uclks in domain",
public_description:
Some("Counts the number of uclks in the QPI uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the QPI Agent is close to the Ubox, they generally should not diverge by more than a handful of cycles."),
counter:
Counter::Programmable(7),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_C_RxR_EXT_STARVED.IRQ",
IntelPerformanceCounterDescription{event_code:
Tuple::One(18),
umask:
Tuple::One(1),
event_name:
"UNC_C_RxR_EXT_STARVED.IRQ",
brief_description:
"Ingress Arbiter Blocking Cycles; IPQ",
public_description:
Some("Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_R3_RING_AD_USED.CW_ODD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(7),
umask:
Tuple::One(2),
event_name:
"UNC_R3_RING_AD_USED.CW_ODD",
brief_description:
"R3 AD Ring in Use; Clockwise and Odd",
public_description:
Some("Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop."),
counter:
Counter::Programmable(7),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_FLITS_G2.NDR_AK",
IntelPerformanceCounterDescription{event_code:
Tuple::One(3),
umask:
Tuple::One(2),
event_name:
"UNC_Q_RxL_FLITS_G2.NDR_AK",
brief_description:
"Flits Received - Group 2; Non-Data Response Rx Flits - AK",
public_description:
Some("Counts the number of flits received from the QPI Link. This is one of three \'groups\' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each \'flit\' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four \'fits\', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI \'speed\' (for example, 8.0 GT/s), the \'transfers\' here refer to \'fits\'. Therefore, in L0, the system will transfer 1 \'flit\' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as \'data\' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual \'data\' and an additional 16 bits of other information. To calculate \'data\' bandwidth, one should therefore do: data flits * 8B / time."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_M_POWER_SELF_REFRESH",
IntelPerformanceCounterDescription{event_code:
Tuple::One(67),
umask:
Tuple::One(0),
event_name:
"UNC_M_POWER_SELF_REFRESH",
brief_description:
"Clock-Enabled Self-Refresh",
public_description:
Some("Counts the number of cycles when the iMC is in self-refresh and the iMC still has a clock. This happens in some package C-states. For example, the PCU may ask the iMC to enter self-refresh even though some of the cores are still processing. One use of this is for Monroe technology. Self-refresh is required during package C3 and C6, but there is no clock in the iMC at this time, so it is not possible to count these cases."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_RPQ_INSERTS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(16),
umask:
Tuple::One(0),
event_name:
"UNC_M_RPQ_INSERTS",
brief_description:
"Read Pending Queue Allocations",
public_description:
Some("Counts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_CAS_COUNT.WR_WMM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(4),
umask:
Tuple::One(4),
event_name:
"UNC_M_CAS_COUNT.WR_WMM",
brief_description:
"DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode",
public_description:
Some("DRAM RD_CAS and WR_CAS Commands"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_R3_RxR_CYCLES_NE.NCS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(16),
umask:
Tuple::One(32),
event_name:
"UNC_R3_RxR_CYCLES_NE.NCS",
brief_description:
"Ingress Cycles Not Empty; NCS",
public_description:
Some("Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_M_MAJOR_MODES.WRITE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(7),
umask:
Tuple::One(2),
event_name:
"UNC_M_MAJOR_MODES.WRITE",
brief_description:
"Cycles in a Major Mode; Write Major Mode",
public_description:
Some("Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_I_CACHE_ACK_PENDING_OCCUPANCY.SOURCE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(20),
umask:
Tuple::One(2),
event_name:
"UNC_I_CACHE_ACK_PENDING_OCCUPANCY.SOURCE",
brief_description:
"Write Ack Pending Occupancy; Select Source",
public_description:
Some("Accumulates the number of writes that have acquired ownership but have not yet returned their data to the uncore. These writes are generally queued up in the switch trying to get to the head of their queues so that they can post their data. The queue occuapancy increments when the ACK is received, and decrements when either the data is returned OR a tickle is received and ownership is released. Note that a single tickle can result in multiple decrements."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_R3_RxR_OCCUPANCY.DRS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(19),
umask:
Tuple::One(8),
event_name:
"UNC_R3_RxR_OCCUPANCY.DRS",
brief_description:
"Ingress Occupancy Accumulator; DRS",
public_description:
Some("Accumulates the occupancy of a given QPI Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency."),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_R3_RxR_INSERTS.NDR",
IntelPerformanceCounterDescription{event_code:
Tuple::One(17),
umask:
Tuple::One(4),
event_name:
"UNC_R3_RxR_INSERTS.NDR",
brief_description:
"Ingress Allocations; NDR",
public_description:
Some("Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_AD_INSERTS.SCHED0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(39),
umask:
Tuple::One(1),
event_name:
"UNC_H_TxR_AD_INSERTS.SCHED0",
brief_description:
"AD Egress Allocations; Scheduler 0",
public_description:
Some("AD Egress Allocations"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_FLITS_G2.NCS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(3),
umask:
Tuple::One(16),
event_name:
"UNC_Q_RxL_FLITS_G2.NCS",
brief_description:
"Flits Received - Group 2; Non-Coherent standard Rx Flits",
public_description:
Some("Counts the number of flits received from the QPI Link. This is one of three \'groups\' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each \'flit\' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four \'fits\', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI \'speed\' (for example, 8.0 GT/s), the \'transfers\' here refer to \'fits\'. Therefore, in L0, the system will transfer 1 \'flit\' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as \'data\' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual \'data\' and an additional 16 bits of other information. To calculate \'data\' bandwidth, one should therefore do: data flits * 8B / time."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_H_REQUESTS.WRITES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(1),
umask:
Tuple::One(12),
event_name:
"UNC_H_REQUESTS.WRITES",
brief_description:
"Read and Write Requests; Writes",
public_description:
Some("Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc)."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_OCCUPANCY_NDR",
IntelPerformanceCounterDescription{event_code:
Tuple::One(26),
umask:
Tuple::One(0),
event_name:
"UNC_Q_RxL_OCCUPANCY_NDR",
brief_description:
"RxQ Occupancy - NDR",
public_description:
Some("Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NDR flits only."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_H_TxR_BL_CYCLES_NE.ALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(53),
umask:
Tuple::One(3),
event_name:
"UNC_H_TxR_BL_CYCLES_NE.ALL",
brief_description:
"BL Egress Not Empty; All",
public_description:
Some("BL Egress Not Empty"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_R3_IIO_CREDITS_USED.NCB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(34),
umask:
Tuple::One(16),
event_name:
"UNC_R3_IIO_CREDITS_USED.NCB",
brief_description:
"to IIO BL Credit In Use",
public_description:
Some("Counts the number of cycles when the NCS/NCB/DRS credit is in use in the QPI for sending messages on BL to the IIO. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transfering data without coherency, and DRS is used for transfering data with coherency (cachable PCI transactions). This event can only track one message class at a time."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_P_DEMOTIONS_CORE3",
IntelPerformanceCounterDescription{event_code:
Tuple::One(33),
umask:
Tuple::One(0),
event_name:
"UNC_P_DEMOTIONS_CORE3",
brief_description:
"Core C State Demotions",
public_description:
Some("Counts the number of times when a configurable cores had a C-state demotion"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
Some("PCUFilter[7:0]"),
extsel:
false,}),
("UNC_I_TRANSACTIONS.PD_PREFETCHES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(21),
umask:
Tuple::One(4),
event_name:
"UNC_I_TRANSACTIONS.PD_PREFETCHES",
brief_description:
"Inbound Transaction Count; Read Prefetches",
public_description:
Some("Counts the number of \'Inbound\' transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_FLITS_G1.DRS_NONDATA",
IntelPerformanceCounterDescription{event_code:
Tuple::One(2),
umask:
Tuple::One(16),
event_name:
"UNC_Q_RxL_FLITS_G1.DRS_NONDATA",
brief_description:
"Flits Received - Group 1; DRS Header Flits",
public_description:
Some("Counts the number of flits received from the QPI Link. This is one of three \'groups\' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each \'flit\' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four \'fits\', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI \'speed\' (for example, 8.0 GT/s), the \'transfers\' here refer to \'fits\'. Therefore, in L0, the system will transfer 1 \'flit\' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as \'data\' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual \'data\' and an additional 16 bits of other information. To calculate \'data\' bandwidth, one should therefore do: data flits * 8B / time."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_R3_RxR_INSERTS.NCS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(17),
umask:
Tuple::One(32),
event_name:
"UNC_R3_RxR_INSERTS.NCS",
brief_description:
"Ingress Allocations; NCS",
public_description:
Some("Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_I_TRANSACTIONS.ORDERINGQ",
IntelPerformanceCounterDescription{event_code:
Tuple::One(21),
umask:
Tuple::One(8),
event_name:
"UNC_I_TRANSACTIONS.ORDERINGQ",
brief_description:
"Inbound Transaction Count; Select Source",
public_description:
Some("Counts the number of \'Inbound\' transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
Some("IRPFilter[4:0]"),
extsel:
false,}),
("UNC_C_LLC_LOOKUP.NID",
IntelPerformanceCounterDescription{event_code:
Tuple::One(52),
umask:
Tuple::One(65),
event_name:
"UNC_C_LLC_LOOKUP.NID",
brief_description:
"Cache Lookups; RTID",
public_description:
Some("Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set filter mask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
Some("CBoFilter[22:18], CBoFilter[17:10]"),
extsel:
false,}),
("UNC_M_DRAM_REFRESH.HIGH",
IntelPerformanceCounterDescription{event_code:
Tuple::One(5),
umask:
Tuple::One(4),
event_name:
"UNC_M_DRAM_REFRESH.HIGH",
brief_description:
"Number of DRAM Refreshes Issued",
public_description:
Some("Counts the number of refreshes issued."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_R2_RING_BL_USED.CCW_EVEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(9),
umask:
Tuple::One(4),
event_name:
"UNC_R2_RING_BL_USED.CCW_EVEN",
brief_description:
"R2 BL Ring in Use; Counterclockwise and Even",
public_description:
Some("Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_R2_IIO_CREDITS_ACQUIRED.DRS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(51),
umask:
Tuple::One(8),
event_name:
"UNC_R2_IIO_CREDITS_ACQUIRED.DRS",
brief_description:
"R2PCIe IIO Credit Acquired; DRS",
public_description:
Some("Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly)."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_C_LLC_VICTIMS.E_STATE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(55),
umask:
Tuple::One(2),
event_name:
"UNC_C_LLC_VICTIMS.E_STATE",
brief_description:
"Lines Victimized; Lines in E state",
public_description:
Some("Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_M_WPQ_OCCUPANCY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(129),
umask:
Tuple::One(0),
event_name:
"UNC_M_WPQ_OCCUPANCY",
brief_description:
"Write Pending Queue Occupancy",
public_description:
Some("Accumulates the occupancies of the Write Pending Queue each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have \'posted\' to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the \'not posted\' filter, we can track how long writes spent in the iMC before completions were sent to the HA. The \'posted\' filter, on the other hand, provides information about how much queueing is actually happenning in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_C_CLOCKTICKS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(0),
umask:
Tuple::One(0),
event_name:
"UNC_C_CLOCKTICKS",
brief_description:
"Uncore Clocks",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_AD_OCCUPANCY.SCHED1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(40),
umask:
Tuple::One(2),
event_name:
"UNC_H_TxR_AD_OCCUPANCY.SCHED1",
brief_description:
"AD Egress Occupancy; Scheduler 1",
public_description:
Some("AD Egress Occupancy"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_C_LLC_VICTIMS.S_STATE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(55),
umask:
Tuple::One(4),
event_name:
"UNC_C_LLC_VICTIMS.S_STATE",
brief_description:
"Lines Victimized; Lines in S State",
public_description:
Some("Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_AK_INSERTS.ALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(47),
umask:
Tuple::One(3),
event_name:
"UNC_H_TxR_AK_INSERTS.ALL",
brief_description:
"AK Egress Allocations; All",
public_description:
Some("AK Egress Allocations"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_AK_OCCUPANCY.SCHED1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(48),
umask:
Tuple::One(2),
event_name:
"UNC_H_TxR_AK_OCCUPANCY.SCHED1",
brief_description:
"AK Egress Occupancy; Scheduler 1",
public_description:
Some("AK Egress Occupancy"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_R2_RxR_CYCLES_NE.NCB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(16),
umask:
Tuple::One(16),
event_name:
"UNC_R2_RxR_CYCLES_NE.NCB",
brief_description:
"Ingress Cycles Not Empty; NCB",
public_description:
Some("Counts the number of cycles when the R2PCIe Ingress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_AK_OCCUPANCY.ALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(48),
umask:
Tuple::One(3),
event_name:
"UNC_H_TxR_AK_OCCUPANCY.ALL",
brief_description:
"AK Egress Occupancy; All",
public_description:
Some("AK Egress Occupancy"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_U_RACU_REQUESTS.COUNT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(70),
umask:
Tuple::One(1),
event_name:
"UNC_U_RACU_REQUESTS.COUNT",
brief_description:
"RACU Request",
public_description:
None,
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("UBOX"),
filter:
None,
extsel:
true,}),
("UNC_H_CLOCKTICKS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(0),
umask:
Tuple::One(0),
event_name:
"UNC_H_CLOCKTICKS",
brief_description:
"uclks",
public_description:
Some("Counts the number of uclks in the HA. This will be slightly different than the count in the Ubox because of enable/freeze delays. The HA is on the other side of the die from the fixed Ubox uclk counter, so the drift could be somewhat larger than in units that are closer like the QPI Agent."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_BL_INSERTS.SCHED1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(51),
umask:
Tuple::One(2),
event_name:
"UNC_H_TxR_BL_INSERTS.SCHED1",
brief_description:
"BL Egress Allocations; Scheduler 1",
public_description:
Some("BL Egress Allocations"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_C_COUNTER0_OCCUPANCY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(31),
umask:
Tuple::One(0),
event_name:
"UNC_C_COUNTER0_OCCUPANCY",
brief_description:
"Counter 0 Occupancy",
public_description:
Some("Since occupancy counts can only be captured in the Cbo\'s 0 counter, this event allows a user to capture occupancy related information by filtering the Cb0 occupancy count captured in Counter 0. The filtering available is found in the control register - threshold, invert and edge detect. E.g. setting threshold to 1 can effectively monitor how many cycles the monitored queue has an entry."),
counter:
Counter::Programmable(14),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_C_RING_BL_USED.UP_ODD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(29),
umask:
Tuple::One(2),
event_name:
"UNC_C_RING_BL_USED.UP_ODD",
brief_description:
"BL Ring in Use; Up and Odd",
public_description:
Some("Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the \'UP\' direction is on the clockwise ring and \'DN\' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring."),
counter:
Counter::Programmable(12),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_R2_TxR_CYCLES_NE.AK",
IntelPerformanceCounterDescription{event_code:
Tuple::One(35),
umask:
Tuple::One(2),
event_name:
"UNC_R2_TxR_CYCLES_NE.AK",
brief_description:
"Egress Cycles Not Empty; AK",
public_description:
Some("Counts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity."),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_P_CORE7_TRANSITION_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(10),
umask:
Tuple::One(0),
event_name:
"UNC_P_CORE7_TRANSITION_CYCLES",
brief_description:
"Core C State Transition Cycles",
public_description:
Some("Number of cycles spent performing core C state transitions. There is one event per core."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
true,}),
("UNC_H_DIRECTORY_UPDATE.ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(13),
umask:
Tuple::One(3),
event_name:
"UNC_H_DIRECTORY_UPDATE.ANY",
brief_description:
"Directory Updates; Any Directory Update",
public_description:
Some("Counts the number of directory updates that were required. These result in writes to the memory controller. This can be filtered by directory sets and directory clears."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_R3_VN0_CREDITS_REJECT.SNP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(55),
umask:
Tuple::One(2),
event_name:
"UNC_R3_VN0_CREDITS_REJECT.SNP",
brief_description:
"VN0 Credit Acquisition Failed on DRS; SNP Message Class",
public_description:
Some("Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(25),
umask:
Tuple::One(2),
event_name:
"UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN1",
brief_description:
"HA iMC CHN0 WPQ Credits Empty - Special; Channel 1",
public_description:
Some("Counts the number of cycles when there are no \'special\' credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC\'s WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and \'special\' requests such as ISOCH writes. This count only tracks the \'special\' credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_R3_VNA_CREDITS_REJECT.HOM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(52),
umask:
Tuple::One(1),
event_name:
"UNC_R3_VNA_CREDITS_REJECT.HOM",
brief_description:
"VNA Credit Reject; HOM Message Class",
public_description:
Some("Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_STALLS.EGRESS_CREDITS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(53),
umask:
Tuple::One(64),
event_name:
"UNC_Q_RxL_STALLS.EGRESS_CREDITS",
brief_description:
"Stalls Sending to R3QPI; Egress Credits",
public_description:
Some("Number of stalls trying to send to R3QPI."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_AD_CYCLES_NE.ALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(41),
umask:
Tuple::One(3),
event_name:
"UNC_H_TxR_AD_CYCLES_NE.ALL",
brief_description:
"AD Egress Not Empty; All",
public_description:
Some("AD Egress Not Empty"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_P_CORE4_TRANSITION_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(7),
umask:
Tuple::One(0),
event_name:
"UNC_P_CORE4_TRANSITION_CYCLES",
brief_description:
"Core C State Transition Cycles",
public_description:
Some("Number of cycles spent performing core C state transitions. There is one event per core."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
true,}),
("UNC_C_RxR_OCCUPANCY.IRQ",
IntelPerformanceCounterDescription{event_code:
Tuple::One(17),
umask:
Tuple::One(1),
event_name:
"UNC_C_RxR_OCCUPANCY.IRQ",
brief_description:
"Ingress Occupancy; IRQ",
public_description:
Some("Counts number of entries in the specified Ingress queue in each cycle."),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_R2_RING_AK_USED.CCW_EVEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(8),
umask:
Tuple::One(4),
event_name:
"UNC_R2_RING_AK_USED.CCW_EVEN",
brief_description:
"R2 AK Ring in Use; Counterclockwise and Even",
public_description:
Some("Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_H_TAD_REQUESTS_G0.REGION3",
IntelPerformanceCounterDescription{event_code:
Tuple::One(27),
umask:
Tuple::One(8),
event_name:
"UNC_H_TAD_REQUESTS_G0.REGION3",
brief_description:
"HA Requests to a TAD Region - Group 0; TAD Region 3",
public_description:
Some("Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for \'Monroe\' systems that use the TAD to enable individual channels to enter self-refresh to save power."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_R3_IIO_CREDITS_ACQUIRED.DRS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(32),
umask:
Tuple::One(8),
event_name:
"UNC_R3_IIO_CREDITS_ACQUIRED.DRS",
brief_description:
"to IIO BL Credit Acquired",
public_description:
Some("Counts the number of times the NCS/NCB/DRS credit is acquried in the QPI for sending messages on BL to the IIO. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transfering data without coherency, and DRS is used for transfering data with coherency (cachable PCI transactions). This event can only track one message class at a time."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_C_RING_BL_USED.DOWN_EVEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(29),
umask:
Tuple::One(4),
event_name:
"UNC_C_RING_BL_USED.DOWN_EVEN",
brief_description:
"BL Ring in Use; Down and Even",
public_description:
Some("Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the \'UP\' direction is on the clockwise ring and \'DN\' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring."),
counter:
Counter::Programmable(12),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_C_TOR_OCCUPANCY.NID_EVICTION",
IntelPerformanceCounterDescription{event_code:
Tuple::One(54),
umask:
Tuple::One(68),
event_name:
"UNC_C_TOR_OCCUPANCY.NID_EVICTION",
brief_description:
"TOR Occupancy; NID Matched Evictions",
public_description:
Some("For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent \'filters\' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select \'MISS_OPC_MATCH\' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)"),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
Some("CBoFilter[17:10]"),
extsel:
false,}),
("UNC_C_TxR_INSERTS.AK_CACHE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(2),
umask:
Tuple::One(2),
event_name:
"UNC_C_TxR_INSERTS.AK_CACHE",
brief_description:
"Egress Allocations; AK - Cachebo",
public_description:
Some("Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_C_TxR_INSERTS.BL_CACHE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(2),
umask:
Tuple::One(4),
event_name:
"UNC_C_TxR_INSERTS.BL_CACHE",
brief_description:
"Egress Allocations; BL - Cacheno",
public_description:
Some("Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_R3_RING_AK_USED.CW_EVEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(8),
umask:
Tuple::One(1),
event_name:
"UNC_R3_RING_AK_USED.CW_EVEN",
brief_description:
"R3 AK Ring in Use; Clockwise and Even",
public_description:
Some("Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop."),
counter:
Counter::Programmable(7),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_R3_RxR_OCCUPANCY.SNP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(19),
umask:
Tuple::One(2),
event_name:
"UNC_R3_RxR_OCCUPANCY.SNP",
brief_description:
"Ingress Occupancy Accumulator; SNP",
public_description:
Some("Accumulates the occupancy of a given QPI Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency."),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_Q_VNA_CREDIT_RETURN_OCCUPANCY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(27),
umask:
Tuple::One(0),
event_name:
"UNC_Q_VNA_CREDIT_RETURN_OCCUPANCY",
brief_description:
"VNA Credits Pending Return - Occupancy",
public_description:
Some("Number of VNA credits in the Rx side that are waitng to be returned back across the link."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_P_PROCHOT_INTERNAL_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(9),
umask:
Tuple::One(0),
event_name:
"UNC_P_PROCHOT_INTERNAL_CYCLES",
brief_description:
"Internal Prochot",
public_description:
Some("Counts the number of cycles that we are in Interal PROCHOT mode. This mode is triggered when a sensor on the die determines that we are too hot and must throttle to avoid damaging the chip."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(24),
umask:
Tuple::One(1),
event_name:
"UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN0",
brief_description:
"HA iMC CHN0 WPQ Credits Empty - Regular; Channel 0",
public_description:
Some("Counts the number of cycles when there are no \'regular\' credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC\'s WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and \'special\' requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_AK_INSERTS.SCHED0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(47),
umask:
Tuple::One(1),
event_name:
"UNC_H_TxR_AK_INSERTS.SCHED0",
brief_description:
"AK Egress Allocations; Scheduler 0",
public_description:
Some("AK Egress Allocations"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_DIRECT2CORE_TXN_OVERRIDE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(19),
umask:
Tuple::One(0),
event_name:
"UNC_H_DIRECT2CORE_TXN_OVERRIDE",
brief_description:
"Number of Reads that had Direct2Core Overridden",
public_description:
Some("Number of Reads where Direct2Core overridden"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_R3_RING_IV_USED.ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(10),
umask:
Tuple::One(15),
event_name:
"UNC_R3_RING_IV_USED.ANY",
brief_description:
"R3 IV Ring in Use; Any",
public_description:
Some("Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. The IV ring is unidirectional. Whether UP or DN is used is dependent on the system programming. Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time."),
counter:
Counter::Programmable(7),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_R3_IIO_CREDITS_REJECT.NCS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(33),
umask:
Tuple::One(32),
event_name:
"UNC_R3_IIO_CREDITS_REJECT.NCS",
brief_description:
"to IIO BL Credit Rejected",
public_description:
Some("Counts the number of times that a request attempted to acquire an NCS/NCB/DRS credit in the QPI for sending messages on BL to the IIO but was rejected because no credit was available. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transfering data without coherency, and DRS is used for transfering data with coherency (cachable PCI transactions). This event can only track one message class at a time."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_I_CACHE_WRITE_OCCUPANCY.SOURCE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(17),
umask:
Tuple::One(2),
event_name:
"UNC_I_CACHE_WRITE_OCCUPANCY.SOURCE",
brief_description:
"Outstanding Write Occupancy; Select Source",
public_description:
Some("Accumulates the number of writes (and write prefetches) that are outstanding in the uncore in each cycle. This can be used with the transaction count event to calculate the average latency in the uncore. The occupancy increments when the ownership fetch/prefetch is issued, and decrements the data is returned to the uncore."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_R3_VNA_CREDIT_CYCLES_USED",
IntelPerformanceCounterDescription{event_code:
Tuple::One(50),
umask:
Tuple::One(0),
event_name:
"UNC_R3_VNA_CREDIT_CYCLES_USED",
brief_description:
"Cycles with 1 or more VNA credits in use",
public_description:
Some("Number of QPI uclk cycles with one or more VNA credits in use. This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average number of used VNA credits."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_R3_VN0_CREDITS_REJECT.NCB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(55),
umask:
Tuple::One(16),
event_name:
"UNC_R3_VN0_CREDITS_REJECT.NCB",
brief_description:
"VN0 Credit Acquisition Failed on DRS; NCB Message Class",
public_description:
Some("Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_FLITS_G2.NCB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(3),
umask:
Tuple::One(12),
event_name:
"UNC_Q_RxL_FLITS_G2.NCB",
brief_description:
"Flits Received - Group 2; Non-Coherent Rx Flits",
public_description:
Some("Counts the number of flits received from the QPI Link. This is one of three \'groups\' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each \'flit\' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four \'fits\', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI \'speed\' (for example, 8.0 GT/s), the \'transfers\' here refer to \'fits\'. Therefore, in L0, the system will transfer 1 \'flit\' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as \'data\' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual \'data\' and an additional 16 bits of other information. To calculate \'data\' bandwidth, one should therefore do: data flits * 8B / time."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_H_DIRECTORY_LOOKUP.NO_SNP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(12),
umask:
Tuple::One(2),
event_name:
"UNC_H_DIRECTORY_LOOKUP.NO_SNP",
brief_description:
"Directory Lookups; Snoop Not Needed",
public_description:
Some("Counts the number of transactions that looked up the directory. Can be filtered by requests that had to snoop and those that did not have to."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(21),
umask:
Tuple::One(2),
event_name:
"UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN1",
brief_description:
"iMC RPQ Credits Empty - Regular; Channel 1",
public_description:
Some("Counts the number of cycles when there are no \'regular\' credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC\'s RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and \'special\' requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_AK_CYCLES_FULL.SCHED1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(50),
umask:
Tuple::One(2),
event_name:
"UNC_H_TxR_AK_CYCLES_FULL.SCHED1",
brief_description:
"AK Egress Full; Scheduler 1",
public_description:
Some("AK Egress Full"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_FLITS_G1.DRS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(2),
umask:
Tuple::One(24),
event_name:
"UNC_Q_RxL_FLITS_G1.DRS",
brief_description:
"Flits Received - Group 1; DRS Flits (both Header and Data)",
public_description:
Some("Counts the number of flits received from the QPI Link. This is one of three \'groups\' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each \'flit\' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four \'fits\', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI \'speed\' (for example, 8.0 GT/s), the \'transfers\' here refer to \'fits\'. Therefore, in L0, the system will transfer 1 \'flit\' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as \'data\' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual \'data\' and an additional 16 bits of other information. To calculate \'data\' bandwidth, one should therefore do: data flits * 8B / time."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_R2_TxR_CYCLES_FULL.AK",
IntelPerformanceCounterDescription{event_code:
Tuple::One(37),
umask:
Tuple::One(2),
event_name:
"UNC_R2_TxR_CYCLES_FULL.AK",
brief_description:
"Egress Cycles Full; AK",
public_description:
Some("Counts the number of cycles when the R2PCIe Egress buffer is full."),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxL_FLITS_G1.HOM_REQ",
IntelPerformanceCounterDescription{event_code:
Tuple::One(0),
umask:
Tuple::One(2),
event_name:
"UNC_Q_TxL_FLITS_G1.HOM_REQ",
brief_description:
"Flits Transferred - Group 1; HOM Request Flits",
public_description:
Some("Counts the number of flits trasmitted across the QPI Link. This is one of three \'groups\' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each \'flit\' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four \'fits\', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI \'speed\' (for example, 8.0 GT/s), the \'transfers\' here refer to \'fits\'. Therefore, in L0, the system will transfer 1 \'flit\' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as \'data\' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual \'data\' and an additional 16 bits of other information. To calculate \'data\' bandwidth, one should therefore do: data flits * 8B / time."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(21),
umask:
Tuple::One(1),
event_name:
"UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN0",
brief_description:
"iMC RPQ Credits Empty - Regular; Channel 0",
public_description:
Some("Counts the number of cycles when there are no \'regular\' credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC\'s RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and \'special\' requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_AD_INSERTS.ALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(39),
umask:
Tuple::One(3),
event_name:
"UNC_H_TxR_AD_INSERTS.ALL",
brief_description:
"AD Egress Allocations; All",
public_description:
Some("AD Egress Allocations"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_R2_RING_AD_USED.CW_EVEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(7),
umask:
Tuple::One(1),
event_name:
"UNC_R2_RING_AD_USED.CW_EVEN",
brief_description:
"R2 AD Ring in Use; Clockwise and Even",
public_description:
Some("Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_M_MAJOR_MODES.PARTIAL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(7),
umask:
Tuple::One(4),
event_name:
"UNC_M_MAJOR_MODES.PARTIAL",
brief_description:
"Cycles in a Major Mode; Partial Major Mode",
public_description:
Some("Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_STALLS.BGF_NCS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(53),
umask:
Tuple::One(4),
event_name:
"UNC_Q_RxL_STALLS.BGF_NCS",
brief_description:
"Stalls Sending to R3QPI; BGF Stall - NDR",
public_description:
Some("Number of stalls trying to send to R3QPI."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_R2_RING_AD_USED.CCW_EVEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(7),
umask:
Tuple::One(4),
event_name:
"UNC_R2_RING_AD_USED.CCW_EVEN",
brief_description:
"R2 AD Ring in Use; Counterclockwise and Even",
public_description:
Some("Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_FLITS_G2.NDR_AD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(3),
umask:
Tuple::One(1),
event_name:
"UNC_Q_RxL_FLITS_G2.NDR_AD",
brief_description:
"Flits Received - Group 2; Non-Data Response Rx Flits - AD",
public_description:
Some("Counts the number of flits received from the QPI Link. This is one of three \'groups\' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each \'flit\' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four \'fits\', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI \'speed\' (for example, 8.0 GT/s), the \'transfers\' here refer to \'fits\'. Therefore, in L0, the system will transfer 1 \'flit\' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as \'data\' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual \'data\' and an additional 16 bits of other information. To calculate \'data\' bandwidth, one should therefore do: data flits * 8B / time."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_H_IMC_WRITES.PARTIAL_ISOCH",
IntelPerformanceCounterDescription{event_code:
Tuple::One(26),
umask:
Tuple::One(8),
event_name:
"UNC_H_IMC_WRITES.PARTIAL_ISOCH",
brief_description:
"HA to iMC Full Line Writes Issued; ISOCH Partial",
public_description:
Some("Counts the total number of full line writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_FLITS_G2.NCB_NONDATA",
IntelPerformanceCounterDescription{event_code:
Tuple::One(3),
umask:
Tuple::One(8),
event_name:
"UNC_Q_RxL_FLITS_G2.NCB_NONDATA",
brief_description:
"Flits Received - Group 2; Non-Coherent non-data Rx Flits",
public_description:
Some("Counts the number of flits received from the QPI Link. This is one of three \'groups\' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each \'flit\' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four \'fits\', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI \'speed\' (for example, 8.0 GT/s), the \'transfers\' here refer to \'fits\'. Therefore, in L0, the system will transfer 1 \'flit\' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as \'data\' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual \'data\' and an additional 16 bits of other information. To calculate \'data\' bandwidth, one should therefore do: data flits * 8B / time."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_C_RxR_IPQ_RETRY.ADDR_CONFLICT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(49),
umask:
Tuple::One(4),
event_name:
"UNC_C_RxR_IPQ_RETRY.ADDR_CONFLICT",
brief_description:
"Probe Queue Retries; Address Conflict",
public_description:
Some("Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN3",
IntelPerformanceCounterDescription{event_code:
Tuple::One(24),
umask:
Tuple::One(8),
event_name:
"UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN3",
brief_description:
"HA iMC CHN0 WPQ Credits Empty - Regular; Channel 3",
public_description:
Some("Counts the number of cycles when there are no \'regular\' credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC\'s WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and \'special\' requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_C_TOR_INSERTS.NID_EVICTION",
IntelPerformanceCounterDescription{event_code:
Tuple::One(53),
umask:
Tuple::One(68),
event_name:
"UNC_C_TOR_INSERTS.NID_EVICTION",
brief_description:
"TOR Inserts; NID Matched Evictions",
public_description:
Some("Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent \'filters\' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select \'MISS_OPC_MATCH\' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
Some("CBoFilter[17:10]"),
extsel:
false,}),
("UNC_H_IMC_RETRY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(30),
umask:
Tuple::One(0),
event_name:
"UNC_H_IMC_RETRY",
brief_description:
"Retry Events",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_CLOCKTICKS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(0),
umask:
Tuple::One(0),
event_name:
"UNC_M_CLOCKTICKS",
brief_description:
"uclks",
public_description:
Some("Uncore Fixed Counter - uclks"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxL_FLITS_G2.NCS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(1),
umask:
Tuple::One(16),
event_name:
"UNC_Q_TxL_FLITS_G2.NCS",
brief_description:
"Flits Transferred - Group 2; Non-Coherent standard Tx Flits",
public_description:
Some("Counts the number of flits trasmitted across the QPI Link. This is one of three \'groups\' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each \'flit\' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four \'fits\', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI \'speed\' (for example, 8.0 GT/s), the \'transfers\' here refer to \'fits\'. Therefore, in L0, the system will transfer 1 \'flit\' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as \'data\' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual \'data\' and an additional 16 bits of other information. To calculate \'data\' bandwidth, one should therefore do: data flits * 8B / time."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_P_PROCHOT_EXTERNAL_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(10),
umask:
Tuple::One(0),
event_name:
"UNC_P_PROCHOT_EXTERNAL_CYCLES",
brief_description:
"External Prochot",
public_description:
Some("Counts the number of cycles that we are in external PROCHOT mode. This mode is triggered when a sensor off the die determines that something off-die (like DRAM) is too hot and must throttle to avoid damaging the chip."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_R3_VN0_CREDITS_USED.SNP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(54),
umask:
Tuple::One(2),
event_name:
"UNC_R3_VN0_CREDITS_USED.SNP",
brief_description:
"VN0 Credit Used; SNP Message Class",
public_description:
Some("Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_I_CACHE_TOTAL_OCCUPANCY.ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(18),
umask:
Tuple::One(1),
event_name:
"UNC_I_CACHE_TOTAL_OCCUPANCY.ANY",
brief_description:
"Total Write Cache Occupancy; Any Source",
public_description:
Some("Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_R3_VN0_CREDITS_REJECT.HOM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(55),
umask:
Tuple::One(1),
event_name:
"UNC_R3_VN0_CREDITS_REJECT.HOM",
brief_description:
"VN0 Credit Acquisition Failed on DRS; HOM Message Class",
public_description:
Some("Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_C_RxR_ISMQ_RETRY.QPI_CREDITS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(51),
umask:
Tuple::One(16),
event_name:
"UNC_C_RxR_ISMQ_RETRY.QPI_CREDITS",
brief_description:
"ISMQ Retries; No QPI Credits",
public_description:
Some("Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_M_PRE_COUNT.PAGE_CLOSE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(2),
umask:
Tuple::One(2),
event_name:
"UNC_M_PRE_COUNT.PAGE_CLOSE",
brief_description:
"DRAM Precharge commands.; Precharge due to timer expiration",
public_description:
Some("Counts the number of DRAM Precharge commands sent on this channel."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_H_RING_BL_USED.CW_ODD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(64),
umask:
Tuple::One(2),
event_name:
"UNC_H_RING_BL_USED.CW_ODD",
brief_description:
"HA BL Ring in Use; Clockwise and Odd",
public_description:
Some("Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_C_RING_BL_USED.UP_EVEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(29),
umask:
Tuple::One(1),
event_name:
"UNC_C_RING_BL_USED.UP_EVEN",
brief_description:
"BL Ring in Use; Up and Even",
public_description:
Some("Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the \'UP\' direction is on the clockwise ring and \'DN\' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring."),
counter:
Counter::Programmable(12),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_C_RING_BOUNCES.AK_CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(5),
umask:
Tuple::One(2),
event_name:
"UNC_C_RING_BOUNCES.AK_CORE",
brief_description:
"Number of LLC responses that bounced on the Ring.; Acknowledgements to core",
public_description:
None,
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_C_RING_SINK_STARVED.AK_CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(6),
umask:
Tuple::One(2),
event_name:
"UNC_C_RING_SINK_STARVED.AK_CORE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_M_POWER_THROTTLE_CYCLES.RANK2",
IntelPerformanceCounterDescription{event_code:
Tuple::One(65),
umask:
Tuple::One(4),
event_name:
"UNC_M_POWER_THROTTLE_CYCLES.RANK2",
brief_description:
"Throttle Cycles for Rank 0; DIMM ID",
public_description:
Some("Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_C_RxR_ISMQ_RETRY.FULL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(51),
umask:
Tuple::One(2),
event_name:
"UNC_C_RxR_ISMQ_RETRY.FULL",
brief_description:
"ISMQ Retries; No Egress Credits",
public_description:
Some("Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_R2_TxR_CYCLES_NE.AD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(35),
umask:
Tuple::One(1),
event_name:
"UNC_R2_TxR_CYCLES_NE.AD",
brief_description:
"Egress Cycles Not Empty; AD",
public_description:
Some("Counts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity."),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_Q_CTO_COUNT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(56),
umask:
Tuple::One(0),
event_name:
"UNC_Q_CTO_COUNT",
brief_description:
"Count of CTO Events",
public_description:
Some("Counts the number of CTO (cluster trigger outs) events that were asserted across the two slots. If both slots trigger in a given cycle, the event will increment by 2. You can use edge detect to count the number of cases when both events triggered."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_H_TxR_BL.DRS_CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(16),
umask:
Tuple::One(2),
event_name:
"UNC_H_TxR_BL.DRS_CORE",
brief_description:
"Outbound DRS Ring Transactions to Cache; Data to Core",
public_description:
Some("Counts the number of DRS messages sent out on the BL ring. This can be filtered by the destination."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_I_ADDRESS_MATCH.STALL_COUNT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(23),
umask:
Tuple::One(1),
event_name:
"UNC_I_ADDRESS_MATCH.STALL_COUNT",
brief_description:
"Address Match (Conflict) Count; Conflict Stalls",
public_description:
Some("Counts the number of times when an inbound write (from a device to memory or another device) had an address match with another request in the write cache."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_U_EVENT_MSG.INT_PRIO",
IntelPerformanceCounterDescription{event_code:
Tuple::One(66),
umask:
Tuple::One(16),
event_name:
"UNC_U_EVENT_MSG.INT_PRIO",
brief_description:
"VLW Received",
public_description:
Some("Virtual Logical Wire (legacy) message were received from Uncore. Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("UBOX"),
filter:
None,
extsel:
false,}),
("UNC_H_RING_AD_USED.CW_ODD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(62),
umask:
Tuple::One(2),
event_name:
"UNC_H_RING_AD_USED.CW_ODD",
brief_description:
"HA AD Ring in Use; Clockwise and Odd",
public_description:
Some("Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxL_INSERTS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(4),
umask:
Tuple::One(0),
event_name:
"UNC_Q_TxL_INSERTS",
brief_description:
"Tx Flit Buffer Allocations",
public_description:
Some("Number of allocations into the QPI Tx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_H_RING_AD_USED.CW_EVEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(62),
umask:
Tuple::One(1),
event_name:
"UNC_H_RING_AD_USED.CW_EVEN",
brief_description:
"HA AD Ring in Use; Clockwise and Even",
public_description:
Some("Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_IMC_WRITES.PARTIAL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(26),
umask:
Tuple::One(2),
event_name:
"UNC_H_IMC_WRITES.PARTIAL",
brief_description:
"HA to iMC Full Line Writes Issued; Partial Non-ISOCH",
public_description:
Some("Counts the total number of full line writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_P_FREQ_MAX_CURRENT_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(7),
umask:
Tuple::One(0),
event_name:
"UNC_P_FREQ_MAX_CURRENT_CYCLES",
brief_description:
"Current Strongest Upper Limit Cycles",
public_description:
Some("Counts the number of cycles when current is the upper limit on frequency."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_C_RING_BOUNCES.IV_CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(5),
umask:
Tuple::One(8),
event_name:
"UNC_C_RING_BOUNCES.IV_CORE",
brief_description:
"Number of LLC responses that bounced on the Ring.; Snoops of processor\'s cache.",
public_description:
None,
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_R3_VNA_CREDITS_REJECT.SNP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(52),
umask:
Tuple::One(2),
event_name:
"UNC_R3_VNA_CREDITS_REJECT.SNP",
brief_description:
"VNA Credit Reject; SNP Message Class",
public_description:
Some("Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_M_CAS_COUNT.ALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(4),
umask:
Tuple::One(15),
event_name:
"UNC_M_CAS_COUNT.ALL",
brief_description:
"DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (w/ and w/out auto-pre)",
public_description:
Some("DRAM RD_CAS and WR_CAS Commands"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_WPQ_INSERTS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(32),
umask:
Tuple::One(0),
event_name:
"UNC_M_WPQ_INSERTS",
brief_description:
"Write Pending Queue Allocations",
public_description:
Some("Counts the number of allocations into the Write Pending Queue. This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have \'posted\' to the iMC."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_STALLS.BGF_NDR",
IntelPerformanceCounterDescription{event_code:
Tuple::One(53),
umask:
Tuple::One(32),
event_name:
"UNC_Q_RxL_STALLS.BGF_NDR",
brief_description:
"Stalls Sending to R3QPI; BGF Stall - NCS",
public_description:
Some("Number of stalls trying to send to R3QPI."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_P_VOLT_TRANS_CYCLES_INCREASE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(1),
umask:
Tuple::One(0),
event_name:
"UNC_P_VOLT_TRANS_CYCLES_INCREASE",
brief_description:
"Cycles Increasing Voltage",
public_description:
Some("Counts the number of cycles when the system is increasing voltage. There is no filtering supported with this event. One can use it as a simple event, or use it conjunction with the occupancy events to monitor the number of cores or threads that were impacted by the transition."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_R2_RxR_CYCLES_NE.DRS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(16),
umask:
Tuple::One(8),
event_name:
"UNC_R2_RxR_CYCLES_NE.DRS",
brief_description:
"Ingress Cycles Not Empty; DRS",
public_description:
Some("Counts the number of cycles when the R2PCIe Ingress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_M_POWER_THROTTLE_CYCLES.RANK0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(65),
umask:
Tuple::One(1),
event_name:
"UNC_M_POWER_THROTTLE_CYCLES.RANK0",
brief_description:
"Throttle Cycles for Rank 0; DIMM ID",
public_description:
Some("Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_C_TxR_ADS_USED",
IntelPerformanceCounterDescription{event_code:
Tuple::One(4),
umask:
Tuple::One(0),
event_name:
"UNC_C_TxR_ADS_USED",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_C_RxR_INSERTS.IPQ",
IntelPerformanceCounterDescription{event_code:
Tuple::One(19),
umask:
Tuple::One(4),
event_name:
"UNC_C_RxR_INSERTS.IPQ",
brief_description:
"Ingress Allocations; IPQ",
public_description:
Some("Counts number of allocations per cycle into the specified Ingress queue."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_C_RxR_IRQ_RETRY.QPI_CREDITS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(50),
umask:
Tuple::One(16),
event_name:
"UNC_C_RxR_IRQ_RETRY.QPI_CREDITS",
brief_description:
"Ingress Request Queue Rejects; No QPI Credits",
public_description:
None,
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_C_RING_BL_USED.DOWN_ODD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(29),
umask:
Tuple::One(8),
event_name:
"UNC_C_RING_BL_USED.DOWN_ODD",
brief_description:
"BL Ring in Use; Down and Odd",
public_description:
Some("Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the \'UP\' direction is on the clockwise ring and \'DN\' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring."),
counter:
Counter::Programmable(12),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_STALLS.GV",
IntelPerformanceCounterDescription{event_code:
Tuple::One(53),
umask:
Tuple::One(128),
event_name:
"UNC_Q_RxL_STALLS.GV",
brief_description:
"Stalls Sending to R3QPI; GV",
public_description:
Some("Number of stalls trying to send to R3QPI."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_R3_RxR_CYCLES_NE.DRS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(16),
umask:
Tuple::One(8),
event_name:
"UNC_R3_RxR_CYCLES_NE.DRS",
brief_description:
"Ingress Cycles Not Empty; DRS",
public_description:
Some("Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_P_FREQ_BAND0_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(11),
umask:
Tuple::One(0),
event_name:
"UNC_P_FREQ_BAND0_CYCLES",
brief_description:
"Frequency Residency",
public_description:
Some("Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter. One can use all four counters with this event, so it is possible to track up to 4 configurable bands. One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
Some("PCUFilter[7:0]"),
extsel:
false,}),
("UNC_Q_RxL_INSERTS_HOM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(12),
umask:
Tuple::One(0),
event_name:
"UNC_Q_RxL_INSERTS_HOM",
brief_description:
"Rx Flit Buffer Allocations - HOM",
public_description:
Some("Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only HOM flits."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_I_CACHE_TOTAL_OCCUPANCY.SOURCE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(18),
umask:
Tuple::One(2),
event_name:
"UNC_I_CACHE_TOTAL_OCCUPANCY.SOURCE",
brief_description:
"Total Write Cache Occupancy; Select Source",
public_description:
Some("Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_C_MISC.RSPI_WAS_FSE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(57),
umask:
Tuple::One(1),
event_name:
"UNC_C_MISC.RSPI_WAS_FSE",
brief_description:
"Cbo Misc; Silent Snoop Eviction",
public_description:
Some("Miscellaneous events in the Cbo."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_C_TOR_INSERTS.MISS_ALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(53),
umask:
Tuple::One(10),
event_name:
"UNC_C_TOR_INSERTS.MISS_ALL",
brief_description:
"TOR Inserts; Miss All",
public_description:
Some("Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent \'filters\' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select \'MISS_OPC_MATCH\' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(30),
umask:
Tuple::One(4),
event_name:
"UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCS",
brief_description:
"VN0 Credit Consumed; NCS",
public_description:
Some("Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_I_RxR_AK_CYCLES_FULL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(11),
umask:
Tuple::One(0),
event_name:
"UNC_I_RxR_AK_CYCLES_FULL",
brief_description:
"tbd",
public_description:
Some("Counts the number of cycles when the AK Ingress is full. This queue is where the IRP receives responses from R2PCIe (the ring)."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_C_TxR_INSERTS.IV_CACHE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(2),
umask:
Tuple::One(8),
event_name:
"UNC_C_TxR_INSERTS.IV_CACHE",
brief_description:
"Egress Allocations; IV - Cachebo",
public_description:
Some("Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_P_CORE3_TRANSITION_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(6),
umask:
Tuple::One(0),
event_name:
"UNC_P_CORE3_TRANSITION_CYCLES",
brief_description:
"Core C State Transition Cycles",
public_description:
Some("Number of cycles spent performing core C state transitions. There is one event per core."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
true,}),
("UNC_U_U2C_EVENTS.MONITOR_T1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(67),
umask:
Tuple::One(2),
event_name:
"UNC_U_U2C_EVENTS.MONITOR_T1",
brief_description:
"Monitor Sent to T0; Monitor T1",
public_description:
Some("Events coming from Uncore can be sent to one or all cores"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("UBOX"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_FLITS_G0.DATA",
IntelPerformanceCounterDescription{event_code:
Tuple::One(1),
umask:
Tuple::One(2),
event_name:
"UNC_Q_RxL_FLITS_G0.DATA",
brief_description:
"Flits Received - Group 0; Data Tx Flits",
public_description:
Some("Counts the number of flits received from the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each \'flit\' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four \'fits\', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI \'speed\' (for example, 8.0 GT/s), the \'transfers\' here refer to \'fits\'. Therefore, in L0, the system will transfer 1 \'flit\' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as \'data\' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual \'data\' and an additional 16 bits of other information. To calculate \'data\' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_H_TAD_REQUESTS_G1.REGION8",
IntelPerformanceCounterDescription{event_code:
Tuple::One(28),
umask:
Tuple::One(1),
event_name:
"UNC_H_TAD_REQUESTS_G1.REGION8",
brief_description:
"HA Requests to a TAD Region - Group 1; TAD Region 8",
public_description:
Some("Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 8 to 10. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for \'Monroe\' systems that use the TAD to enable individual channels to enter self-refresh to save power."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_C_RxR_INT_STARVED.IPQ",
IntelPerformanceCounterDescription{event_code:
Tuple::One(20),
umask:
Tuple::One(4),
event_name:
"UNC_C_RxR_INT_STARVED.IPQ",
brief_description:
"Ingress Internal Starvation Cycles; IPQ",
public_description:
Some("Counts cycles in internal starvation. This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_FLITS_G0.NON_DATA",
IntelPerformanceCounterDescription{event_code:
Tuple::One(1),
umask:
Tuple::One(4),
event_name:
"UNC_Q_RxL_FLITS_G0.NON_DATA",
brief_description:
"Flits Received - Group 0; Non-Data protocol Tx Flits",
public_description:
Some("Counts the number of flits received from the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each \'flit\' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four \'fits\', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI \'speed\' (for example, 8.0 GT/s), the \'transfers\' here refer to \'fits\'. Therefore, in L0, the system will transfer 1 \'flit\' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as \'data\' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual \'data\' and an additional 16 bits of other information. To calculate \'data\' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_R3_RING_AK_USED.CCW_ODD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(8),
umask:
Tuple::One(8),
event_name:
"UNC_R3_RING_AK_USED.CCW_ODD",
brief_description:
"R3 AK Ring in Use; Counterclockwise and Odd",
public_description:
Some("Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop."),
counter:
Counter::Programmable(7),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_M_CAS_COUNT.WR_RMM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(4),
umask:
Tuple::One(8),
event_name:
"UNC_M_CAS_COUNT.WR_RMM",
brief_description:
"DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode",
public_description:
Some("DRAM RD_CAS and WR_CAS Commands"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_STALLS.BGF_HOM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(53),
umask:
Tuple::One(8),
event_name:
"UNC_Q_RxL_STALLS.BGF_HOM",
brief_description:
"Stalls Sending to R3QPI; BGF Stall - DRS",
public_description:
Some("Number of stalls trying to send to R3QPI."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_U_LOCK_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(68),
umask:
Tuple::One(0),
event_name:
"UNC_U_LOCK_CYCLES",
brief_description:
"IDI Lock/SplitLock Cycles",
public_description:
Some("Number of times an IDI Lock/SplitLock sequence was started"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("UBOX"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_INSERTS_NDR",
IntelPerformanceCounterDescription{event_code:
Tuple::One(14),
umask:
Tuple::One(0),
event_name:
"UNC_Q_RxL_INSERTS_NDR",
brief_description:
"Rx Flit Buffer Allocations - NDR",
public_description:
Some("Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NDR flits."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_Q_TxL_FLITS_G1.DRS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(0),
umask:
Tuple::One(24),
event_name:
"UNC_Q_TxL_FLITS_G1.DRS",
brief_description:
"Flits Transferred - Group 1; DRS Flits (both Header and Data)",
public_description:
Some("Counts the number of flits trasmitted across the QPI Link. This is one of three \'groups\' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each \'flit\' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four \'fits\', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI \'speed\' (for example, 8.0 GT/s), the \'transfers\' here refer to \'fits\'. Therefore, in L0, the system will transfer 1 \'flit\' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as \'data\' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual \'data\' and an additional 16 bits of other information. To calculate \'data\' bandwidth, one should therefore do: data flits * 8B / time."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_I_RxR_BL_NCS_CYCLES_FULL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(6),
umask:
Tuple::One(0),
event_name:
"UNC_I_RxR_BL_NCS_CYCLES_FULL",
brief_description:
"tbd",
public_description:
Some("Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_I_ADDRESS_MATCH.MERGE_COUNT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(23),
umask:
Tuple::One(2),
event_name:
"UNC_I_ADDRESS_MATCH.MERGE_COUNT",
brief_description:
"Address Match (Conflict) Count; Conflict Merges",
public_description:
Some("Counts the number of times when an inbound write (from a device to memory or another device) had an address match with another request in the write cache."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_I_RxR_BL_NCB_OCCUPANCY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(8),
umask:
Tuple::One(0),
event_name:
"UNC_I_RxR_BL_NCB_OCCUPANCY",
brief_description:
"tbd",
public_description:
Some("Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_R3_VN0_CREDITS_REJECT.NDR",
IntelPerformanceCounterDescription{event_code:
Tuple::One(55),
umask:
Tuple::One(4),
event_name:
"UNC_R3_VN0_CREDITS_REJECT.NDR",
brief_description:
"VN0 Credit Acquisition Failed on DRS; NDR Message Class",
public_description:
Some("Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_FLITS_G1.HOM_REQ",
IntelPerformanceCounterDescription{event_code:
Tuple::One(2),
umask:
Tuple::One(2),
event_name:
"UNC_Q_RxL_FLITS_G1.HOM_REQ",
brief_description:
"Flits Received - Group 1; HOM Request Flits",
public_description:
Some("Counts the number of flits received from the QPI Link. This is one of three \'groups\' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each \'flit\' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four \'fits\', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI \'speed\' (for example, 8.0 GT/s), the \'transfers\' here refer to \'fits\'. Therefore, in L0, the system will transfer 1 \'flit\' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as \'data\' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual \'data\' and an additional 16 bits of other information. To calculate \'data\' bandwidth, one should therefore do: data flits * 8B / time."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_R3_RxR_BYPASSED.AD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(18),
umask:
Tuple::One(1),
event_name:
"UNC_R3_RxR_BYPASSED.AD",
brief_description:
"Ingress Bypassed",
public_description:
Some("Counts the number of times when the Ingress was bypassed and an incoming transaction was bypassed directly across the BGF and into the qfclk domain."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_P_FREQ_BAND1_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(12),
umask:
Tuple::One(0),
event_name:
"UNC_P_FREQ_BAND1_CYCLES",
brief_description:
"Frequency Residency",
public_description:
Some("Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter. One can use all four counters with this event, so it is possible to track up to 4 configurable bands. One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
Some("PCUFilter[15:8]"),
extsel:
false,}),
("UNC_I_TxR_AD_STALL_CREDIT_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(24),
umask:
Tuple::One(0),
event_name:
"UNC_I_TxR_AD_STALL_CREDIT_CYCLES",
brief_description:
"No AD Egress Credit Stalls",
public_description:
Some("Counts the number times when it is not possible to issue a request to the R2PCIe because there are no AD Egress Credits available."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_BL_CYCLES_FULL.SCHED0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(54),
umask:
Tuple::One(1),
event_name:
"UNC_H_TxR_BL_CYCLES_FULL.SCHED0",
brief_description:
"BL Egress Full; Scheduler 0",
public_description:
Some("BL Egress Full"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_P_FREQ_MIN_IO_P_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(1),
umask:
Tuple::One(0),
event_name:
"UNC_P_FREQ_MIN_IO_P_CYCLES",
brief_description:
"IO P Limit Strongest Lower Limit Cycles",
public_description:
Some("Counts the number of cycles when IO P Limit is preventing us from dropping the frequency lower. This algorithm monitors the needs to the IO subsystem on both local and remote sockets and will maintain a frequency high enough to maintain good IO BW. This is necessary for when all the IA cores on a socket are idle but a user still would like to maintain high IO Bandwidth."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
true,}),
("UNC_U_EVENT_MSG.IPI_RCVD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(66),
umask:
Tuple::One(4),
event_name:
"UNC_U_EVENT_MSG.IPI_RCVD",
brief_description:
"VLW Received",
public_description:
Some("Virtual Logical Wire (legacy) message were received from Uncore. Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("UBOX"),
filter:
None,
extsel:
false,}),
("UNC_C_TOR_INSERTS.OPCODE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(53),
umask:
Tuple::One(1),
event_name:
"UNC_C_TOR_INSERTS.OPCODE",
brief_description:
"TOR Inserts; Opcode Match",
public_description:
Some("Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent \'filters\' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select \'MISS_OPC_MATCH\' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
Some("CBoFilter[31:23]"),
extsel:
false,}),
("UNC_P_CORE2_TRANSITION_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(5),
umask:
Tuple::One(0),
event_name:
"UNC_P_CORE2_TRANSITION_CYCLES",
brief_description:
"Core C State Transition Cycles",
public_description:
Some("Number of cycles spent performing core C state transitions. There is one event per core."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
true,}),
("UNC_R3_VN0_CREDITS_USED.NDR",
IntelPerformanceCounterDescription{event_code:
Tuple::One(54),
umask:
Tuple::One(4),
event_name:
"UNC_R3_VN0_CREDITS_USED.NDR",
brief_description:
"VN0 Credit Used; NDR Message Class",
public_description:
Some("Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_I_TxR_REQUEST_OCCUPANCY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(13),
umask:
Tuple::One(0),
event_name:
"UNC_I_TxR_REQUEST_OCCUPANCY",
brief_description:
"Outbound Request Queue Occupancy",
public_description:
Some("Accumultes the number of outstanding outbound requests from the IRP to the switch (towards the devices). This can be used in conjuection with the allocations event in order to calculate average latency of outbound requests."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_P_FREQ_TRANS_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(0),
umask:
Tuple::One(0),
event_name:
"UNC_P_FREQ_TRANS_CYCLES",
brief_description:
"Cycles spent changing Frequency",
public_description:
Some("Counts the number of cycles when the system is changing frequency. This can not be filtered by thread ID. One can also use it with the occupancy counter that monitors number of threads in C0 to estimate the performance impact that frequency transitions had on the system."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
true,}),
("UNC_C_TOR_INSERTS.NID_WB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(53),
umask:
Tuple::One(80),
event_name:
"UNC_C_TOR_INSERTS.NID_WB",
brief_description:
"TOR Inserts; NID Matched Writebacks",
public_description:
Some("Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent \'filters\' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select \'MISS_OPC_MATCH\' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
Some("CBoFilter[17:10]"),
extsel:
false,}),
("UNC_R3_VN0_CREDITS_USED.NCB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(54),
umask:
Tuple::One(16),
event_name:
"UNC_R3_VN0_CREDITS_USED.NCB",
brief_description:
"VN0 Credit Used; NCB Message Class",
public_description:
Some("Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_U_PHOLD_CYCLES.ACK_TO_DEASSERT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(69),
umask:
Tuple::One(2),
event_name:
"UNC_U_PHOLD_CYCLES.ACK_TO_DEASSERT",
brief_description:
"Cycles PHOLD Assert to Ack; ACK to Deassert",
public_description:
Some("PHOLD cycles. Filter from source CoreID."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("UBOX"),
filter:
None,
extsel:
true,}),
("UNC_U_FILTER_MATCH.U2C_DISABLE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(65),
umask:
Tuple::One(8),
event_name:
"UNC_U_FILTER_MATCH.U2C_DISABLE",
brief_description:
"Filter Match",
public_description:
Some("Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("UBOX"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_CRC_ERRORS.LINK_INIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(3),
umask:
Tuple::One(1),
event_name:
"UNC_Q_RxL_CRC_ERRORS.LINK_INIT",
brief_description:
"CRC Errors Detected; LinkInit",
public_description:
Some("Number of CRC errors detected in the QPI Agent. Each QPI flit incorporates 8 bits of CRC for error detection. This counts the number of flits where the CRC was able to detect an error. After an error has been detected, the QPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it)."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_STALLS.BGF_DRS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(53),
umask:
Tuple::One(1),
event_name:
"UNC_Q_RxL_STALLS.BGF_DRS",
brief_description:
"Stalls Sending to R3QPI; BGF Stall - HOM",
public_description:
Some("Number of stalls trying to send to R3QPI."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_C_LLC_VICTIMS.M_STATE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(55),
umask:
Tuple::One(1),
event_name:
"UNC_C_LLC_VICTIMS.M_STATE",
brief_description:
"Lines Victimized; Lines in M state",
public_description:
Some("Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_M_POWER_CRITICAL_THROTTLE_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(134),
umask:
Tuple::One(0),
event_name:
"UNC_M_POWER_CRITICAL_THROTTLE_CYCLES",
brief_description:
"Critical Throttle Cycles",
public_description:
Some("Counts the number of cycles when the iMC is in critical thermal throttling. When this happens, all traffic is blocked. This should be rare unless something bad is going on in the platform. There is no filtering by rank for this event."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxL_FLITS_G1.HOM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(0),
umask:
Tuple::One(6),
event_name:
"UNC_Q_TxL_FLITS_G1.HOM",
brief_description:
"Flits Transferred - Group 1; HOM Flits",
public_description:
Some("Counts the number of flits trasmitted across the QPI Link. This is one of three \'groups\' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each \'flit\' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four \'fits\', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI \'speed\' (for example, 8.0 GT/s), the \'transfers\' here refer to \'fits\'. Therefore, in L0, the system will transfer 1 \'flit\' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as \'data\' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual \'data\' and an additional 16 bits of other information. To calculate \'data\' bandwidth, one should therefore do: data flits * 8B / time."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_P_FREQ_MIN_PERF_P_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(2),
umask:
Tuple::One(0),
event_name:
"UNC_P_FREQ_MIN_PERF_P_CYCLES",
brief_description:
"Perf P Limit Strongest Lower Limit Cycles",
public_description:
Some("Counts the number of cycles when Perf P Limit is preventing us from dropping the frequency lower. Perf P Limit is an algorithm that takes input from remote sockets when determining if a socket should drop it\'s frequency down. This is largely to minimize increases in snoop and remote read latencies."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
true,}),
("UNC_Q_RxL_OCCUPANCY_HOM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(24),
umask:
Tuple::One(0),
event_name:
"UNC_Q_RxL_OCCUPANCY_HOM",
brief_description:
"RxQ Occupancy - HOM",
public_description:
Some("Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors HOM flits only."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_C_LLC_VICTIMS.MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(55),
umask:
Tuple::One(8),
event_name:
"UNC_C_LLC_VICTIMS.MISS",
brief_description:
"Lines Victimized",
public_description:
Some("Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_FLITS_G1.HOM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(2),
umask:
Tuple::One(6),
event_name:
"UNC_Q_RxL_FLITS_G1.HOM",
brief_description:
"Flits Received - Group 1; HOM Flits",
public_description:
Some("Counts the number of flits received from the QPI Link. This is one of three \'groups\' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each \'flit\' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four \'fits\', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI \'speed\' (for example, 8.0 GT/s), the \'transfers\' here refer to \'fits\'. Therefore, in L0, the system will transfer 1 \'flit\' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as \'data\' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual \'data\' and an additional 16 bits of other information. To calculate \'data\' bandwidth, one should therefore do: data flits * 8B / time."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_C_RING_IV_USED.ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(30),
umask:
Tuple::One(15),
event_name:
"UNC_C_RING_IV_USED.ANY",
brief_description:
"BL Ring in Use; Any",
public_description:
Some("Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring in JKT. Therefore, if one wants to monitor the \'Even\' ring, they should select both UP_EVEN and DN_EVEN. To monitor the \'Odd\' ring, they should select both UP_ODD and DN_ODD."),
counter:
Counter::Programmable(12),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_M_POWER_CKE_CYCLES.RANK4",
IntelPerformanceCounterDescription{event_code:
Tuple::One(131),
umask:
Tuple::One(16),
event_name:
"UNC_M_POWER_CKE_CYCLES.RANK4",
brief_description:
"CKE_ON_CYCLES by Rank; DIMM ID",
public_description:
Some("Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary)."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_OCCUPANCY_DRS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(21),
umask:
Tuple::One(0),
event_name:
"UNC_Q_RxL_OCCUPANCY_DRS",
brief_description:
"RxQ Occupancy - DRS",
public_description:
Some("Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors DRS flits only."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_C_RxR_IRQ_RETRY.ADDR_CONFLICT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(50),
umask:
Tuple::One(4),
event_name:
"UNC_C_RxR_IRQ_RETRY.ADDR_CONFLICT",
brief_description:
"Ingress Request Queue Rejects; Address Conflict",
public_description:
None,
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_C_MISC.STARTED",
IntelPerformanceCounterDescription{event_code:
Tuple::One(57),
umask:
Tuple::One(4),
event_name:
"UNC_C_MISC.STARTED",
brief_description:
"Cbo Misc",
public_description:
Some("Miscellaneous events in the Cbo."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_C_RxR_IRQ_RETRY.RTID",
IntelPerformanceCounterDescription{event_code:
Tuple::One(50),
umask:
Tuple::One(8),
event_name:
"UNC_C_RxR_IRQ_RETRY.RTID",
brief_description:
"Ingress Request Queue Rejects; No RTIDs",
public_description:
None,
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_C_RxR_INSERTS.IRQ",
IntelPerformanceCounterDescription{event_code:
Tuple::One(19),
umask:
Tuple::One(1),
event_name:
"UNC_C_RxR_INSERTS.IRQ",
brief_description:
"Ingress Allocations; IRQ",
public_description:
Some("Counts number of allocations per cycle into the specified Ingress queue."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_C_RxR_EXT_STARVED.IPQ",
IntelPerformanceCounterDescription{event_code:
Tuple::One(18),
umask:
Tuple::One(2),
event_name:
"UNC_C_RxR_EXT_STARVED.IPQ",
brief_description:
"Ingress Arbiter Blocking Cycles; IRQ",
public_description:
Some("Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_M_PREEMPTION.RD_PREEMPT_WR",
IntelPerformanceCounterDescription{event_code:
Tuple::One(8),
umask:
Tuple::One(2),
event_name:
"UNC_M_PREEMPTION.RD_PREEMPT_WR",
brief_description:
"Read Preemption Count; Read over Write Preemption",
public_description:
Some("Counts the number of times a read in the iMC preempts another read or write. Generally reads to an open page are issued ahead of requests to closed pages. This improves the page hit rate of the system. However, high priority requests can cause pages of active requests to be closed in order to get them out. This will reduce the latency of the high-priority request at the expense of lower bandwidth and increased overall average latency."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_INSERTS_SNP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(13),
umask:
Tuple::One(0),
event_name:
"UNC_Q_RxL_INSERTS_SNP",
brief_description:
"Rx Flit Buffer Allocations - SNP",
public_description:
Some("Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only SNP flits."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_H_TxR_BL.DRS_CACHE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(16),
umask:
Tuple::One(1),
event_name:
"UNC_H_TxR_BL.DRS_CACHE",
brief_description:
"Outbound DRS Ring Transactions to Cache; Data to Cache",
public_description:
Some("Counts the number of DRS messages sent out on the BL ring. This can be filtered by the destination."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_U_EVENT_MSG.MSI_RCVD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(66),
umask:
Tuple::One(2),
event_name:
"UNC_U_EVENT_MSG.MSI_RCVD",
brief_description:
"VLW Received",
public_description:
Some("Virtual Logical Wire (legacy) message were received from Uncore. Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("UBOX"),
filter:
None,
extsel:
false,}),
("UNC_H_DIRECTORY_LOOKUP.SNP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(12),
umask:
Tuple::One(1),
event_name:
"UNC_H_DIRECTORY_LOOKUP.SNP",
brief_description:
"Directory Lookups; Snoop Needed",
public_description:
Some("Counts the number of transactions that looked up the directory. Can be filtered by requests that had to snoop and those that did not have to."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_MAJOR_MODES.ISOCH",
IntelPerformanceCounterDescription{event_code:
Tuple::One(7),
umask:
Tuple::One(8),
event_name:
"UNC_M_MAJOR_MODES.ISOCH",
brief_description:
"Cycles in a Major Mode; Isoch Major Mode",
public_description:
Some("Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_H_RING_BL_USED.CCW_EVEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(64),
umask:
Tuple::One(4),
event_name:
"UNC_H_RING_BL_USED.CCW_EVEN",
brief_description:
"HA BL Ring in Use; Counterclockwise and Even",
public_description:
Some("Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_TAD_REQUESTS_G0.REGION0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(27),
umask:
Tuple::One(1),
event_name:
"UNC_H_TAD_REQUESTS_G0.REGION0",
brief_description:
"HA Requests to a TAD Region - Group 0; TAD Region 0",
public_description:
Some("Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for \'Monroe\' systems that use the TAD to enable individual channels to enter self-refresh to save power."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxL_FLITS_G1.SNP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(0),
umask:
Tuple::One(1),
event_name:
"UNC_Q_TxL_FLITS_G1.SNP",
brief_description:
"Flits Transferred - Group 1; SNP Flits",
public_description:
Some("Counts the number of flits trasmitted across the QPI Link. This is one of three \'groups\' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each \'flit\' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four \'fits\', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI \'speed\' (for example, 8.0 GT/s), the \'transfers\' here refer to \'fits\'. Therefore, in L0, the system will transfer 1 \'flit\' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as \'data\' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual \'data\' and an additional 16 bits of other information. To calculate \'data\' bandwidth, one should therefore do: data flits * 8B / time."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_R3_RING_BL_USED.CW_EVEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(9),
umask:
Tuple::One(1),
event_name:
"UNC_R3_RING_BL_USED.CW_EVEN",
brief_description:
"R3 BL Ring in Use; Clockwise and Even",
public_description:
Some("Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop."),
counter:
Counter::Programmable(7),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_C_RxR_EXT_STARVED.ISMQ",
IntelPerformanceCounterDescription{event_code:
Tuple::One(18),
umask:
Tuple::One(4),
event_name:
"UNC_C_RxR_EXT_STARVED.ISMQ",
brief_description:
"Ingress Arbiter Blocking Cycles; ISMQ",
public_description:
Some("Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN2",
IntelPerformanceCounterDescription{event_code:
Tuple::One(21),
umask:
Tuple::One(4),
event_name:
"UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN2",
brief_description:
"iMC RPQ Credits Empty - Regular; Channel 2",
public_description:
Some("Counts the number of cycles when there are no \'regular\' credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC\'s RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and \'special\' requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_TRACKER_INSERTS.ALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(6),
umask:
Tuple::One(3),
event_name:
"UNC_H_TRACKER_INSERTS.ALL",
brief_description:
"Tracker Allocations; All Requests",
public_description:
Some("Counts the number of allocations into the local HA tracker pool. This can be used in conjunction with the occupancy accumulation event in order to calculate average latency. One cannot filter between reads and writes. HA trackers are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_CREDITS_CONSUMED_VN0.HOM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(30),
umask:
Tuple::One(8),
event_name:
"UNC_Q_RxL_CREDITS_CONSUMED_VN0.HOM",
brief_description:
"VN0 Credit Consumed; HOM",
public_description:
Some("Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_Q_RxL_INSERTS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(8),
umask:
Tuple::One(0),
event_name:
"UNC_Q_RxL_INSERTS",
brief_description:
"Rx Flit Buffer Allocations",
public_description:
Some("Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_R3_RING_BL_USED.CCW_ODD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(9),
umask:
Tuple::One(8),
event_name:
"UNC_R3_RING_BL_USED.CCW_ODD",
brief_description:
"R3 BL Ring in Use; Counterclockwise and Odd",
public_description:
Some("Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop."),
counter:
Counter::Programmable(7),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_I_CACHE_ACK_PENDING_OCCUPANCY.ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(20),
umask:
Tuple::One(1),
event_name:
"UNC_I_CACHE_ACK_PENDING_OCCUPANCY.ANY",
brief_description:
"Write Ack Pending Occupancy; Any Source",
public_description:
Some("Accumulates the number of writes that have acquired ownership but have not yet returned their data to the uncore. These writes are generally queued up in the switch trying to get to the head of their queues so that they can post their data. The queue occuapancy increments when the ACK is received, and decrements when either the data is returned OR a tickle is received and ownership is released. Note that a single tickle can result in multiple decrements."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_I_RxR_AK_INSERTS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(10),
umask:
Tuple::One(0),
event_name:
"UNC_I_RxR_AK_INSERTS",
brief_description:
"AK Ingress Occupancy",
public_description:
Some("Counts the number of allocations into the AK Ingress. This queue is where the IRP receives responses from R2PCIe (the ring)."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_OCCUPANCY_SNP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(25),
umask:
Tuple::One(0),
event_name:
"UNC_Q_RxL_OCCUPANCY_SNP",
brief_description:
"RxQ Occupancy - SNP",
public_description:
Some("Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors SNP flits only."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_I_TICKLES.LOST_OWNERSHIP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(22),
umask:
Tuple::One(1),
event_name:
"UNC_I_TICKLES.LOST_OWNERSHIP",
brief_description:
"Tickle Count; Ownership Lost",
public_description:
Some("Counts the number of tickles that are received. This is for both explicit (from Cbo) and implicit (internal conflict) tickles."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_AD_CYCLES_FULL.SCHED1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(42),
umask:
Tuple::One(2),
event_name:
"UNC_H_TxR_AD_CYCLES_FULL.SCHED1",
brief_description:
"AD Egress Full; Scheduler 1",
public_description:
Some("AD Egress Full"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxL_CYCLES_NE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(6),
umask:
Tuple::One(0),
event_name:
"UNC_Q_TxL_CYCLES_NE",
brief_description:
"Tx Flit Buffer Cycles not Empty",
public_description:
Some("Counts the number of cycles when the TxQ is not empty. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_R3_RxR_INSERTS.HOM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(17),
umask:
Tuple::One(1),
event_name:
"UNC_R3_RxR_INSERTS.HOM",
brief_description:
"Ingress Allocations; HOM",
public_description:
Some("Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxL_CRC_NO_CREDITS.FULL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(2),
umask:
Tuple::One(1),
event_name:
"UNC_Q_TxL_CRC_NO_CREDITS.FULL",
brief_description:
"Cycles Stalled with no LLR Credits; LLR is full",
public_description:
Some("Number of cycles when the Tx side ran out of Link Layer Retry credits, causing the Tx to stall."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_H_TAD_REQUESTS_G1.REGION11",
IntelPerformanceCounterDescription{event_code:
Tuple::One(28),
umask:
Tuple::One(8),
event_name:
"UNC_H_TAD_REQUESTS_G1.REGION11",
brief_description:
"HA Requests to a TAD Region - Group 1; TAD Region 11",
public_description:
Some("Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 8 to 10. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for \'Monroe\' systems that use the TAD to enable individual channels to enter self-refresh to save power."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_I_RxR_BL_DRS_OCCUPANCY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(7),
umask:
Tuple::One(0),
event_name:
"UNC_I_RxR_BL_DRS_OCCUPANCY",
brief_description:
"tbd",
public_description:
Some("Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_C_TxR_INSERTS.AD_CACHE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(2),
umask:
Tuple::One(1),
event_name:
"UNC_C_TxR_INSERTS.AD_CACHE",
brief_description:
"Egress Allocations; AD - Cachebo",
public_description:
Some("Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_AD.SNP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(15),
umask:
Tuple::One(2),
event_name:
"UNC_H_TxR_AD.SNP",
brief_description:
"Outbound NDR Ring Transactions; Snoops",
public_description:
Some("Counts the number of outbound transactions on the AD ring. This can be filtered by the NDR and SNP message classes. See the filter descriptions for more details."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_C_RING_BOUNCES.BL_CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(5),
umask:
Tuple::One(4),
event_name:
"UNC_C_RING_BOUNCES.BL_CORE",
brief_description:
"Number of LLC responses that bounced on the Ring.; Data Responses to core",
public_description:
None,
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_AD_OCCUPANCY.SCHED0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(40),
umask:
Tuple::One(1),
event_name:
"UNC_H_TxR_AD_OCCUPANCY.SCHED0",
brief_description:
"AD Egress Occupancy; Scheduler 0",
public_description:
Some("AD Egress Occupancy"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_R3_VN0_CREDITS_USED.NCS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(54),
umask:
Tuple::One(32),
event_name:
"UNC_R3_VN0_CREDITS_USED.NCS",
brief_description:
"VN0 Credit Used; NCS Message Class",
public_description:
Some("Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_C_LLC_LOOKUP.REMOTE_SNOOP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(52),
umask:
Tuple::One(9),
event_name:
"UNC_C_LLC_LOOKUP.REMOTE_SNOOP",
brief_description:
"Cache Lookups; External Snoop Request",
public_description:
Some("Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set filter mask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
Some("CBoFilter[22:18]"),
extsel:
false,}),
("UNC_C_RxR_IRQ_RETRY.ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(50),
umask:
Tuple::One(1),
event_name:
"UNC_C_RxR_IRQ_RETRY.ANY",
brief_description:
"Ingress Request Queue Rejects; Any Reject",
public_description:
None,
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_R3_RxR_CYCLES_NE.NCB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(16),
umask:
Tuple::One(16),
event_name:
"UNC_R3_RxR_CYCLES_NE.NCB",
brief_description:
"Ingress Cycles Not Empty; NCB",
public_description:
Some("Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN3",
IntelPerformanceCounterDescription{event_code:
Tuple::One(21),
umask:
Tuple::One(8),
event_name:
"UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN3",
brief_description:
"iMC RPQ Credits Empty - Regular; Channel 3",
public_description:
Some("Counts the number of cycles when there are no \'regular\' credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC\'s RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and \'special\' requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_R3_RxR_OCCUPANCY.NCS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(19),
umask:
Tuple::One(32),
event_name:
"UNC_R3_RxR_OCCUPANCY.NCS",
brief_description:
"Ingress Occupancy Accumulator; NCS",
public_description:
Some("Accumulates the occupancy of a given QPI Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency."),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_AK_CYCLES_NE.SCHED1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(49),
umask:
Tuple::One(2),
event_name:
"UNC_H_TxR_AK_CYCLES_NE.SCHED1",
brief_description:
"AK Egress Not Empty; Scheduler 1",
public_description:
Some("AK Egress Not Empty"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_R2_IIO_CREDITS_USED.NCB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(50),
umask:
Tuple::One(16),
event_name:
"UNC_R2_IIO_CREDITS_USED.NCB",
brief_description:
"R2PCIe IIO Credits in Use; NCB",
public_description:
Some("Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly)."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_C_TxR_STARVED.BL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(3),
umask:
Tuple::One(4),
event_name:
"UNC_C_TxR_STARVED.BL",
brief_description:
"Injection Starvation; Onto BL Ring",
public_description:
Some("Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_BL_OCCUPANCY.ALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(52),
umask:
Tuple::One(3),
event_name:
"UNC_H_TxR_BL_OCCUPANCY.ALL",
brief_description:
"BL Egress Occupancy; All",
public_description:
Some("BL Egress Occupancy"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_C_TOR_INSERTS.NID_MISS_ALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(53),
umask:
Tuple::One(74),
event_name:
"UNC_C_TOR_INSERTS.NID_MISS_ALL",
brief_description:
"TOR Inserts; NID Matched Miss All",
public_description:
Some("Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent \'filters\' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select \'MISS_OPC_MATCH\' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
Some("CBoFilter[17:10]"),
extsel:
false,}),
("UNC_M_WPQ_CYCLES_NE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(33),
umask:
Tuple::One(0),
event_name:
"UNC_M_WPQ_CYCLES_NE",
brief_description:
"Write Pending Queue Not Empty",
public_description:
Some("Counts the number of cycles that the Write Pending Queue is not empty. This can then be used to calculate the average queue occupancy (in conjunction with the WPQ Occupancy Accumulation count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have \'posted\' to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_WPQ_WRITE_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(36),
umask:
Tuple::One(0),
event_name:
"UNC_M_WPQ_WRITE_HIT",
brief_description:
"Write Pending Queue CAM Match",
public_description:
Some("Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_P_CORE1_TRANSITION_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(4),
umask:
Tuple::One(0),
event_name:
"UNC_P_CORE1_TRANSITION_CYCLES",
brief_description:
"Core C State Transition Cycles",
public_description:
Some("Number of cycles spent performing core C state transitions. There is one event per core."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
true,}),
("UNC_Q_TxL_FLITS_G0.DATA",
IntelPerformanceCounterDescription{event_code:
Tuple::One(0),
umask:
Tuple::One(2),
event_name:
"UNC_Q_TxL_FLITS_G0.DATA",
brief_description:
"Flits Transferred - Group 0; Data Tx Flits",
public_description:
Some("Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each \'flit\' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four \'fits\', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI \'speed\' (for example, 8.0 GT/s), the \'transfers\' here refer to \'fits\'. Therefore, in L0, the system will transfer 1 \'flit\' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as \'data\' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual \'data\' and an additional 16 bits of other information. To calculate \'data\' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_U_EVENT_MSG.VLW_RCVD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(66),
umask:
Tuple::One(1),
event_name:
"UNC_U_EVENT_MSG.VLW_RCVD",
brief_description:
"VLW Received",
public_description:
Some("Virtual Logical Wire (legacy) message were received from Uncore. Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("UBOX"),
filter:
None,
extsel:
false,}),
("UNC_U_FILTER_MATCH.ENABLE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(65),
umask:
Tuple::One(1),
event_name:
"UNC_U_FILTER_MATCH.ENABLE",
brief_description:
"Filter Match",
public_description:
Some("Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("UBOX"),
filter:
Some("UBoxFilter[3:0]"),
extsel:
false,}),
("UNC_Q_TxL_BYPASSED",
IntelPerformanceCounterDescription{event_code:
Tuple::One(5),
umask:
Tuple::One(0),
event_name:
"UNC_Q_TxL_BYPASSED",
brief_description:
"Tx Flit Buffer Bypassed",
public_description:
Some("Counts the number of times that an incoming flit was able to bypass the Tx flit buffer and pass directly out the QPI Link. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_M_POWER_CKE_CYCLES.RANK6",
IntelPerformanceCounterDescription{event_code:
Tuple::One(131),
umask:
Tuple::One(64),
event_name:
"UNC_M_POWER_CKE_CYCLES.RANK6",
brief_description:
"CKE_ON_CYCLES by Rank; DIMM ID",
public_description:
Some("Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary)."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_R3_VN0_CREDITS_USED.DRS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(54),
umask:
Tuple::One(8),
event_name:
"UNC_R3_VN0_CREDITS_USED.DRS",
brief_description:
"VN0 Credit Used; DRS Message Class",
public_description:
Some("Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_C_MISC.RFO_HIT_S",
IntelPerformanceCounterDescription{event_code:
Tuple::One(57),
umask:
Tuple::One(8),
event_name:
"UNC_C_MISC.RFO_HIT_S",
brief_description:
"Cbo Misc; RFO HitS",
public_description:
Some("Miscellaneous events in the Cbo."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_BL_INSERTS.ALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(51),
umask:
Tuple::One(3),
event_name:
"UNC_H_TxR_BL_INSERTS.ALL",
brief_description:
"BL Egress Allocations; All",
public_description:
Some("BL Egress Allocations"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_R2_TxR_CYCLES_NE.BL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(35),
umask:
Tuple::One(4),
event_name:
"UNC_R2_TxR_CYCLES_NE.BL",
brief_description:
"Egress Cycles Not Empty; BL",
public_description:
Some("Counts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity."),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_M_DRAM_PRE_ALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(6),
umask:
Tuple::One(0),
event_name:
"UNC_M_DRAM_PRE_ALL",
brief_description:
"DRAM Precharge All Commands",
public_description:
Some("Counts the number of times that the precharge all command was sent."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_U_FILTER_MATCH.DISABLE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(65),
umask:
Tuple::One(2),
event_name:
"UNC_U_FILTER_MATCH.DISABLE",
brief_description:
"Filter Match",
public_description:
Some("Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("UBOX"),
filter:
None,
extsel:
false,}),
("UNC_P_CORE6_TRANSITION_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(9),
umask:
Tuple::One(0),
event_name:
"UNC_P_CORE6_TRANSITION_CYCLES",
brief_description:
"Core C State Transition Cycles",
public_description:
Some("Number of cycles spent performing core C state transitions. There is one event per core."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
true,}),
("UNC_M_POWER_CKE_CYCLES.RANK2",
IntelPerformanceCounterDescription{event_code:
Tuple::One(131),
umask:
Tuple::One(4),
event_name:
"UNC_M_POWER_CKE_CYCLES.RANK2",
brief_description:
"CKE_ON_CYCLES by Rank; DIMM ID",
public_description:
Some("Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary)."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_H_REQUESTS.READS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(1),
umask:
Tuple::One(3),
event_name:
"UNC_H_REQUESTS.READS",
brief_description:
"Read and Write Requests; Reads",
public_description:
Some("Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc)."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_R3_RxR_CYCLES_NE.SNP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(16),
umask:
Tuple::One(2),
event_name:
"UNC_R3_RxR_CYCLES_NE.SNP",
brief_description:
"Ingress Cycles Not Empty; SNP",
public_description:
Some("Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxL_FLITS_G2.NCB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(1),
umask:
Tuple::One(12),
event_name:
"UNC_Q_TxL_FLITS_G2.NCB",
brief_description:
"Flits Transferred - Group 2; Non-Coherent Bypass Tx Flits",
public_description:
Some("Counts the number of flits trasmitted across the QPI Link. This is one of three \'groups\' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each \'flit\' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four \'fits\', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI \'speed\' (for example, 8.0 GT/s), the \'transfers\' here refer to \'fits\'. Therefore, in L0, the system will transfer 1 \'flit\' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as \'data\' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual \'data\' and an additional 16 bits of other information. To calculate \'data\' bandwidth, one should therefore do: data flits * 8B / time."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_C_RING_SRC_THRTL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(7),
umask:
Tuple::One(0),
event_name:
"UNC_C_RING_SRC_THRTL",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_R3_VNA_CREDIT_CYCLES_OUT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(49),
umask:
Tuple::One(0),
event_name:
"UNC_R3_VNA_CREDIT_CYCLES_OUT",
brief_description:
"Cycles with no VNA credits available",
public_description:
Some("Number of QPI uclk cycles when the transmitted has no VNA credits available and therefore cannot send any requests on this channel. Note that this does not mean that no flits can be transmitted, as those holding VN0 credits will still (potentially) be able to transmit. Generally it is the goal of the uncore that VNA credits should not run out, as this can substantially throttle back useful QPI bandwidth."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_R3_RING_AD_USED.CCW_EVEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(7),
umask:
Tuple::One(4),
event_name:
"UNC_R3_RING_AD_USED.CCW_EVEN",
brief_description:
"R3 AD Ring in Use; Counterclockwise and Even",
public_description:
Some("Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop."),
counter:
Counter::Programmable(7),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_P_POWER_STATE_OCCUPANCY.CORES_C3",
IntelPerformanceCounterDescription{event_code:
Tuple::One(128),
umask:
Tuple::One(128),
event_name:
"UNC_P_POWER_STATE_OCCUPANCY.CORES_C3",
brief_description:
"Number of cores in C0",
public_description:
Some("This is an occupancy event that tracks the number of cores that are in C0. It can be used by itself to get the average number of cores in C0, with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(19),
umask:
Tuple::One(8),
event_name:
"UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT",
brief_description:
"Direct 2 Core Spawning; Spawn Failure - Egress and RBT",
public_description:
Some("Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exlusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_I_TRANSACTIONS.READS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(21),
umask:
Tuple::One(1),
event_name:
"UNC_I_TRANSACTIONS.READS",
brief_description:
"Inbound Transaction Count; Reads",
public_description:
Some("Counts the number of \'Inbound\' transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_R3_VNA_CREDITS_REJECT.NCB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(52),
umask:
Tuple::One(16),
event_name:
"UNC_R3_VNA_CREDITS_REJECT.NCB",
brief_description:
"VNA Credit Reject; NCB Message Class",
public_description:
Some("Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_H_RING_AD_USED.CCW_EVEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(62),
umask:
Tuple::One(4),
event_name:
"UNC_H_RING_AD_USED.CCW_EVEN",
brief_description:
"HA AD Ring in Use; Counterclockwise and Even",
public_description:
Some("Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_RING_AK_USED.CCW_EVEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(63),
umask:
Tuple::One(4),
event_name:
"UNC_H_RING_AK_USED.CCW_EVEN",
brief_description:
"HA AK Ring in Use; Counterclockwise and Even",
public_description:
Some("Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxL0_POWER_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(12),
umask:
Tuple::One(0),
event_name:
"UNC_Q_TxL0_POWER_CYCLES",
brief_description:
"Cycles in L0",
public_description:
Some("Number of QPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxL_FLITS_G1.DRS_NONDATA",
IntelPerformanceCounterDescription{event_code:
Tuple::One(0),
umask:
Tuple::One(16),
event_name:
"UNC_Q_TxL_FLITS_G1.DRS_NONDATA",
brief_description:
"Flits Transferred - Group 1; DRS Header Flits",
public_description:
Some("Counts the number of flits trasmitted across the QPI Link. This is one of three \'groups\' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each \'flit\' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four \'fits\', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI \'speed\' (for example, 8.0 GT/s), the \'transfers\' here refer to \'fits\'. Therefore, in L0, the system will transfer 1 \'flit\' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as \'data\' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual \'data\' and an additional 16 bits of other information. To calculate \'data\' bandwidth, one should therefore do: data flits * 8B / time."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_H_TAD_REQUESTS_G1.REGION10",
IntelPerformanceCounterDescription{event_code:
Tuple::One(28),
umask:
Tuple::One(4),
event_name:
"UNC_H_TAD_REQUESTS_G1.REGION10",
brief_description:
"HA Requests to a TAD Region - Group 1; TAD Region 10",
public_description:
Some("Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 8 to 10. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for \'Monroe\' systems that use the TAD to enable individual channels to enter self-refresh to save power."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_P_TOTAL_TRANSITION_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(11),
umask:
Tuple::One(0),
event_name:
"UNC_P_TOTAL_TRANSITION_CYCLES",
brief_description:
"Total Core C State Transition Cycles",
public_description:
Some("Number of cycles spent performing core C state transitions across all cores."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
true,}),
("UNC_H_TxR_BL_OCCUPANCY.SCHED0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(52),
umask:
Tuple::One(1),
event_name:
"UNC_H_TxR_BL_OCCUPANCY.SCHED0",
brief_description:
"BL Egress Occupancy; Scheduler 0",
public_description:
Some("BL Egress Occupancy"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_RING_AK_USED.CW_EVEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(63),
umask:
Tuple::One(1),
event_name:
"UNC_H_RING_AK_USED.CW_EVEN",
brief_description:
"HA AK Ring in Use; Clockwise and Even",
public_description:
Some("Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_R3_IIO_CREDITS_REJECT.DRS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(33),
umask:
Tuple::One(8),
event_name:
"UNC_R3_IIO_CREDITS_REJECT.DRS",
brief_description:
"to IIO BL Credit Rejected",
public_description:
Some("Counts the number of times that a request attempted to acquire an NCS/NCB/DRS credit in the QPI for sending messages on BL to the IIO but was rejected because no credit was available. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transfering data without coherency, and DRS is used for transfering data with coherency (cachable PCI transactions). This event can only track one message class at a time."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxL_FLITS_G2.NDR_AD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(1),
umask:
Tuple::One(1),
event_name:
"UNC_Q_TxL_FLITS_G2.NDR_AD",
brief_description:
"Flits Transferred - Group 2; Non-Data Response Tx Flits - AD",
public_description:
Some("Counts the number of flits trasmitted across the QPI Link. This is one of three \'groups\' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each \'flit\' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four \'fits\', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI \'speed\' (for example, 8.0 GT/s), the \'transfers\' here refer to \'fits\'. Therefore, in L0, the system will transfer 1 \'flit\' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as \'data\' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual \'data\' and an additional 16 bits of other information. To calculate \'data\' bandwidth, one should therefore do: data flits * 8B / time."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_P_DEMOTIONS_CORE6",
IntelPerformanceCounterDescription{event_code:
Tuple::One(36),
umask:
Tuple::One(0),
event_name:
"UNC_P_DEMOTIONS_CORE6",
brief_description:
"Core C State Demotions",
public_description:
Some("Counts the number of times when a configurable cores had a C-state demotion"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
Some("PCUFilter[7:0]"),
extsel:
false,}),
("UNC_C_RxR_ISMQ_RETRY.IIO_CREDITS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(51),
umask:
Tuple::One(32),
event_name:
"UNC_C_RxR_ISMQ_RETRY.IIO_CREDITS",
brief_description:
"ISMQ Retries; No IIO Credits",
public_description:
Some("Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_FLITS_G2.NCB_DATA",
IntelPerformanceCounterDescription{event_code:
Tuple::One(3),
umask:
Tuple::One(4),
event_name:
"UNC_Q_RxL_FLITS_G2.NCB_DATA",
brief_description:
"Flits Received - Group 2; Non-Coherent data Rx Flits",
public_description:
Some("Counts the number of flits received from the QPI Link. This is one of three \'groups\' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each \'flit\' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four \'fits\', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI \'speed\' (for example, 8.0 GT/s), the \'transfers\' here refer to \'fits\'. Therefore, in L0, the system will transfer 1 \'flit\' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as \'data\' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual \'data\' and an additional 16 bits of other information. To calculate \'data\' bandwidth, one should therefore do: data flits * 8B / time."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(34),
umask:
Tuple::One(4),
event_name:
"UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI0",
brief_description:
"Cycles without QPI Ingress Credits; BL to QPI Link 0",
public_description:
Some("Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent. This can be filtered by the different credit pools and the different links."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(22),
umask:
Tuple::One(2),
event_name:
"UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN1",
brief_description:
"iMC RPQ Credits Empty - Special; Channel 1",
public_description:
Some("Counts the number of cycles when there are no \'special\' credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC\'s RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and \'special\' requests such as ISOCH reads. This count only tracks the \'special\' credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(34),
umask:
Tuple::One(8),
event_name:
"UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI1",
brief_description:
"Cycles without QPI Ingress Credits; BL to QPI Link 1",
public_description:
Some("Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent. This can be filtered by the different credit pools and the different links."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_C_RxR_IPQ_RETRY.ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(49),
umask:
Tuple::One(1),
event_name:
"UNC_C_RxR_IPQ_RETRY.ANY",
brief_description:
"Probe Queue Retries; Any Reject",
public_description:
Some("Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_C_TxR_INSERTS.BL_CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(2),
umask:
Tuple::One(64),
event_name:
"UNC_C_TxR_INSERTS.BL_CORE",
brief_description:
"Egress Allocations; BL - Corebo",
public_description:
Some("Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxL_FLITS_G0.NON_DATA",
IntelPerformanceCounterDescription{event_code:
Tuple::One(0),
umask:
Tuple::One(4),
event_name:
"UNC_Q_TxL_FLITS_G0.NON_DATA",
brief_description:
"Flits Transferred - Group 0; Non-Data protocol Tx Flits",
public_description:
Some("Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each \'flit\' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four \'fits\', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI \'speed\' (for example, 8.0 GT/s), the \'transfers\' here refer to \'fits\'. Therefore, in L0, the system will transfer 1 \'flit\' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as \'data\' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual \'data\' and an additional 16 bits of other information. To calculate \'data\' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,})]),}