pub const IVYBRIDGE_CORE: Map<&'static str, IntelPerformanceCounterDescription> = ::phf::Map{key: 1897749892740154578,
disps:
::phf::Slice::Static(&[(0, 123), (0, 131), (0, 8), (0, 108),
(0, 5), (1, 287), (0, 182), (0, 100),
(0, 13), (0, 5), (0, 17), (0, 191),
(6, 89), (0, 8), (4, 220), (0, 2),
(0, 0), (0, 240), (0, 216), (0, 1),
(0, 0), (0, 205), (1, 270), (0, 116),
(1, 62), (0, 17), (0, 32), (0, 3),
(0, 84), (0, 79), (0, 44), (0, 204),
(0, 0), (4, 238), (15, 35), (4, 8),
(2, 263), (0, 306), (8, 6), (30, 135),
(0, 1), (0, 23), (0, 16), (0, 46),
(1, 24), (0, 0), (11, 178), (0, 0),
(6, 79), (0, 2), (4, 172), (0, 85),
(0, 29), (8, 54), (19, 141), (0, 0),
(6, 269), (0, 2), (0, 229), (1, 234),
(0, 82), (2, 249), (52, 0)]),
entries:
::phf::Slice::Static(&[("UOPS_EXECUTED.CORE_CYCLES_GE_2",
IntelPerformanceCounterDescription{event_code:
Tuple::One(177),
umask:
Tuple::One(2),
event_name:
"UOPS_EXECUTED.CORE_CYCLES_GE_2",
brief_description:
"Cycles at least 2 micro-op is executed from any thread on physical core",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
2,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_RQSTS.ALL_RFO",
IntelPerformanceCounterDescription{event_code:
Tuple::One(36),
umask:
Tuple::One(12),
event_name:
"L2_RQSTS.ALL_RFO",
brief_description:
"RFO requests to L2 cache",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(156),
umask:
Tuple::One(1),
event_name:
"IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",
brief_description:
"Cycles with less than 3 uops delivered by the front end.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("CPL_CYCLES.RING0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(92),
umask:
Tuple::One(1),
event_name:
"CPL_CYCLES.RING0",
brief_description:
"Unhalted core cycles when the thread is in ring 0",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("SIMD_FP_256.PACKED_DOUBLE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(17),
umask:
Tuple::One(2),
event_name:
"SIMD_FP_256.PACKED_DOUBLE",
brief_description:
"number of AVX-256 Computational FP double precision uops issued this cycle",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_LOAD_UOPS_RETIRED.L2_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(209),
umask:
Tuple::One(2),
event_name:
"MEM_LOAD_UOPS_RETIRED.L2_HIT",
brief_description:
"Retired load uops with L2 cache hits as data sources.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_RQSTS.PF_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(36),
umask:
Tuple::One(128),
event_name:
"L2_RQSTS.PF_MISS",
brief_description:
"Requests from the L2 hardware prefetchers that miss L2 cache",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("INT_MISC.RECOVERY_CYCLES_ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(13),
umask:
Tuple::One(3),
event_name:
"INT_MISC.RECOVERY_CYCLES_ANY",
brief_description:
"Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
false,
any_thread:
true,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_TRANS.L2_WB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(240),
umask:
Tuple::One(64),
event_name:
"L2_TRANS.L2_WB",
brief_description:
"L2 writebacks that access L2 cache",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6",
IntelPerformanceCounterDescription{event_code:
Tuple::One(96),
umask:
Tuple::One(1),
event_name:
"OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6",
brief_description:
"Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
6,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(156),
umask:
Tuple::One(1),
event_name:
"IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
brief_description:
"Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
4,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("CYCLE_ACTIVITY.CYCLES_MEM_ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(163),
umask:
Tuple::One(2),
event_name:
"CYCLE_ACTIVITY.CYCLES_MEM_ANY",
brief_description:
"Cycles while memory subsystem has an outstanding load.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
2,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(137),
umask:
Tuple::One(160),
event_name:
"BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL",
brief_description:
"Taken speculative and retired mispredicted indirect calls",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("LOAD_HIT_PRE.SW_PF",
IntelPerformanceCounterDescription{event_code:
Tuple::One(76),
umask:
Tuple::One(1),
event_name:
"LOAD_HIT_PRE.SW_PF",
brief_description:
"Not software-prefetch load dispatches that hit FB allocated for software prefetch",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("IDQ.MITE_UOPS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(121),
umask:
Tuple::One(4),
event_name:
"IDQ.MITE_UOPS",
brief_description:
"Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_TRANS.L1D_WB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(240),
umask:
Tuple::One(16),
event_name:
"L2_TRANS.L1D_WB",
brief_description:
"L1D writebacks that access L2 cache",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L1D_PEND_MISS.PENDING_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(72),
umask:
Tuple::One(1),
event_name:
"L1D_PEND_MISS.PENDING_CYCLES",
brief_description:
"Cycles with L1D load Misses outstanding.",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Programmable(4),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("CPL_CYCLES.RING0_TRANS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(92),
umask:
Tuple::One(1),
event_name:
"CPL_CYCLES.RING0_TRANS",
brief_description:
"Number of intervals between processor halts while thread is in ring 0",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100007,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
false,
any_thread:
false,
edge_detect:
true,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_MISP_EXEC.ALL_BRANCHES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(137),
umask:
Tuple::One(255),
event_name:
"BR_MISP_EXEC.ALL_BRANCHES",
brief_description:
"Speculative and retired mispredicted macro conditional branches",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("RS_EVENTS.EMPTY_END",
IntelPerformanceCounterDescription{event_code:
Tuple::One(94),
umask:
Tuple::One(1),
event_name:
"RS_EVENTS.EMPTY_END",
brief_description:
"Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
true,
any_thread:
false,
edge_detect:
true,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_REQUESTS.ALL_DATA_RD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(176),
umask:
Tuple::One(8),
event_name:
"OFFCORE_REQUESTS.ALL_DATA_RD",
brief_description:
"Demand and prefetch data reads",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_DISPATCHED_PORT.PORT_2_CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(161),
umask:
Tuple::One(12),
event_name:
"UOPS_DISPATCHED_PORT.PORT_2_CORE",
brief_description:
"Uops dispatched to port 2, loads and stores per core (speculative and retired)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
true,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_ISSUED.FLAGS_MERGE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(14),
umask:
Tuple::One(16),
event_name:
"UOPS_ISSUED.FLAGS_MERGE",
brief_description:
"Number of flags-merge uops being allocated.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_RQSTS.PF_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(36),
umask:
Tuple::One(64),
event_name:
"L2_RQSTS.PF_HIT",
brief_description:
"Requests from the L2 hardware prefetchers that hit L2 cache",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
IntelPerformanceCounterDescription{event_code:
Tuple::One(96),
umask:
Tuple::One(4),
event_name:
"OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
brief_description:
"Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_TRANS.ALL_REQUESTS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(240),
umask:
Tuple::One(128),
event_name:
"L2_TRANS.ALL_REQUESTS",
brief_description:
"Transactions accessing L2 pipe",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_DISPATCHED_PORT.PORT_4",
IntelPerformanceCounterDescription{event_code:
Tuple::One(161),
umask:
Tuple::One(64),
event_name:
"UOPS_DISPATCHED_PORT.PORT_4",
brief_description:
"Cycles per thread when uops are dispatched to port 4",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("ROB_MISC_EVENTS.LBR_INSERTS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(204),
umask:
Tuple::One(32),
event_name:
"ROB_MISC_EVENTS.LBR_INSERTS",
brief_description:
"Count cases of saving new LBR",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_LOAD_UOPS_RETIRED.L2_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(209),
umask:
Tuple::One(16),
event_name:
"MEM_LOAD_UOPS_RETIRED.L2_MISS",
brief_description:
"Miss in mid-level (L2) cache. Excludes Unknown data-source.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
50021,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("LD_BLOCKS.NO_SR",
IntelPerformanceCounterDescription{event_code:
Tuple::One(3),
umask:
Tuple::One(8),
event_name:
"LD_BLOCKS.NO_SR",
brief_description:
"This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_TRANS.CODE_RD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(240),
umask:
Tuple::One(4),
event_name:
"L2_TRANS.CODE_RD",
brief_description:
"L2 cache accesses when fetching instructions",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.NO_SNOOP_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.NO_SNOOP_NEEDED",
brief_description:
"Counts demand data writes (RFOs) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
4298899458,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("FP_ASSIST.SIMD_INPUT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(202),
umask:
Tuple::One(16),
event_name:
"FP_ASSIST.SIMD_INPUT",
brief_description:
"Number of SIMD FP assists due to input values",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MOVE_ELIMINATION.INT_NOT_ELIMINATED",
IntelPerformanceCounterDescription{event_code:
Tuple::One(88),
umask:
Tuple::One(4),
event_name:
"MOVE_ELIMINATION.INT_NOT_ELIMINATED",
brief_description:
"Number of integer Move Elimination candidate uops that were not eliminated.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
1000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_DISPATCHED_PORT.PORT_5_CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(161),
umask:
Tuple::One(128),
event_name:
"UOPS_DISPATCHED_PORT.PORT_5_CORE",
brief_description:
"Cycles per core when uops are dispatched to port 5",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
true,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.DRAM",
brief_description:
"Counts all demand & prefetch code reads that miss the LLC and the data returned from dram",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
12889096772,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("RESOURCE_STALLS.ROB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(162),
umask:
Tuple::One(16),
event_name:
"RESOURCE_STALLS.ROB",
brief_description:
"Cycles stalled due to re-order buffer full.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
IntelPerformanceCounterDescription{event_code:
Tuple::One(205),
umask:
Tuple::One(1),
event_name:
"MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
brief_description:
"Loads with latency value being above 64",
public_description:
None,
counter:
Counter::Programmable(8),
counter_ht_off:
Counter::Programmable(8),
pebs_counters:
None,
sample_after_value:
2003,
msr_index:
MSRIndex::One(246),
msr_value:
64,
taken_alone:
true,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOnly,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("IDQ.MS_DSB_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(121),
umask:
Tuple::One(16),
event_name:
"IDQ.MS_DSB_CYCLES",
brief_description:
"Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MACHINE_CLEARS.MASKMOV",
IntelPerformanceCounterDescription{event_code:
Tuple::One(195),
umask:
Tuple::One(32),
event_name:
"MACHINE_CLEARS.MASKMOV",
brief_description:
"This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
IntelPerformanceCounterDescription{event_code:
Tuple::One(96),
umask:
Tuple::One(4),
event_name:
"OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
brief_description:
"Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("BACLEARS.ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(230),
umask:
Tuple::One(31),
event_name:
"BACLEARS.ANY",
brief_description:
"Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",
IntelPerformanceCounterDescription{event_code:
Tuple::One(136),
umask:
Tuple::One(196),
event_name:
"BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",
brief_description:
"Speculative and retired indirect branches excluding calls and returns",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("ILD_STALL.IQ_FULL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(135),
umask:
Tuple::One(4),
event_name:
"ILD_STALL.IQ_FULL",
brief_description:
"Stall cycles because IQ is full",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_MISP_RETIRED.CONDITIONAL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(197),
umask:
Tuple::One(1),
event_name:
"BR_MISP_RETIRED.CONDITIONAL",
brief_description:
"Mispredicted conditional branch instructions retired.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
400009,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("DTLB_STORE_MISSES.WALK_DURATION",
IntelPerformanceCounterDescription{event_code:
Tuple::One(73),
umask:
Tuple::One(4),
event_name:
"DTLB_STORE_MISSES.WALK_DURATION",
brief_description:
"Cycles when PMH is busy with page walks",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(16),
umask:
Tuple::One(128),
event_name:
"FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE",
brief_description:
"Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(60),
umask:
Tuple::One(1),
event_name:
"CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY",
brief_description:
"Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
true,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_INST_RETIRED.CONDITIONAL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(196),
umask:
Tuple::One(1),
event_name:
"BR_INST_RETIRED.CONDITIONAL",
brief_description:
"Conditional branch instructions retired.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
400009,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_LOAD_UOPS_RETIRED.L1_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(209),
umask:
Tuple::One(8),
event_name:
"MEM_LOAD_UOPS_RETIRED.L1_MISS",
brief_description:
"Retired load uops which data sources following L1 data-cache miss",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("LSD.UOPS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(168),
umask:
Tuple::One(1),
event_name:
"LSD.UOPS",
brief_description:
"Number of Uops delivered by the LSD.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_DISPATCHED_PORT.PORT_2",
IntelPerformanceCounterDescription{event_code:
Tuple::One(161),
umask:
Tuple::One(12),
event_name:
"UOPS_DISPATCHED_PORT.PORT_2",
brief_description:
"Cycles per thread when load or STA uops are dispatched to port 2",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(96),
umask:
Tuple::One(1),
event_name:
"OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
brief_description:
"Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("CYCLE_ACTIVITY.STALLS_TOTAL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(163),
umask:
Tuple::One(4),
event_name:
"CYCLE_ACTIVITY.STALLS_TOTAL",
brief_description:
"Total execution stalls.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
4,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_EXECUTED.CORE_CYCLES_GE_3",
IntelPerformanceCounterDescription{event_code:
Tuple::One(177),
umask:
Tuple::One(2),
event_name:
"UOPS_EXECUTED.CORE_CYCLES_GE_3",
brief_description:
"Cycles at least 3 micro-op is executed from any thread on physical core",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
3,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MOVE_ELIMINATION.INT_ELIMINATED",
IntelPerformanceCounterDescription{event_code:
Tuple::One(88),
umask:
Tuple::One(1),
event_name:
"MOVE_ELIMINATION.INT_ELIMINATED",
brief_description:
"Number of integer Move Elimination candidate uops that were eliminated.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
1000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("CPU_CLK_UNHALTED.REF_TSC",
IntelPerformanceCounterDescription{event_code:
Tuple::One(0),
umask:
Tuple::One(3),
event_name:
"CPU_CLK_UNHALTED.REF_TSC",
brief_description:
"Reference cycles when the core is not in halt state.",
public_description:
None,
counter:
Counter::Fixed(8),
counter_ht_off:
Counter::Fixed(8),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(156),
umask:
Tuple::One(1),
event_name:
"IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
brief_description:
"Cycles with less than 2 uops delivered by the front end.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
2,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_UOPS_RETIRED.LOCK_LOADS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(208),
umask:
Tuple::One(33),
event_name:
"MEM_UOPS_RETIRED.LOCK_LOADS",
brief_description:
"Retired load uops with locked access.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100007,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_ISSUED.SLOW_LEA",
IntelPerformanceCounterDescription{event_code:
Tuple::One(14),
umask:
Tuple::One(32),
event_name:
"UOPS_ISSUED.SLOW_LEA",
brief_description:
"Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("ITLB_MISSES.WALK_DURATION",
IntelPerformanceCounterDescription{event_code:
Tuple::One(133),
umask:
Tuple::One(4),
event_name:
"ITLB_MISSES.WALK_DURATION",
brief_description:
"Cycles when PMH is busy with page walks",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_EXECUTED.CORE_CYCLES_GE_4",
IntelPerformanceCounterDescription{event_code:
Tuple::One(177),
umask:
Tuple::One(2),
event_name:
"UOPS_EXECUTED.CORE_CYCLES_GE_4",
brief_description:
"Cycles at least 4 micro-op is executed from any thread on physical core",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
4,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("CYCLE_ACTIVITY.CYCLES_NO_EXECUTE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(163),
umask:
Tuple::One(4),
event_name:
"CYCLE_ACTIVITY.CYCLES_NO_EXECUTE",
brief_description:
"Total execution stalls",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
4,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(136),
umask:
Tuple::One(144),
event_name:
"BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL",
brief_description:
"Taken speculative and retired direct near calls",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_DISPATCHED_PORT.PORT_4_CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(161),
umask:
Tuple::One(64),
event_name:
"UOPS_DISPATCHED_PORT.PORT_4_CORE",
brief_description:
"Cycles per core when uops are dispatched to port 4",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
true,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_UOPS_RETIRED.ALL_STORES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(208),
umask:
Tuple::One(130),
event_name:
"MEM_UOPS_RETIRED.ALL_STORES",
brief_description:
"All retired store uops.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC",
IntelPerformanceCounterDescription{event_code:
Tuple::One(177),
umask:
Tuple::One(1),
event_name:
"UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC",
brief_description:
"Cycles where at least 2 uops were executed per-thread",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
2,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("INST_RETIRED.PREC_DIST",
IntelPerformanceCounterDescription{event_code:
Tuple::One(192),
umask:
Tuple::One(1),
event_name:
"INST_RETIRED.PREC_DIST",
brief_description:
"Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution",
public_description:
None,
counter:
Counter::Programmable(2),
counter_ht_off:
Counter::Programmable(2),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOnly,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
IntelPerformanceCounterDescription{event_code:
Tuple::One(205),
umask:
Tuple::One(1),
event_name:
"MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
brief_description:
"Loads with latency value being above 512",
public_description:
None,
counter:
Counter::Programmable(8),
counter_ht_off:
Counter::Programmable(8),
pebs_counters:
None,
sample_after_value:
101,
msr_index:
MSRIndex::One(246),
msr_value:
512,
taken_alone:
true,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOnly,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
IntelPerformanceCounterDescription{event_code:
Tuple::One(205),
umask:
Tuple::One(1),
event_name:
"MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
brief_description:
"Loads with latency value being above 32",
public_description:
None,
counter:
Counter::Programmable(8),
counter_ht_off:
Counter::Programmable(8),
pebs_counters:
None,
sample_after_value:
100007,
msr_index:
MSRIndex::One(246),
msr_value:
32,
taken_alone:
true,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOnly,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC",
IntelPerformanceCounterDescription{event_code:
Tuple::One(177),
umask:
Tuple::One(1),
event_name:
"UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC",
brief_description:
"Cycles where at least 4 uops were executed per-thread",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
4,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_UOPS_RETIRED.SPLIT_LOADS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(208),
umask:
Tuple::One(65),
event_name:
"MEM_UOPS_RETIRED.SPLIT_LOADS",
brief_description:
"Retired load uops that split across a cacheline boundary.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(16),
umask:
Tuple::One(16),
event_name:
"FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE",
brief_description:
"Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
IntelPerformanceCounterDescription{event_code:
Tuple::One(8),
umask:
Tuple::One(129),
event_name:
"DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
brief_description:
"Demand load Miss in all translation lookaside buffer (TLB) levels causes an page walk of any page size.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_DISPATCHED_PORT.PORT_0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(161),
umask:
Tuple::One(1),
event_name:
"UOPS_DISPATCHED_PORT.PORT_0",
brief_description:
"Cycles per thread when uops are dispatched to port 0",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_INST_EXEC.TAKEN_CONDITIONAL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(136),
umask:
Tuple::One(129),
event_name:
"BR_INST_EXEC.TAKEN_CONDITIONAL",
brief_description:
"Taken speculative and retired macro-conditional branches",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OTHER_ASSISTS.AVX_TO_SSE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(193),
umask:
Tuple::One(16),
event_name:
"OTHER_ASSISTS.AVX_TO_SSE",
brief_description:
"Number of transitions from AVX-256 to legacy SSE when penalty applicable.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("FP_ASSIST.SIMD_OUTPUT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(202),
umask:
Tuple::One(8),
event_name:
"FP_ASSIST.SIMD_OUTPUT",
brief_description:
"Number of SIMD FP assists due to Output values",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("INST_RETIRED.ANY_P",
IntelPerformanceCounterDescription{event_code:
Tuple::One(192),
umask:
Tuple::One(0),
event_name:
"INST_RETIRED.ANY_P",
brief_description:
"Number of instructions retired. General Counter - architectural event",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_LOAD_UOPS_RETIRED.LLC_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(209),
umask:
Tuple::One(4),
event_name:
"MEM_LOAD_UOPS_RETIRED.LLC_HIT",
brief_description:
"Retired load uops which data sources were data hits in LLC without snoops required.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
50021,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_LOAD_UOPS_RETIRED.LLC_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(209),
umask:
Tuple::One(32),
event_name:
"MEM_LOAD_UOPS_RETIRED.LLC_MISS",
brief_description:
"Miss in last-level (L3) cache. Excludes Unknown data-source.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100007,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("CYCLE_ACTIVITY.STALLS_L1D_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(163),
umask:
Tuple::One(12),
event_name:
"CYCLE_ACTIVITY.STALLS_L1D_MISS",
brief_description:
"Execution stalls while L1 cache miss demand load is outstanding.",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Programmable(4),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
12,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("ITLB_MISSES.LARGE_PAGE_WALK_COMPLETED",
IntelPerformanceCounterDescription{event_code:
Tuple::One(133),
umask:
Tuple::One(128),
event_name:
"ITLB_MISSES.LARGE_PAGE_WALK_COMPLETED",
brief_description:
"Completed page walks in ITLB due to STLB load misses for large pages",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_RETIRED.CORE_STALL_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(194),
umask:
Tuple::One(1),
event_name:
"UOPS_RETIRED.CORE_STALL_CYCLES",
brief_description:
"Cycles without actually retired uops.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
true,
any_thread:
true,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MACHINE_CLEARS.SMC",
IntelPerformanceCounterDescription{event_code:
Tuple::One(195),
umask:
Tuple::One(4),
event_name:
"MACHINE_CLEARS.SMC",
brief_description:
"Self-modifying code (SMC) detected.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("LSD.CYCLES_ACTIVE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(168),
umask:
Tuple::One(1),
event_name:
"LSD.CYCLES_ACTIVE",
brief_description:
"Cycles Uops delivered by the LSD, but didn\'t come from the decoder",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("RESOURCE_STALLS.ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(162),
umask:
Tuple::One(1),
event_name:
"RESOURCE_STALLS.ANY",
brief_description:
"Resource-related stall cycles",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("SIMD_FP_256.PACKED_SINGLE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(17),
umask:
Tuple::One(1),
event_name:
"SIMD_FP_256.PACKED_SINGLE",
brief_description:
"number of GSSE-256 Computational FP single precision uops issued this cycle",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("IDQ.MS_SWITCHES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(121),
umask:
Tuple::One(48),
event_name:
"IDQ.MS_SWITCHES",
brief_description:
"Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
false,
any_thread:
false,
edge_detect:
true,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(96),
umask:
Tuple::One(8),
event_name:
"OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
brief_description:
"Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
IntelPerformanceCounterDescription{event_code:
Tuple::One(205),
umask:
Tuple::One(1),
event_name:
"MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
brief_description:
"Loads with latency value being above 16",
public_description:
None,
counter:
Counter::Programmable(8),
counter_ht_off:
Counter::Programmable(8),
pebs_counters:
None,
sample_after_value:
20011,
msr_index:
MSRIndex::One(246),
msr_value:
16,
taken_alone:
true,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOnly,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("DTLB_STORE_MISSES.WALK_COMPLETED",
IntelPerformanceCounterDescription{event_code:
Tuple::One(73),
umask:
Tuple::One(2),
event_name:
"DTLB_STORE_MISSES.WALK_COMPLETED",
brief_description:
"Store misses in all DTLB levels that cause completed page walks",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_MISP_EXEC.NONTAKEN_CONDITIONAL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(137),
umask:
Tuple::One(65),
event_name:
"BR_MISP_EXEC.NONTAKEN_CONDITIONAL",
brief_description:
"Not taken speculative and retired mispredicted macro conditional branches",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_RETIRED.RETIRE_SLOTS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(194),
umask:
Tuple::One(2),
event_name:
"UOPS_RETIRED.RETIRE_SLOTS",
brief_description:
"Retirement slots used.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("FP_ASSIST.ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(202),
umask:
Tuple::One(30),
event_name:
"FP_ASSIST.ANY",
brief_description:
"Cycles with any input/output SSE or FP assist",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("IDQ.MS_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(121),
umask:
Tuple::One(48),
event_name:
"IDQ.MS_CYCLES",
brief_description:
"Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_L1D_WB_RQSTS.HIT_E",
IntelPerformanceCounterDescription{event_code:
Tuple::One(40),
umask:
Tuple::One(4),
event_name:
"L2_L1D_WB_RQSTS.HIT_E",
brief_description:
"Not rejected writebacks from L1D to L2 cache lines in E state",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC",
IntelPerformanceCounterDescription{event_code:
Tuple::One(177),
umask:
Tuple::One(1),
event_name:
"UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC",
brief_description:
"Cycles where at least 3 uops were executed per-thread",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
3,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(7),
umask:
Tuple::One(1),
event_name:
"LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",
brief_description:
"False dependencies in MOB due to partial compare on address",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_DISPATCHED_PORT.PORT_1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(161),
umask:
Tuple::One(2),
event_name:
"UOPS_DISPATCHED_PORT.PORT_1",
brief_description:
"Cycles per thread when uops are dispatched to port 1",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_DISPATCHED_PORT.PORT_5",
IntelPerformanceCounterDescription{event_code:
Tuple::One(161),
umask:
Tuple::One(128),
event_name:
"UOPS_DISPATCHED_PORT.PORT_5",
brief_description:
"Cycles per thread when uops are dispatched to port 5",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_RQSTS.ALL_DEMAND_DATA_RD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(36),
umask:
Tuple::One(3),
event_name:
"L2_RQSTS.ALL_DEMAND_DATA_RD",
brief_description:
"Demand Data Read requests",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_INST_EXEC.ALL_CONDITIONAL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(136),
umask:
Tuple::One(193),
event_name:
"BR_INST_EXEC.ALL_CONDITIONAL",
brief_description:
"Speculative and retired macro-conditional branches",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(210),
umask:
Tuple::One(4),
event_name:
"MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM",
brief_description:
"Retired load uops which data sources were HitM responses from shared LLC.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
20011,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("LSD.CYCLES_4_UOPS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(168),
umask:
Tuple::One(1),
event_name:
"LSD.CYCLES_4_UOPS",
brief_description:
"Cycles 4 Uops delivered by the LSD, but didn\'t come from the decoder",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
4,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.ANY_RESPONSE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.ANY_RESPONSE",
brief_description:
"Counts all demand & prefetch data reads that hit in the LLC",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
272734355601,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.DRAM",
brief_description:
"Counts demand data reads that miss the LLC and the data returned from dram",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
12889096193,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_LINES_OUT.PF_CLEAN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(242),
umask:
Tuple::One(4),
event_name:
"L2_LINES_OUT.PF_CLEAN",
brief_description:
"Clean L2 cache lines evicted by L2 prefetch",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("CYCLE_ACTIVITY.CYCLES_L1D_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(163),
umask:
Tuple::One(8),
event_name:
"CYCLE_ACTIVITY.CYCLES_L1D_MISS",
brief_description:
"Cycles while L1 cache miss demand load is outstanding.",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Programmable(4),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
8,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_MISP_RETIRED.NEAR_TAKEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(197),
umask:
Tuple::One(32),
event_name:
"BR_MISP_RETIRED.NEAR_TAKEN",
brief_description:
"number of near branch instructions retired that were mispredicted and taken.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
400009,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_MISP_RETIRED.ALL_BRANCHES_PEBS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(197),
umask:
Tuple::One(4),
event_name:
"BR_MISP_RETIRED.ALL_BRANCHES_PEBS",
brief_description:
"Mispredicted macro branch instructions retired.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
400009,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOnly,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("CYCLE_ACTIVITY.CYCLES_L2_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(163),
umask:
Tuple::One(1),
event_name:
"CYCLE_ACTIVITY.CYCLES_L2_MISS",
brief_description:
"Cycles while L2 cache miss load* is outstanding.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
IntelPerformanceCounterDescription{event_code:
Tuple::One(99),
umask:
Tuple::One(1),
event_name:
"LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
brief_description:
"Cycles when L1 and L2 are locked due to UC or split lock",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_INST_RETIRED.NEAR_TAKEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(196),
umask:
Tuple::One(32),
event_name:
"BR_INST_RETIRED.NEAR_TAKEN",
brief_description:
"Taken branch instructions retired.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
400009,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE",
brief_description:
"Counts non-temporal stores",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
67584,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_INST_EXEC.ALL_DIRECT_JMP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(136),
umask:
Tuple::One(194),
event_name:
"BR_INST_EXEC.ALL_DIRECT_JMP",
brief_description:
"Speculative and retired macro-unconditional branches excluding calls and indirects",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_REQUESTS.DEMAND_DATA_RD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(176),
umask:
Tuple::One(1),
event_name:
"OFFCORE_REQUESTS.DEMAND_DATA_RD",
brief_description:
"Demand Data Read requests sent to uncore",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(210),
umask:
Tuple::One(8),
event_name:
"MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE",
brief_description:
"Retired load uops which data sources were hits in LLC without snoops required.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(136),
umask:
Tuple::One(136),
event_name:
"BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN",
brief_description:
"Taken speculative and retired indirect branches with return mnemonic",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_INST_EXEC.NONTAKEN_CONDITIONAL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(136),
umask:
Tuple::One(65),
event_name:
"BR_INST_EXEC.NONTAKEN_CONDITIONAL",
brief_description:
"Not taken macro-conditional branches",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("IDQ.MITE_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(121),
umask:
Tuple::One(4),
event_name:
"IDQ.MITE_CYCLES",
brief_description:
"Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MOVE_ELIMINATION.SIMD_NOT_ELIMINATED",
IntelPerformanceCounterDescription{event_code:
Tuple::One(88),
umask:
Tuple::One(8),
event_name:
"MOVE_ELIMINATION.SIMD_NOT_ELIMINATED",
brief_description:
"Number of SIMD Move Elimination candidate uops that were not eliminated.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
1000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE",
brief_description:
"Counts all demand & prefetch data reads",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
66995,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("CPU_CLK_UNHALTED.THREAD_P",
IntelPerformanceCounterDescription{event_code:
Tuple::One(60),
umask:
Tuple::One(0),
event_name:
"CPU_CLK_UNHALTED.THREAD_P",
brief_description:
"Thread cycles when thread is not in halt state",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",
IntelPerformanceCounterDescription{event_code:
Tuple::One(137),
umask:
Tuple::One(196),
event_name:
"BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",
brief_description:
"Mispredicted indirect branches excluding calls and returns",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("IDQ.DSB_UOPS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(121),
umask:
Tuple::One(8),
event_name:
"IDQ.DSB_UOPS",
brief_description:
"Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_LINES_OUT.DEMAND_CLEAN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(242),
umask:
Tuple::One(1),
event_name:
"L2_LINES_OUT.DEMAND_CLEAN",
brief_description:
"Clean L2 cache lines evicted by demand",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_ISSUED.ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(14),
umask:
Tuple::One(1),
event_name:
"UOPS_ISSUED.ANY",
brief_description:
"Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("CYCLE_ACTIVITY.STALLS_L2_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(163),
umask:
Tuple::One(5),
event_name:
"CYCLE_ACTIVITY.STALLS_L2_MISS",
brief_description:
"Execution stalls while L2 cache miss load* is outstanding.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
5,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_TRANS.RFO",
IntelPerformanceCounterDescription{event_code:
Tuple::One(240),
umask:
Tuple::One(2),
event_name:
"L2_TRANS.RFO",
brief_description:
"RFO requests that access L2 cache",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_L1D_WB_RQSTS.ALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(40),
umask:
Tuple::One(15),
event_name:
"L2_L1D_WB_RQSTS.ALL",
brief_description:
"Not rejected writebacks from L1D to L2 cache lines in any state.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_REQUESTS.DEMAND_RFO",
IntelPerformanceCounterDescription{event_code:
Tuple::One(176),
umask:
Tuple::One(4),
event_name:
"OFFCORE_REQUESTS.DEMAND_RFO",
brief_description:
"Demand RFO requests including regular RFOs, locks, ItoM",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_TRANS.L2_FILL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(240),
umask:
Tuple::One(32),
event_name:
"L2_TRANS.L2_FILL",
brief_description:
"L2 fill requests that access L2 cache",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_INST_RETIRED.FAR_BRANCH",
IntelPerformanceCounterDescription{event_code:
Tuple::One(196),
umask:
Tuple::One(64),
event_name:
"BR_INST_RETIRED.FAR_BRANCH",
brief_description:
"Far branch instructions retired.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100007,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_RQSTS.CODE_RD_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(36),
umask:
Tuple::One(32),
event_name:
"L2_RQSTS.CODE_RD_MISS",
brief_description:
"L2 cache misses when fetching instructions",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("DSB2MITE_SWITCHES.PENALTY_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(171),
umask:
Tuple::One(2),
event_name:
"DSB2MITE_SWITCHES.PENALTY_CYCLES",
brief_description:
"Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_INST_RETIRED.NOT_TAKEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(196),
umask:
Tuple::One(16),
event_name:
"BR_INST_RETIRED.NOT_TAKEN",
brief_description:
"Not taken branch instructions retired.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
400009,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.COREWB.ANY_RESPONSE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.COREWB.ANY_RESPONSE",
brief_description:
"Counts all writebacks from the core to the LLC",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
65544,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("IDQ.ALL_DSB_CYCLES_4_UOPS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(121),
umask:
Tuple::One(24),
event_name:
"IDQ.ALL_DSB_CYCLES_4_UOPS",
brief_description:
"Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
4,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_REQUESTS_BUFFER.SQ_FULL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(178),
umask:
Tuple::One(1),
event_name:
"OFFCORE_REQUESTS_BUFFER.SQ_FULL",
brief_description:
"Cases when offcore requests buffer cannot take more entries for core",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_INST_EXEC.TAKEN_DIRECT_JUMP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(136),
umask:
Tuple::One(130),
event_name:
"BR_INST_EXEC.TAKEN_DIRECT_JUMP",
brief_description:
"Taken speculative and retired macro-conditional branch instructions excluding calls and indirects",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("IDQ.MITE_ALL_UOPS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(121),
umask:
Tuple::One(60),
event_name:
"IDQ.MITE_ALL_UOPS",
brief_description:
"Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("TLB_FLUSH.STLB_ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(189),
umask:
Tuple::One(32),
event_name:
"TLB_FLUSH.STLB_ANY",
brief_description:
"STLB flush attempts",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100007,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("EPT.WALK_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(79),
umask:
Tuple::One(16),
event_name:
"EPT.WALK_CYCLES",
brief_description:
"Cycle count for an Extended Page table walk. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(136),
umask:
Tuple::One(160),
event_name:
"BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL",
brief_description:
"Taken speculative and retired indirect calls",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("DTLB_LOAD_MISSES.WALK_COMPLETED",
IntelPerformanceCounterDescription{event_code:
Tuple::One(8),
umask:
Tuple::One(130),
event_name:
"DTLB_LOAD_MISSES.WALK_COMPLETED",
brief_description:
"Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("RS_EVENTS.EMPTY_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(94),
umask:
Tuple::One(1),
event_name:
"RS_EVENTS.EMPTY_CYCLES",
brief_description:
"Cycles when Reservation Station (RS) is empty for the thread",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("ILD_STALL.LCP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(135),
umask:
Tuple::One(1),
event_name:
"ILD_STALL.LCP",
brief_description:
"Stalls caused by changing prefix length of the instruction.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("IDQ.EMPTY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(121),
umask:
Tuple::One(2),
event_name:
"IDQ.EMPTY",
brief_description:
"Instruction Decode Queue (IDQ) empty cycles",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_LOAD_UOPS_RETIRED.L1_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(209),
umask:
Tuple::One(1),
event_name:
"MEM_LOAD_UOPS_RETIRED.L1_HIT",
brief_description:
"Retired load uops with L1 cache hits as data sources.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_UOPS_RETIRED.SPLIT_STORES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(208),
umask:
Tuple::One(66),
event_name:
"MEM_UOPS_RETIRED.SPLIT_STORES",
brief_description:
"Retired store uops that split across a cacheline boundary.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("FP_COMP_OPS_EXE.SSE_PACKED_SINGLE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(16),
umask:
Tuple::One(64),
event_name:
"FP_COMP_OPS_EXE.SSE_PACKED_SINGLE",
brief_description:
"Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
brief_description:
"Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
4298899457,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_ISSUED.STALL_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(14),
umask:
Tuple::One(1),
event_name:
"UOPS_ISSUED.STALL_CYCLES",
brief_description:
"Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
true,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_TRANS.ALL_PF",
IntelPerformanceCounterDescription{event_code:
Tuple::One(240),
umask:
Tuple::One(8),
event_name:
"L2_TRANS.ALL_PF",
brief_description:
"L2 or LLC HW prefetches that access L2 cache",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_REQUESTS.DEMAND_CODE_RD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(176),
umask:
Tuple::One(2),
event_name:
"OFFCORE_REQUESTS.DEMAND_CODE_RD",
brief_description:
"Cacheable and noncachaeble code read requests",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("IDQ.ALL_MITE_CYCLES_4_UOPS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(121),
umask:
Tuple::One(36),
event_name:
"IDQ.ALL_MITE_CYCLES_4_UOPS",
brief_description:
"Cycles MITE is delivering 4 Uops",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
4,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_LINES_IN.I",
IntelPerformanceCounterDescription{event_code:
Tuple::One(241),
umask:
Tuple::One(1),
event_name:
"L2_LINES_IN.I",
brief_description:
"L2 cache lines in I state filling L2",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_LINES_IN.S",
IntelPerformanceCounterDescription{event_code:
Tuple::One(241),
umask:
Tuple::One(2),
event_name:
"L2_LINES_IN.S",
brief_description:
"L2 cache lines in S state filling L2",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("LONGEST_LAT_CACHE.REFERENCE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(46),
umask:
Tuple::One(79),
event_name:
"LONGEST_LAT_CACHE.REFERENCE",
brief_description:
"Core-originated cacheable demand requests that refer to LLC",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(211),
umask:
Tuple::One(1),
event_name:
"MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM",
brief_description:
"Retired load uops which data sources missed LLC but serviced from local dram.",
public_description:
Some("Retired load uop whose Data Source was: local DRAM either Snoop not needed or Snoop Miss (RspI)"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100007,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("ITLB_MISSES.MISS_CAUSES_A_WALK",
IntelPerformanceCounterDescription{event_code:
Tuple::One(133),
umask:
Tuple::One(1),
event_name:
"ITLB_MISSES.MISS_CAUSES_A_WALK",
brief_description:
"Misses at all ITLB levels that cause page walks",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("IDQ.MS_DSB_OCCUR",
IntelPerformanceCounterDescription{event_code:
Tuple::One(121),
umask:
Tuple::One(16),
event_name:
"IDQ.MS_DSB_OCCUR",
brief_description:
"Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
false,
any_thread:
false,
edge_detect:
true,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L1D_PEND_MISS.FB_FULL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(72),
umask:
Tuple::One(2),
event_name:
"L1D_PEND_MISS.FB_FULL",
brief_description:
"Cycles a demand request was blocked due to Fill Buffers inavailability",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_MISP_EXEC.TAKEN_CONDITIONAL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(137),
umask:
Tuple::One(129),
event_name:
"BR_MISP_EXEC.TAKEN_CONDITIONAL",
brief_description:
"Taken speculative and retired mispredicted macro conditional branches",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE",
brief_description:
"Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
68723408898,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
IntelPerformanceCounterDescription{event_code:
Tuple::One(205),
umask:
Tuple::One(1),
event_name:
"MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
brief_description:
"Loads with latency value being above 128",
public_description:
None,
counter:
Counter::Programmable(8),
counter_ht_off:
Counter::Programmable(8),
pebs_counters:
None,
sample_after_value:
1009,
msr_index:
MSRIndex::One(246),
msr_value:
128,
taken_alone:
true,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOnly,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("CPU_CLK_UNHALTED.THREAD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(0),
umask:
Tuple::One(2),
event_name:
"CPU_CLK_UNHALTED.THREAD",
brief_description:
"Core cycles when the thread is not in halt state.",
public_description:
None,
counter:
Counter::Fixed(4),
counter_ht_off:
Counter::Fixed(4),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE",
brief_description:
"Counts all demand & prefetch prefetch RFOs",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
65826,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("ARITH.FPU_DIV",
IntelPerformanceCounterDescription{event_code:
Tuple::One(20),
umask:
Tuple::One(4),
event_name:
"ARITH.FPU_DIV",
brief_description:
"Divide operations executed",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
false,
any_thread:
false,
edge_detect:
true,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("LD_BLOCKS.STORE_FORWARD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(3),
umask:
Tuple::One(2),
event_name:
"LD_BLOCKS.STORE_FORWARD",
brief_description:
"Cases when loads get true Block-on-Store blocking code preventing store forwarding",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_EXECUTED.THREAD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(177),
umask:
Tuple::One(1),
event_name:
"UOPS_EXECUTED.THREAD",
brief_description:
"Counts the number of uops to be executed per-thread each cycle.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_INST_RETIRED.ALL_BRANCHES_PEBS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(196),
umask:
Tuple::One(4),
event_name:
"BR_INST_RETIRED.ALL_BRANCHES_PEBS",
brief_description:
"All (macro) branch instructions retired.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
400009,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOnly,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("IDQ.ALL_MITE_CYCLES_ANY_UOPS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(121),
umask:
Tuple::One(36),
event_name:
"IDQ.ALL_MITE_CYCLES_ANY_UOPS",
brief_description:
"Cycles MITE is delivering any Uop",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(16),
umask:
Tuple::One(32),
event_name:
"FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE",
brief_description:
"Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("CYCLE_ACTIVITY.CYCLES_LDM_PENDING",
IntelPerformanceCounterDescription{event_code:
Tuple::One(163),
umask:
Tuple::One(2),
event_name:
"CYCLE_ACTIVITY.CYCLES_LDM_PENDING",
brief_description:
"Cycles with pending memory loads.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
2,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.NO_SNOOP_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.NO_SNOOP_NEEDED",
brief_description:
"Counts demand & prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
4298899746,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.DRAM",
brief_description:
"Counts all demand & prefetch data reads that miss the LLC and the data returned from dram",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
12889096337,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC",
IntelPerformanceCounterDescription{event_code:
Tuple::One(177),
umask:
Tuple::One(1),
event_name:
"UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC",
brief_description:
"Cycles where at least 1 uop was executed per-thread",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("CYCLE_ACTIVITY.STALLS_LDM_PENDING",
IntelPerformanceCounterDescription{event_code:
Tuple::One(163),
umask:
Tuple::One(6),
event_name:
"CYCLE_ACTIVITY.STALLS_LDM_PENDING",
brief_description:
"Execution stalls due to memory subsystem.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
6,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED",
brief_description:
"Counts demand code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
4298899460,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("DTLB_LOAD_MISSES.STLB_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(95),
umask:
Tuple::One(4),
event_name:
"DTLB_LOAD_MISSES.STLB_HIT",
brief_description:
"Load operations that miss the first DTLB level but hit the second and do not cause page walks",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
IntelPerformanceCounterDescription{event_code:
Tuple::One(205),
umask:
Tuple::One(1),
event_name:
"MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
brief_description:
"Loads with latency value being above 256",
public_description:
None,
counter:
Counter::Programmable(8),
counter_ht_off:
Counter::Programmable(8),
pebs_counters:
None,
sample_after_value:
503,
msr_index:
MSRIndex::One(246),
msr_value:
256,
taken_alone:
true,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOnly,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
IntelPerformanceCounterDescription{event_code:
Tuple::One(156),
umask:
Tuple::One(1),
event_name:
"IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
brief_description:
"Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
true,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_MISP_EXEC.ALL_CONDITIONAL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(137),
umask:
Tuple::One(193),
event_name:
"BR_MISP_EXEC.ALL_CONDITIONAL",
brief_description:
"Speculative and retired mispredicted macro conditional branches",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.ANY_RESPONSE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.ANY_RESPONSE",
brief_description:
"Counts all demand & prefetch code reads that hit in the LLC",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
272734356036,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_DISPATCHED_PORT.PORT_1_CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(161),
umask:
Tuple::One(2),
event_name:
"UOPS_DISPATCHED_PORT.PORT_1_CORE",
brief_description:
"Cycles per core when uops are dispatched to port 1",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
true,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
brief_description:
"Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
68723409041,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.ALL_READS.ANY_RESPONSE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.ALL_READS.ANY_RESPONSE",
brief_description:
"Counts all data/code/rfo references (demand & prefetch)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
67575,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_MISP_EXEC.TAKEN_RETURN_NEAR",
IntelPerformanceCounterDescription{event_code:
Tuple::One(137),
umask:
Tuple::One(136),
event_name:
"BR_MISP_EXEC.TAKEN_RETURN_NEAR",
brief_description:
"Taken speculative and retired mispredicted indirect branches with return mnemonic",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("PAGE_WALKS.LLC_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(190),
umask:
Tuple::One(1),
event_name:
"PAGE_WALKS.LLC_MISS",
brief_description:
"Number of any page walk that had a miss in LLC.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE",
brief_description:
"Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
66560,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED",
brief_description:
"Counts demand & prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
4298900036,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_LOAD_UOPS_RETIRED.HIT_LFB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(209),
umask:
Tuple::One(64),
event_name:
"MEM_LOAD_UOPS_RETIRED.HIT_LFB",
brief_description:
"Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(136),
umask:
Tuple::One(200),
event_name:
"BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN",
brief_description:
"Speculative and retired indirect return branches.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
IntelPerformanceCounterDescription{event_code:
Tuple::One(73),
umask:
Tuple::One(1),
event_name:
"DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
brief_description:
"Store misses in all DTLB levels that cause page walks",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_TRANS_RETIRED.PRECISE_STORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(205),
umask:
Tuple::One(2),
event_name:
"MEM_TRANS_RETIRED.PRECISE_STORE",
brief_description:
"Sample stores and collect precise store operation via PEBS record. PMC3 only.",
public_description:
None,
counter:
Counter::Programmable(8),
counter_ht_off:
Counter::Programmable(8),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
true,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOnly,
precise_store:
true,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_RETIRED.ALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(194),
umask:
Tuple::One(1),
event_name:
"UOPS_RETIRED.ALL",
brief_description:
"Actually retired uops.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("IDQ.ALL_DSB_CYCLES_ANY_UOPS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(121),
umask:
Tuple::One(24),
event_name:
"IDQ.ALL_DSB_CYCLES_ANY_UOPS",
brief_description:
"Cycles Decode Stream Buffer (DSB) is delivering any Uop",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_LINES_OUT.PF_DIRTY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(242),
umask:
Tuple::One(8),
event_name:
"L2_LINES_OUT.PF_DIRTY",
brief_description:
"Dirty L2 cache lines evicted by L2 prefetch",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("DTLB_STORE_MISSES.STLB_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(73),
umask:
Tuple::One(16),
event_name:
"DTLB_STORE_MISSES.STLB_HIT",
brief_description:
"Store operations that miss the first TLB level but hit the second and do not cause page walks",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OTHER_ASSISTS.ANY_WB_ASSIST",
IntelPerformanceCounterDescription{event_code:
Tuple::One(193),
umask:
Tuple::One(128),
event_name:
"OTHER_ASSISTS.ANY_WB_ASSIST",
brief_description:
"Number of times any microcode assist is invoked by HW upon uop writeback.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("DTLB_LOAD_MISSES.LARGE_PAGE_WALK_COMPLETED",
IntelPerformanceCounterDescription{event_code:
Tuple::One(8),
umask:
Tuple::One(136),
event_name:
"DTLB_LOAD_MISSES.LARGE_PAGE_WALK_COMPLETED",
brief_description:
"Page walk for a large page completed for Demand load",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("CYCLE_ACTIVITY.CYCLES_L2_PENDING",
IntelPerformanceCounterDescription{event_code:
Tuple::One(163),
umask:
Tuple::One(1),
event_name:
"CYCLE_ACTIVITY.CYCLES_L2_PENDING",
brief_description:
"Cycles with pending L2 cache miss loads.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_LINES_OUT.DIRTY_ALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(242),
umask:
Tuple::One(10),
event_name:
"L2_LINES_OUT.DIRTY_ALL",
brief_description:
"Dirty L2 cache lines filling the L2",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
brief_description:
"Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
17183801489,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS.LOCAL_DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS.LOCAL_DRAM",
brief_description:
"Counts LLC replacements",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
25773998515,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("IDQ.MS_DSB_UOPS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(121),
umask:
Tuple::One(16),
event_name:
"IDQ.MS_DSB_UOPS",
brief_description:
"Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_RETIRED.TOTAL_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(194),
umask:
Tuple::One(1),
event_name:
"UOPS_RETIRED.TOTAL_CYCLES",
brief_description:
"Cycles with less than 10 actually retired uops.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
10,
invert:
true,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(156),
umask:
Tuple::One(1),
event_name:
"IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
brief_description:
"Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
3,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_ISSUED.SINGLE_MUL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(14),
umask:
Tuple::One(64),
event_name:
"UOPS_ISSUED.SINGLE_MUL",
brief_description:
"Number of Multiply packed/scalar single precision uops allocated",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_RQSTS.DEMAND_DATA_RD_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(36),
umask:
Tuple::One(1),
event_name:
"L2_RQSTS.DEMAND_DATA_RD_HIT",
brief_description:
"Demand Data Read requests that hit L2 cache",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("LONGEST_LAT_CACHE.MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(46),
umask:
Tuple::One(65),
event_name:
"LONGEST_LAT_CACHE.MISS",
brief_description:
"Core-originated cacheable demand requests missed LLC",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_UOPS_RETIRED.STLB_MISS_LOADS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(208),
umask:
Tuple::One(17),
event_name:
"MEM_UOPS_RETIRED.STLB_MISS_LOADS",
brief_description:
"Retired load uops that miss the STLB.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("DTLB_LOAD_MISSES.WALK_DURATION",
IntelPerformanceCounterDescription{event_code:
Tuple::One(8),
umask:
Tuple::One(132),
event_name:
"DTLB_LOAD_MISSES.WALK_DURATION",
brief_description:
"Demand load cycles page miss handler (PMH) is busy with this walk.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MISALIGN_MEM_REF.LOADS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(5),
umask:
Tuple::One(1),
event_name:
"MISALIGN_MEM_REF.LOADS",
brief_description:
"Speculative cache line split load uops dispatched to L1 cache",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OTHER_ASSISTS.AVX_STORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(193),
umask:
Tuple::One(8),
event_name:
"OTHER_ASSISTS.AVX_STORE",
brief_description:
"Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_INST_RETIRED.NEAR_RETURN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(196),
umask:
Tuple::One(8),
event_name:
"BR_INST_RETIRED.NEAR_RETURN",
brief_description:
"Return instructions retired.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100007,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L1D_PEND_MISS.PENDING_CYCLES_ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(72),
umask:
Tuple::One(1),
event_name:
"L1D_PEND_MISS.PENDING_CYCLES_ANY",
brief_description:
"Cycles with L1D load Misses outstanding from any thread on physical core",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Programmable(4),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
false,
any_thread:
true,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_DISPATCHED_PORT.PORT_3_CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(161),
umask:
Tuple::One(48),
event_name:
"UOPS_DISPATCHED_PORT.PORT_3_CORE",
brief_description:
"Cycles per core when load or STA uops are dispatched to port 3",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
true,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_DISPATCHED_PORT.PORT_3",
IntelPerformanceCounterDescription{event_code:
Tuple::One(161),
umask:
Tuple::One(48),
event_name:
"UOPS_DISPATCHED_PORT.PORT_3",
brief_description:
"Cycles per thread when load or STA uops are dispatched to port 3",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_STORE_LOCK_RQSTS.ALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(39),
umask:
Tuple::One(15),
event_name:
"L2_STORE_LOCK_RQSTS.ALL",
brief_description:
"RFOs that access cache lines in any state",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("CYCLE_ACTIVITY.STALLS_L2_PENDING",
IntelPerformanceCounterDescription{event_code:
Tuple::One(163),
umask:
Tuple::One(5),
event_name:
"CYCLE_ACTIVITY.STALLS_L2_PENDING",
brief_description:
"Execution stalls due to L2 cache misses.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
5,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
brief_description:
"Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
17183801345,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("FP_COMP_OPS_EXE.X87",
IntelPerformanceCounterDescription{event_code:
Tuple::One(16),
umask:
Tuple::One(1),
event_name:
"FP_COMP_OPS_EXE.X87",
brief_description:
"Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("ICACHE.IFETCH_STALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(128),
umask:
Tuple::One(4),
event_name:
"ICACHE.IFETCH_STALL",
brief_description:
"Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
brief_description:
"Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
4298899601,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE",
brief_description:
"Counts all demand code reads",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
65540,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.ANY_RESPONSE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.ANY_RESPONSE",
brief_description:
"Counts all demand & prefetch RFOs that hit in the LLC",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
272734355746,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("ITLB_MISSES.WALK_COMPLETED",
IntelPerformanceCounterDescription{event_code:
Tuple::One(133),
umask:
Tuple::One(2),
event_name:
"ITLB_MISSES.WALK_COMPLETED",
brief_description:
"Misses in all ITLB levels that cause completed page walks",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_RQSTS.ALL_CODE_RD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(36),
umask:
Tuple::One(48),
event_name:
"L2_RQSTS.ALL_CODE_RD",
brief_description:
"L2 code requests",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_EXECUTED.CORE_CYCLES_NONE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(177),
umask:
Tuple::One(2),
event_name:
"UOPS_EXECUTED.CORE_CYCLES_NONE",
brief_description:
"Cycles with no micro-ops executed from any thread on physical core",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
true,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_ISSUED.CORE_STALL_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(14),
umask:
Tuple::One(1),
event_name:
"UOPS_ISSUED.CORE_STALL_CYCLES",
brief_description:
"Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
true,
any_thread:
true,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
IntelPerformanceCounterDescription{event_code:
Tuple::One(205),
umask:
Tuple::One(1),
event_name:
"MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
brief_description:
"Loads with latency value being above 8",
public_description:
None,
counter:
Counter::Programmable(8),
counter_ht_off:
Counter::Programmable(8),
pebs_counters:
None,
sample_after_value:
50021,
msr_index:
MSRIndex::One(246),
msr_value:
8,
taken_alone:
true,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOnly,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("TLB_FLUSH.DTLB_THREAD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(189),
umask:
Tuple::One(1),
event_name:
"TLB_FLUSH.DTLB_THREAD",
brief_description:
"DTLB flush attempts of the thread-specific entries",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100007,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("LOCK_CYCLES.CACHE_LOCK_DURATION",
IntelPerformanceCounterDescription{event_code:
Tuple::One(99),
umask:
Tuple::One(2),
event_name:
"LOCK_CYCLES.CACHE_LOCK_DURATION",
brief_description:
"Cycles when L1D is locked",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE",
brief_description:
"Counts all demand data reads that hit in the LLC",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
272734355457,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",
IntelPerformanceCounterDescription{event_code:
Tuple::One(136),
umask:
Tuple::One(132),
event_name:
"BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",
brief_description:
"Taken speculative and retired indirect branches excluding calls and returns",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(210),
umask:
Tuple::One(1),
event_name:
"MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS",
brief_description:
"Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
20011,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE",
brief_description:
"Counts all demand code reads that hit in the LLC",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
272734355460,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_RETIRED.STALL_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(194),
umask:
Tuple::One(1),
event_name:
"UOPS_RETIRED.STALL_CYCLES",
brief_description:
"Cycles without actually retired uops.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
true,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MACHINE_CLEARS.COUNT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(195),
umask:
Tuple::One(1),
event_name:
"MACHINE_CLEARS.COUNT",
brief_description:
"Number of machine clears (nukes) of any type.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
false,
any_thread:
false,
edge_detect:
true,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("INST_RETIRED.ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(0),
umask:
Tuple::One(1),
event_name:
"INST_RETIRED.ANY",
brief_description:
"Instructions retired from execution.",
public_description:
None,
counter:
Counter::Fixed(2),
counter_ht_off:
Counter::Fixed(2),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("DSB_FILL.EXCEED_DSB_LINES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(172),
umask:
Tuple::One(8),
event_name:
"DSB_FILL.EXCEED_DSB_LINES",
brief_description:
"Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(60),
umask:
Tuple::One(2),
event_name:
"CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE",
brief_description:
"Count XClk pulses when this thread is unhalted and the other is halted.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_INST_EXEC.ALL_DIRECT_NEAR_CALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(136),
umask:
Tuple::One(208),
event_name:
"BR_INST_EXEC.ALL_DIRECT_NEAR_CALL",
brief_description:
"Speculative and retired direct near calls",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("IDQ_UOPS_NOT_DELIVERED.CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(156),
umask:
Tuple::One(1),
event_name:
"IDQ_UOPS_NOT_DELIVERED.CORE",
brief_description:
"Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_LINES_IN.E",
IntelPerformanceCounterDescription{event_code:
Tuple::One(241),
umask:
Tuple::One(4),
event_name:
"L2_LINES_IN.E",
brief_description:
"L2 cache lines in E state filling L2",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_L1D_WB_RQSTS.HIT_M",
IntelPerformanceCounterDescription{event_code:
Tuple::One(40),
umask:
Tuple::One(8),
event_name:
"L2_L1D_WB_RQSTS.HIT_M",
brief_description:
"Not rejected writebacks from L1D to L2 cache lines in M state",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("IDQ.MS_UOPS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(121),
umask:
Tuple::One(48),
event_name:
"IDQ.MS_UOPS",
brief_description:
"Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_INST_RETIRED.ALL_BRANCHES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(196),
umask:
Tuple::One(0),
event_name:
"BR_INST_RETIRED.ALL_BRANCHES",
brief_description:
"All (macro) branch instructions retired.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
400009,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("CPU_CLK_UNHALTED.THREAD_P_ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(60),
umask:
Tuple::One(0),
event_name:
"CPU_CLK_UNHALTED.THREAD_P_ANY",
brief_description:
"Core cycles when at least one thread on the physical core is not in halt state",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
true,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OTHER_ASSISTS.SSE_TO_AVX",
IntelPerformanceCounterDescription{event_code:
Tuple::One(193),
umask:
Tuple::One(32),
event_name:
"OTHER_ASSISTS.SSE_TO_AVX",
brief_description:
"Number of transitions from SSE to AVX-256 when penalty applicable.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("FP_ASSIST.X87_OUTPUT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(202),
umask:
Tuple::One(2),
event_name:
"FP_ASSIST.X87_OUTPUT",
brief_description:
"Number of X87 assists due to output value.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("DSB2MITE_SWITCHES.COUNT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(171),
umask:
Tuple::One(1),
event_name:
"DSB2MITE_SWITCHES.COUNT",
brief_description:
"Decode Stream Buffer (DSB)-to-MITE switches",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MACHINE_CLEARS.MEMORY_ORDERING",
IntelPerformanceCounterDescription{event_code:
Tuple::One(195),
umask:
Tuple::One(2),
event_name:
"MACHINE_CLEARS.MEMORY_ORDERING",
brief_description:
"Counts the number of machine clears due to memory order conflicts.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("IDQ.MS_MITE_UOPS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(121),
umask:
Tuple::One(32),
event_name:
"IDQ.MS_MITE_UOPS",
brief_description:
"Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("RESOURCE_STALLS.SB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(162),
umask:
Tuple::One(8),
event_name:
"RESOURCE_STALLS.SB",
brief_description:
"Cycles stalled due to no store buffers available. (not including draining form sync).",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(96),
umask:
Tuple::One(2),
event_name:
"OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
brief_description:
"Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE",
brief_description:
"Counts all demand rfo\'s",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
65538,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.ANY_RESPONSE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.ANY_RESPONSE",
brief_description:
"Counts all demand data writes (RFOs) that hit in the LLC",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
272734355458,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("INT_MISC.RECOVERY_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(13),
umask:
Tuple::One(3),
event_name:
"INT_MISC.RECOVERY_CYCLES",
brief_description:
"Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_INST_RETIRED.NEAR_CALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(196),
umask:
Tuple::One(2),
event_name:
"BR_INST_RETIRED.NEAR_CALL",
brief_description:
"Direct and indirect near call instructions retired.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100007,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MISALIGN_MEM_REF.STORES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(5),
umask:
Tuple::One(2),
event_name:
"MISALIGN_MEM_REF.STORES",
brief_description:
"Speculative cache line split STA uops dispatched to L1 cache",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("CYCLE_ACTIVITY.STALLS_L1D_PENDING",
IntelPerformanceCounterDescription{event_code:
Tuple::One(163),
umask:
Tuple::One(12),
event_name:
"CYCLE_ACTIVITY.STALLS_L1D_PENDING",
brief_description:
"Execution stalls due to L1 data cache misses",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Programmable(4),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
12,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_STORE_LOCK_RQSTS.HIT_M",
IntelPerformanceCounterDescription{event_code:
Tuple::One(39),
umask:
Tuple::One(8),
event_name:
"L2_STORE_LOCK_RQSTS.HIT_M",
brief_description:
"RFOs that hit cache lines in M state",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_RQSTS.RFO_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(36),
umask:
Tuple::One(8),
event_name:
"L2_RQSTS.RFO_MISS",
brief_description:
"RFO requests that miss L2 cache",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_RQSTS.CODE_RD_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(36),
umask:
Tuple::One(16),
event_name:
"L2_RQSTS.CODE_RD_HIT",
brief_description:
"L2 cache hits when fetching instructions, code reads.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_RQSTS.ALL_PF",
IntelPerformanceCounterDescription{event_code:
Tuple::One(36),
umask:
Tuple::One(192),
event_name:
"L2_RQSTS.ALL_PF",
brief_description:
"Requests from L2 hardware prefetchers",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("CPU_CLK_THREAD_UNHALTED.REF_XCLK",
IntelPerformanceCounterDescription{event_code:
Tuple::One(60),
umask:
Tuple::One(1),
event_name:
"CPU_CLK_THREAD_UNHALTED.REF_XCLK",
brief_description:
"Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("FP_ASSIST.X87_INPUT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(202),
umask:
Tuple::One(4),
event_name:
"FP_ASSIST.X87_INPUT",
brief_description:
"Number of X87 assists due to input value.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.OTHER.ANY_RESPONSE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.OTHER.ANY_RESPONSE",
brief_description:
"Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses. It also includes L2 hints sent to LLC to keep a line from being evicted out of the core caches",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
98304,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_TRANS.DEMAND_DATA_RD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(240),
umask:
Tuple::One(1),
event_name:
"L2_TRANS.DEMAND_DATA_RD",
brief_description:
"Demand Data Read requests that access L2 cache",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_DISPATCHED_PORT.PORT_0_CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(161),
umask:
Tuple::One(1),
event_name:
"UOPS_DISPATCHED_PORT.PORT_0_CORE",
brief_description:
"Cycles per core when uops are dispatched to port 0",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
true,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L1D.REPLACEMENT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(81),
umask:
Tuple::One(1),
event_name:
"L1D.REPLACEMENT",
brief_description:
"L1D data line replacements",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_LINES_IN.ALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(241),
umask:
Tuple::One(7),
event_name:
"L2_LINES_IN.ALL",
brief_description:
"L2 cache lines filling L2",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("CYCLE_ACTIVITY.STALLS_MEM_ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(163),
umask:
Tuple::One(6),
event_name:
"CYCLE_ACTIVITY.STALLS_MEM_ANY",
brief_description:
"Execution stalls while memory subsystem has an outstanding load.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
6,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_UOPS_RETIRED.ALL_LOADS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(208),
umask:
Tuple::One(129),
event_name:
"MEM_UOPS_RETIRED.ALL_LOADS",
brief_description:
"All retired load uops.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_STORE_LOCK_RQSTS.MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(39),
umask:
Tuple::One(1),
event_name:
"L2_STORE_LOCK_RQSTS.MISS",
brief_description:
"RFOs that miss cache lines",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
IntelPerformanceCounterDescription{event_code:
Tuple::One(205),
umask:
Tuple::One(1),
event_name:
"MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
brief_description:
"Loads with latency value being above 4",
public_description:
None,
counter:
Counter::Programmable(8),
counter_ht_off:
Counter::Programmable(8),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::One(246),
msr_value:
4,
taken_alone:
true,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOnly,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(96),
umask:
Tuple::One(8),
event_name:
"OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
brief_description:
"Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(96),
umask:
Tuple::One(2),
event_name:
"OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD",
brief_description:
"Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("RESOURCE_STALLS.RS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(162),
umask:
Tuple::One(4),
event_name:
"RESOURCE_STALLS.RS",
brief_description:
"Cycles stalled due to no eligible RS entry available.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("IDQ.DSB_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(121),
umask:
Tuple::One(8),
event_name:
"IDQ.DSB_CYCLES",
brief_description:
"Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_INST_EXEC.ALL_BRANCHES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(136),
umask:
Tuple::One(255),
event_name:
"BR_INST_EXEC.ALL_BRANCHES",
brief_description:
"Speculative and retired branches",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("ICACHE.MISSES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(128),
umask:
Tuple::One(2),
event_name:
"ICACHE.MISSES",
brief_description:
"Instruction cache, streaming buffer and victim cache misses",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_UOPS_RETIRED.STLB_MISS_STORES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(208),
umask:
Tuple::One(18),
event_name:
"MEM_UOPS_RETIRED.STLB_MISS_STORES",
brief_description:
"Retired store uops that miss the STLB.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE",
brief_description:
"Counts all demand data reads",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
65537,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_LINES_OUT.DEMAND_DIRTY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(242),
umask:
Tuple::One(2),
event_name:
"L2_LINES_OUT.DEMAND_DIRTY",
brief_description:
"Dirty L2 cache lines evicted by demand",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.DRAM",
brief_description:
"Counts demand code reads that miss the LLC and the data returned from dram",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
12889096196,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_RQSTS.RFO_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(36),
umask:
Tuple::One(4),
event_name:
"L2_RQSTS.RFO_HIT",
brief_description:
"RFO requests that hit L2 cache",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",
IntelPerformanceCounterDescription{event_code:
Tuple::One(137),
umask:
Tuple::One(132),
event_name:
"BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",
brief_description:
"Taken speculative and retired mispredicted indirect branches excluding calls and returns",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_EXECUTED.CORE_CYCLES_GE_1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(177),
umask:
Tuple::One(2),
event_name:
"UOPS_EXECUTED.CORE_CYCLES_GE_1",
brief_description:
"Cycles at least 1 micro-op is executed from any thread on physical core",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("CYCLE_ACTIVITY.CYCLES_L1D_PENDING",
IntelPerformanceCounterDescription{event_code:
Tuple::One(163),
umask:
Tuple::One(8),
event_name:
"CYCLE_ACTIVITY.CYCLES_L1D_PENDING",
brief_description:
"Cycles with pending L1 cache miss loads.",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Programmable(4),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
8,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("BR_MISP_RETIRED.ALL_BRANCHES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(197),
umask:
Tuple::One(0),
event_name:
"BR_MISP_RETIRED.ALL_BRANCHES",
brief_description:
"All mispredicted macro branch instructions retired.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
400009,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(96),
umask:
Tuple::One(1),
event_name:
"OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
brief_description:
"Offcore outstanding Demand Data Read transactions in uncore queue.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("CPL_CYCLES.RING123",
IntelPerformanceCounterDescription{event_code:
Tuple::One(92),
umask:
Tuple::One(2),
event_name:
"CPL_CYCLES.RING123",
brief_description:
"Unhalted core cycles when thread is in rings 1, 2, or 3",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("INT_MISC.RECOVERY_STALLS_COUNT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(13),
umask:
Tuple::One(3),
event_name:
"INT_MISC.RECOVERY_STALLS_COUNT",
brief_description:
"Number of occurences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
false,
any_thread:
false,
edge_detect:
true,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("ITLB_MISSES.STLB_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(133),
umask:
Tuple::One(16),
event_name:
"ITLB_MISSES.STLB_HIT",
brief_description:
"Operations that miss the first ITLB level but hit the second and do not cause any page walks",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("ITLB.ITLB_FLUSH",
IntelPerformanceCounterDescription{event_code:
Tuple::One(174),
umask:
Tuple::One(1),
event_name:
"ITLB.ITLB_FLUSH",
brief_description:
"Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100007,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(210),
umask:
Tuple::One(2),
event_name:
"MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT",
brief_description:
"Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
20011,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::PebsOrRegular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
brief_description:
"Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
68723408897,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_EXECUTED.CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(177),
umask:
Tuple::One(2),
event_name:
"UOPS_EXECUTED.CORE",
brief_description:
"Number of uops executed on the core.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L1D_PEND_MISS.PENDING",
IntelPerformanceCounterDescription{event_code:
Tuple::One(72),
umask:
Tuple::One(1),
event_name:
"L1D_PEND_MISS.PENDING",
brief_description:
"L1D miss oustandings duration in cycles",
public_description:
None,
counter:
Counter::Programmable(4),
counter_ht_off:
Counter::Programmable(4),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("LOAD_HIT_PRE.HW_PF",
IntelPerformanceCounterDescription{event_code:
Tuple::One(76),
umask:
Tuple::One(2),
event_name:
"LOAD_HIT_PRE.HW_PF",
brief_description:
"Not software-prefetch load dispatches that hit FB allocated for hardware prefetch",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("ARITH.FPU_DIV_ACTIVE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(20),
umask:
Tuple::One(1),
event_name:
"ARITH.FPU_DIV_ACTIVE",
brief_description:
"Cycles when divider is busy executing divide operations",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("MOVE_ELIMINATION.SIMD_ELIMINATED",
IntelPerformanceCounterDescription{event_code:
Tuple::One(88),
umask:
Tuple::One(2),
event_name:
"MOVE_ELIMINATION.SIMD_ELIMINATED",
brief_description:
"Number of SIMD Move Elimination candidate uops that were eliminated.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
1000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("L2_L1D_WB_RQSTS.MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(40),
umask:
Tuple::One(1),
event_name:
"L2_L1D_WB_RQSTS.MISS",
brief_description:
"Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
200003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("CPU_CLK_UNHALTED.THREAD_ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(0),
umask:
Tuple::One(2),
event_name:
"CPU_CLK_UNHALTED.THREAD_ANY",
brief_description:
"Core cycles when at least one thread on the physical core is not in halt state",
public_description:
None,
counter:
Counter::Fixed(4),
counter_ht_off:
Counter::Fixed(4),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
true,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("UOPS_EXECUTED.STALL_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(177),
umask:
Tuple::One(1),
event_name:
"UOPS_EXECUTED.STALL_CYCLES",
brief_description:
"Counts number of cycles no uops were dispatched to be executed on this thread.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
1,
invert:
true,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,}),
("OFFCORE_RESPONSE.ALL_READS.LLC_MISS.DRAM",
IntelPerformanceCounterDescription{event_code:
Tuple::Two(183,
187),
umask:
Tuple::One(1),
event_name:
"OFFCORE_RESPONSE.ALL_READS.LLC_MISS.DRAM",
brief_description:
"Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data returned from dram",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(15),
pebs_counters:
None,
sample_after_value:
100003,
msr_index:
MSRIndex::Two(166,
167),
msr_value:
12889097207,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
true,
unit:
None,
filter:
None,
extsel:
false,}),
("ICACHE.HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(128),
umask:
Tuple::One(1),
event_name:
"ICACHE.HIT",
brief_description:
"Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Programmable(255),
pebs_counters:
None,
sample_after_value:
2000003,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
None,
filter:
None,
extsel:
false,})]),}