pub const HASWELLX_UNCORE: Map<&'static str, IntelPerformanceCounterDescription> = ::phf::Map{key: 1897749892740154578,
disps:
::phf::Slice::Static(&[(0, 26), (0, 240), (0, 0), (0, 385),
(0, 7), (0, 275), (0, 186), (0, 70),
(0, 304), (0, 261), (0, 22), (0, 38),
(0, 10), (2, 1068), (0, 0), (0, 1),
(1, 654), (0, 778), (0, 1), (0, 578),
(1, 950), (0, 0), (0, 395), (0, 236),
(0, 0), (0, 4), (0, 6), (0, 38),
(0, 65), (0, 4), (0, 0), (0, 0), (0, 0),
(0, 2), (0, 513), (0, 40), (0, 1),
(0, 9), (0, 0), (1, 52), (0, 30),
(0, 30), (0, 18), (0, 78), (1, 1160),
(0, 90), (0, 28), (1, 30), (0, 107),
(0, 778), (0, 54), (0, 17), (0, 176),
(1, 1164), (0, 143), (0, 11), (0, 631),
(5, 1197), (0, 953), (0, 107), (0, 751),
(0, 112), (0, 19), (0, 0), (0, 93),
(2, 759), (0, 0), (0, 24), (5, 1199),
(0, 126), (0, 21), (0, 8), (0, 26),
(0, 944), (0, 2), (2, 755), (0, 6),
(0, 0), (0, 321), (0, 19), (0, 37),
(0, 1095), (0, 42), (0, 55), (0, 308),
(0, 0), (0, 20), (0, 96), (0, 13),
(0, 0), (0, 16), (0, 662), (0, 16),
(0, 13), (0, 542), (0, 347), (0, 63),
(0, 4), (0, 326), (0, 1), (0, 385),
(0, 115), (0, 4), (0, 0), (0, 20),
(1, 642), (0, 25), (0, 36), (0, 12),
(1, 613), (0, 341), (0, 1), (0, 13),
(0, 30), (0, 30), (0, 22), (1, 896),
(0, 177), (0, 208), (0, 1), (1, 847),
(0, 214), (4, 965), (0, 709), (1, 193),
(0, 0), (0, 68), (1, 292), (0, 273),
(0, 20), (2, 796), (1, 1103), (0, 467),
(0, 409), (1, 54), (0, 673), (0, 98),
(0, 333), (0, 489), (0, 1), (0, 0),
(0, 651), (0, 319), (0, 22), (0, 8),
(0, 60), (0, 40), (0, 31), (0, 76),
(0, 191), (1, 104), (0, 271), (0, 0),
(0, 1216), (6, 399), (0, 2), (0, 57),
(2, 685), (0, 26), (0, 2), (1, 158),
(0, 239), (0, 159), (0, 106), (0, 43),
(0, 117), (0, 550), (0, 53), (0, 88),
(0, 507), (0, 109), (0, 21), (0, 29),
(0, 41), (1, 34), (0, 3), (0, 312),
(0, 40), (0, 0), (0, 11), (0, 115),
(0, 10), (0, 0), (0, 748), (12, 14),
(3, 1248), (0, 19), (0, 1033), (0, 0),
(5, 197), (0, 3), (0, 0), (0, 1083),
(2, 556), (1, 461), (0, 10), (0, 778),
(3, 949), (27, 144), (0, 3), (0, 700),
(0, 256), (0, 29), (3, 745), (0, 420),
(0, 8), (0, 0), (0, 28), (1, 1150),
(0, 226), (0, 10), (4, 512), (0, 34),
(1, 351), (0, 73), (6, 899), (0, 451),
(0, 1), (0, 308), (0, 1), (0, 0),
(0, 451), (2, 557), (6, 833), (4, 56),
(0, 0), (0, 21), (32, 69), (0, 1),
(0, 144), (0, 11), (1, 239), (0, 3),
(0, 72), (0, 650), (27, 510), (2, 250),
(5, 821), (2, 389), (0, 218), (0, 263),
(0, 3), (0, 3), (26, 474), (92, 726),
(5, 334), (0, 7), (0, 66), (13, 912),
(0, 138), (5, 1061), (0, 33), (0, 3),
(0, 20), (0, 4), (20, 1012)]),
entries:
::phf::Slice::Static(&[("UNC_C_RING_BOUNCES.AK",
IntelPerformanceCounterDescription{event_code:
Tuple::One(5),
umask:
Tuple::One(2),
event_name:
"UNC_C_RING_BOUNCES.AK",
brief_description:
"Number of LLC responses that bounced on the Ring.; AK",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK7.ALLBANKS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(16),
event_name:
"UNC_M_RD_CAS_RANK7.ALLBANKS",
brief_description:
"RD_CAS Access to Rank 7; All Banks",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxL_FLITS_G1.DRS_NONDATA",
IntelPerformanceCounterDescription{event_code:
Tuple::One(0),
umask:
Tuple::One(16),
event_name:
"UNC_Q_TxL_FLITS_G1.DRS_NONDATA",
brief_description:
"Flits Transferred - Group 1; DRS Header Flits",
public_description:
Some("Counts the number of flits trasmitted across the QPI Link. This is one of three \'groups\' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each \'flit\' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four \'fits\', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI \'speed\' (for example, 8.0 GT/s), the \'transfers\' here refer to \'fits\'. Therefore, in L0, the system will transfer 1 \'flit\' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as \'data\' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual \'data\' and an additional 16 bits of other information. To calculate \'data\' bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of protocol flits transmitted over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits transmitted over the NCB channel which transmits non-coherent data. This includes only the header flits (not the data). This includes extended headers."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_Q_RxL_STALLS_VN1.BGF_HOM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(58),
umask:
Tuple::One(8),
event_name:
"UNC_Q_RxL_STALLS_VN1.BGF_HOM",
brief_description:
"Stalls Sending to R3QPI on VN1; BGF Stall - DRS",
public_description:
Some("Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the DRS message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_P_FREQ_BAND1_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(12),
umask:
Tuple::One(0),
event_name:
"UNC_P_FREQ_BAND1_CYCLES",
brief_description:
"Frequency Residency",
public_description:
Some("Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter. One can use all four counters with this event, so it is possible to track up to 4 configurable bands. One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
Some("PCUFilter[15:8]"),
extsel:
false,}),
("UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN2",
IntelPerformanceCounterDescription{event_code:
Tuple::One(22),
umask:
Tuple::One(4),
event_name:
"UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN2",
brief_description:
"iMC RPQ Credits Empty - Special; Channel 2",
public_description:
Some("Counts the number of cycles when there are no \'special\' credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC\'s RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and \'special\' requests such as ISOCH reads. This count only tracks the \'special\' credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK7.BANKG2",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(19),
event_name:
"UNC_M_RD_CAS_RANK7.BANKG2",
brief_description:
"RD_CAS Access to Rank 7; Bank Group 2 (Banks 8-11)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_R3_VNA_CREDITS_REJECT.NCS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(52),
umask:
Tuple::One(32),
event_name:
"UNC_R3_VNA_CREDITS_REJECT.NCS",
brief_description:
"VNA Credit Reject; NCS Message Class",
public_description:
Some("Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Non-Coherent Standard (NCS)."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_C_LLC_LOOKUP.REMOTE_SNOOP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(52),
umask:
Tuple::One(9),
event_name:
"UNC_C_LLC_LOOKUP.REMOTE_SNOOP",
brief_description:
"Cache Lookups; External Snoop Request",
public_description:
Some("Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Filters for only snoop requests coming from the remote socket(s) through the IPQ."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
Some("CBoFilter0[23:17]"),
extsel:
false,}),
("UNC_M_DCLOCKTICKS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(0),
umask:
Tuple::One(0),
event_name:
"UNC_M_DCLOCKTICKS",
brief_description:
"DRAM Clockticks",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_C_RING_AK_USED.UP_EVEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(28),
umask:
Tuple::One(1),
event_name:
"UNC_C_RING_AK_USED.UP_EVEN",
brief_description:
"AK Ring In Use; Up and Even",
public_description:
Some("Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the \'UP\' direction is on the clockwise ring and \'DN\' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK1.BANKG0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(185),
umask:
Tuple::One(17),
event_name:
"UNC_M_WR_CAS_RANK1.BANKG0",
brief_description:
"WR_CAS Access to Rank 1; Bank Group 0 (Banks 0-3)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxR_AD_HOM_CREDIT_ACQUIRED.VN0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(38),
umask:
Tuple::One(1),
event_name:
"UNC_Q_TxR_AD_HOM_CREDIT_ACQUIRED.VN0",
brief_description:
"R3QPI Egress Credit Occupancy - HOM; for VN0",
public_description:
Some("Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Home messages on AD."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_R3_SBO0_CREDITS_ACQUIRED.BL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(40),
umask:
Tuple::One(2),
event_name:
"UNC_R3_SBO0_CREDITS_ACQUIRED.BL",
brief_description:
"SBo0 Credits Acquired; For BL Ring",
public_description:
Some("Number of Sbo 0 credits acquired in a given cycle, per ring."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK5.BANKG2",
IntelPerformanceCounterDescription{event_code:
Tuple::One(189),
umask:
Tuple::One(19),
event_name:
"UNC_M_WR_CAS_RANK5.BANKG2",
brief_description:
"WR_CAS Access to Rank 5; Bank Group 2 (Banks 8-11)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_H_SBO1_CREDIT_OCCUPANCY.BL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(107),
umask:
Tuple::One(2),
event_name:
"UNC_H_SBO1_CREDIT_OCCUPANCY.BL",
brief_description:
"SBo1 Credits Occupancy; For BL Ring",
public_description:
Some("Number of Sbo 1 credits in use in a given cycle, per ring."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_C_RING_AK_USED.DOWN_ODD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(28),
umask:
Tuple::One(8),
event_name:
"UNC_C_RING_AK_USED.DOWN_ODD",
brief_description:
"AK Ring In Use; Down and Odd",
public_description:
Some("Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the \'UP\' direction is on the clockwise ring and \'DN\' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK6.BANKG2",
IntelPerformanceCounterDescription{event_code:
Tuple::One(182),
umask:
Tuple::One(19),
event_name:
"UNC_M_RD_CAS_RANK6.BANKG2",
brief_description:
"RD_CAS Access to Rank 6; Bank Group 2 (Banks 8-11)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_H_HITME_HIT.ALLOCS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(113),
umask:
Tuple::One(112),
event_name:
"UNC_H_HITME_HIT.ALLOCS",
brief_description:
"Counts Number of Hits in HitMe Cache; Allocations",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_R3_RING_BL_USED.CCW_ODD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(9),
umask:
Tuple::One(8),
event_name:
"UNC_R3_RING_BL_USED.CCW_ODD",
brief_description:
"R3 BL Ring in Use; Counterclockwise and Odd",
public_description:
Some("Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity."),
counter:
Counter::Programmable(7),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_I_MISC0.PF_TIMEOUT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(20),
umask:
Tuple::One(128),
event_name:
"UNC_I_MISC0.PF_TIMEOUT",
brief_description:
"Misc Events - Set 0; Prefetch TimeOut",
public_description:
Some("Indicates the fetch for a previous prefetch wasn\'t accepted by the prefetch. This happens in the case of a prefetch TimeOut"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK1.BANK3",
IntelPerformanceCounterDescription{event_code:
Tuple::One(185),
umask:
Tuple::One(3),
event_name:
"UNC_M_WR_CAS_RANK1.BANK3",
brief_description:
"WR_CAS Access to Rank 1; Bank 3",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK1.BANK2",
IntelPerformanceCounterDescription{event_code:
Tuple::One(185),
umask:
Tuple::One(2),
event_name:
"UNC_M_WR_CAS_RANK1.BANK2",
brief_description:
"WR_CAS Access to Rank 1; Bank 2",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_CYCLES_NE_NDR.VN1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(20),
umask:
Tuple::One(2),
event_name:
"UNC_Q_RxL_CYCLES_NE_NDR.VN1",
brief_description:
"RxQ Cycles Not Empty - NDR; for VN1",
public_description:
Some("Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NDR flits only."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_U_U2C_EVENTS.UMC",
IntelPerformanceCounterDescription{event_code:
Tuple::One(67),
umask:
Tuple::One(32),
event_name:
"UNC_U_U2C_EVENTS.UMC",
brief_description:
"Monitor Sent to T0; Uncorrectable Machine Check",
public_description:
Some("Events coming from Uncore can be sent to one or all cores"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("UBOX"),
filter:
None,
extsel:
false,}),
("UNC_M_WMM_TO_RMM.VMSE_RETRY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(192),
umask:
Tuple::One(4),
event_name:
"UNC_M_WMM_TO_RMM.VMSE_RETRY",
brief_description:
"Transition from WMM to RMM because of low threshold",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_C_TOR_INSERTS.NID_EVICTION",
IntelPerformanceCounterDescription{event_code:
Tuple::One(53),
umask:
Tuple::One(68),
event_name:
"UNC_C_TOR_INSERTS.NID_EVICTION",
brief_description:
"TOR Inserts; NID Matched Evictions",
public_description:
Some("Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent \'filters\' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select \'MISS_OPC_MATCH\' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; NID matched eviction transactions inserted into the TOR."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
Some("CBoFilter1[15:0]"),
extsel:
false,}),
("UNC_C_RxR_OCCUPANCY.IRQ_REJECTED",
IntelPerformanceCounterDescription{event_code:
Tuple::One(17),
umask:
Tuple::One(2),
event_name:
"UNC_C_RxR_OCCUPANCY.IRQ_REJECTED",
brief_description:
"IRQ Rejected",
public_description:
Some("Counts number of entries in the specified Ingress queue in each cycle.;RTLSignal: PmonIrqQualRejAllocU119H[0];Additional Notes: IRQ_REJECTED should not be Ored with the other umasks."),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_R3_VN0_CREDITS_REJECT.HOM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(55),
umask:
Tuple::One(1),
event_name:
"UNC_R3_VN0_CREDITS_REJECT.HOM",
brief_description:
"VN0 Credit Acquisition Failed on DRS; HOM Message Class",
public_description:
Some("Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_R3_RING_AK_USED.CW",
IntelPerformanceCounterDescription{event_code:
Tuple::One(8),
umask:
Tuple::One(3),
event_name:
"UNC_R3_RING_AK_USED.CW",
brief_description:
"R3 AK Ring in Use; Clockwise",
public_description:
Some("Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop."),
counter:
Counter::Programmable(7),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_R2_RING_AD_USED.CCW",
IntelPerformanceCounterDescription{event_code:
Tuple::One(7),
umask:
Tuple::One(12),
event_name:
"UNC_R2_RING_AD_USED.CCW",
brief_description:
"R2 AD Ring in Use; Counterclockwise",
public_description:
Some("Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_STARVED.BL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(109),
umask:
Tuple::One(2),
event_name:
"UNC_H_TxR_STARVED.BL",
brief_description:
"Injection Starvation; For BL Ring",
public_description:
Some("Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxR_AK_NDR_CREDIT_ACQUIRED",
IntelPerformanceCounterDescription{event_code:
Tuple::One(41),
umask:
Tuple::One(0),
event_name:
"UNC_Q_TxR_AK_NDR_CREDIT_ACQUIRED",
brief_description:
"R3QPI Egress Credit Occupancy - AK NDR",
public_description:
Some("Number of credits into the R3 (for transactions across the BGF) acquired each cycle. Local NDR message class to AK Egress."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_S_RING_AD_USED.DOWN_ODD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(27),
umask:
Tuple::One(8),
event_name:
"UNC_S_RING_AD_USED.DOWN_ODD",
brief_description:
"AD Ring In Use; Down and Odd",
public_description:
Some("Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the \'UP\' direction is on the clockwise ring and \'DN\' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK6.BANK2",
IntelPerformanceCounterDescription{event_code:
Tuple::One(190),
umask:
Tuple::One(2),
event_name:
"UNC_M_WR_CAS_RANK6.BANK2",
brief_description:
"WR_CAS Access to Rank 6; Bank 2",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_R2_RING_AD_USED.CW_EVEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(7),
umask:
Tuple::One(1),
event_name:
"UNC_R2_RING_AD_USED.CW_EVEN",
brief_description:
"R2 AD Ring in Use; Clockwise and Even",
public_description:
Some("Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_STALLS_VN0.BGF_DRS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(53),
umask:
Tuple::One(1),
event_name:
"UNC_Q_RxL_STALLS_VN0.BGF_DRS",
brief_description:
"Stalls Sending to R3QPI on VN0; BGF Stall - HOM",
public_description:
Some("Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the HOM message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_M_RD_CAS_RANK6.BANK9",
IntelPerformanceCounterDescription{event_code:
Tuple::One(182),
umask:
Tuple::One(9),
event_name:
"UNC_M_RD_CAS_RANK6.BANK9",
brief_description:
"RD_CAS Access to Rank 6; Bank 9",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_R3_VN1_CREDITS_USED.SNP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(56),
umask:
Tuple::One(2),
event_name:
"UNC_R3_VN1_CREDITS_USED.SNP",
brief_description:
"VN1 Credit Used; SNP Message Class",
public_description:
Some("Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_AD.HOM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(15),
umask:
Tuple::One(4),
event_name:
"UNC_H_TxR_AD.HOM",
brief_description:
"Outbound NDR Ring Transactions; Non-data Responses",
public_description:
Some("Counts the number of outbound transactions on the AD ring. This can be filtered by the NDR and SNP message classes. See the filter descriptions for more details.; Filter for outbound NDR transactions sent on the AD ring. NDR stands for \'non-data response\' and is generally used for completions that do not include data. AD NDR is used for transactions to remote sockets."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK4.BANK7",
IntelPerformanceCounterDescription{event_code:
Tuple::One(180),
umask:
Tuple::One(7),
event_name:
"UNC_M_RD_CAS_RANK4.BANK7",
brief_description:
"RD_CAS Access to Rank 4; Bank 7",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_ACT_COUNT.RD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(1),
umask:
Tuple::One(1),
event_name:
"UNC_M_ACT_COUNT.RD",
brief_description:
"DRAM Activate Count; Activate due to Read",
public_description:
Some("Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_R2_IIO_CREDITS_USED.DRS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(50),
umask:
Tuple::One(8),
event_name:
"UNC_R2_IIO_CREDITS_USED.DRS",
brief_description:
"R2PCIe IIO Credits in Use; DRS",
public_description:
Some("Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the DRS message class."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK1.BANK15",
IntelPerformanceCounterDescription{event_code:
Tuple::One(177),
umask:
Tuple::One(15),
event_name:
"UNC_M_RD_CAS_RANK1.BANK15",
brief_description:
"RD_CAS Access to Rank 1; Bank 15",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_C_RxR_INT_STARVED.ISMQ",
IntelPerformanceCounterDescription{event_code:
Tuple::One(20),
umask:
Tuple::One(8),
event_name:
"UNC_C_RxR_INT_STARVED.ISMQ",
brief_description:
"Ingress Internal Starvation Cycles; ISMQ",
public_description:
Some("Counts cycles in internal starvation. This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.; Cycles with the ISMQ in Internal Starvation."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_R3_VN1_CREDITS_REJECT.NCB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(57),
umask:
Tuple::One(16),
event_name:
"UNC_R3_VN1_CREDITS_REJECT.NCB",
brief_description:
"VN1 Credit Acquisition Failed on DRS; NCB Message Class",
public_description:
Some("Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_Q_DIRECT2CORE.FAILURE_CREDITS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(19),
umask:
Tuple::One(2),
event_name:
"UNC_Q_DIRECT2CORE.FAILURE_CREDITS",
brief_description:
"Direct 2 Core Spawning; Spawn Failure - Egress Credits",
public_description:
Some("Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exlusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because there were not enough Egress credits. Had there been enough credits, the spawn would have worked as the RBT bit was set and the RBT tag matched."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_I_TxR_BL_STALL_CREDIT_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(25),
umask:
Tuple::One(0),
event_name:
"UNC_I_TxR_BL_STALL_CREDIT_CYCLES",
brief_description:
"No BL Egress Credit Stalls",
public_description:
Some("Counts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK0.ALLBANKS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(184),
umask:
Tuple::One(16),
event_name:
"UNC_M_WR_CAS_RANK0.ALLBANKS",
brief_description:
"WR_CAS Access to Rank 0; All Banks",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_R2_IIO_CREDITS_USED.NCB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(50),
umask:
Tuple::One(16),
event_name:
"UNC_R2_IIO_CREDITS_USED.NCB",
brief_description:
"R2PCIe IIO Credits in Use; NCB",
public_description:
Some("Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCB message class."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO3",
IntelPerformanceCounterDescription{event_code:
Tuple::One(34),
umask:
Tuple::One(8),
event_name:
"UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO3",
brief_description:
"CBox AD Credits Empty",
public_description:
Some("No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 3"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_NDR",
IntelPerformanceCounterDescription{event_code:
Tuple::One(32),
umask:
Tuple::One(64),
event_name:
"UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_NDR",
brief_description:
"QPI0 AD Credits Empty",
public_description:
Some("No credits available to send to QPI0 on the AD Ring; VN1 NDR Messages"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK4.BANK11",
IntelPerformanceCounterDescription{event_code:
Tuple::One(180),
umask:
Tuple::One(11),
event_name:
"UNC_M_RD_CAS_RANK4.BANK11",
brief_description:
"RD_CAS Access to Rank 4; Bank 11",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_P_CORE5_TRANSITION_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(101),
umask:
Tuple::One(0),
event_name:
"UNC_P_CORE5_TRANSITION_CYCLES",
brief_description:
"Core C State Transition Cycles",
public_description:
Some("Number of cycles spent performing core C state transitions. There is one event per core."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(34),
umask:
Tuple::One(8),
event_name:
"UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI1",
brief_description:
"Cycles without QPI Ingress Credits; BL to QPI Link 1",
public_description:
Some("Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent. This can be filtered by the different credit pools and the different links."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN_SHR",
IntelPerformanceCounterDescription{event_code:
Tuple::One(42),
umask:
Tuple::One(4),
event_name:
"UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN_SHR",
brief_description:
"R3QPI Egress Credit Occupancy - DRS; for Shared VN",
public_description:
Some("Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_P_POWER_STATE_OCCUPANCY.CORES_C6",
IntelPerformanceCounterDescription{event_code:
Tuple::One(128),
umask:
Tuple::One(192),
event_name:
"UNC_P_POWER_STATE_OCCUPANCY.CORES_C6",
brief_description:
"Number of cores in C-State; C6 and C7",
public_description:
Some("This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_R3_RING_BL_USED.CW_ODD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(9),
umask:
Tuple::One(2),
event_name:
"UNC_R3_RING_BL_USED.CW_ODD",
brief_description:
"R3 BL Ring in Use; Clockwise and Odd",
public_description:
Some("Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity."),
counter:
Counter::Programmable(7),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_P_PROCHOT_INTERNAL_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(9),
umask:
Tuple::One(0),
event_name:
"UNC_P_PROCHOT_INTERNAL_CYCLES",
brief_description:
"Internal Prochot",
public_description:
Some("Counts the number of cycles that we are in Interal PROCHOT mode. This mode is triggered when a sensor on the die determines that we are too hot and must throttle to avoid damaging the chip."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_P_FREQ_MAX_OS_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(6),
umask:
Tuple::One(0),
event_name:
"UNC_P_FREQ_MAX_OS_CYCLES",
brief_description:
"OS Strongest Upper Limit Cycles",
public_description:
Some("Counts the number of cycles when the OS is the upper limit on frequency."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK6.BANK2",
IntelPerformanceCounterDescription{event_code:
Tuple::One(182),
umask:
Tuple::One(2),
event_name:
"UNC_M_RD_CAS_RANK6.BANK2",
brief_description:
"RD_CAS Access to Rank 6; Bank 2",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_R2_RING_AK_USED.CW_EVEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(8),
umask:
Tuple::One(1),
event_name:
"UNC_R2_RING_AK_USED.CW_EVEN",
brief_description:
"R2 AK Ring in Use; Clockwise and Even",
public_description:
Some("Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_H_RING_BL_USED.CW",
IntelPerformanceCounterDescription{event_code:
Tuple::One(64),
umask:
Tuple::One(3),
event_name:
"UNC_H_RING_BL_USED.CW",
brief_description:
"HA BL Ring in Use; Clockwise",
public_description:
Some("Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK1.BANKG3",
IntelPerformanceCounterDescription{event_code:
Tuple::One(185),
umask:
Tuple::One(20),
event_name:
"UNC_M_WR_CAS_RANK1.BANKG3",
brief_description:
"WR_CAS Access to Rank 1; Bank Group 3 (Banks 12-15)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxL_FLITS_G1.DRS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(0),
umask:
Tuple::One(24),
event_name:
"UNC_Q_TxL_FLITS_G1.DRS",
brief_description:
"Flits Transferred - Group 1; DRS Flits (both Header and Data)",
public_description:
Some("Counts the number of flits trasmitted across the QPI Link. This is one of three \'groups\' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each \'flit\' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four \'fits\', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI \'speed\' (for example, 8.0 GT/s), the \'transfers\' here refer to \'fits\'. Therefore, in L0, the system will transfer 1 \'flit\' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as \'data\' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual \'data\' and an additional 16 bits of other information. To calculate \'data\' bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_C_BOUNCE_CONTROL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(10),
umask:
Tuple::One(0),
event_name:
"UNC_C_BOUNCE_CONTROL",
brief_description:
"Bounce Control",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_H_SNOOP_OCCUPANCY.REMOTE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(9),
umask:
Tuple::One(2),
event_name:
"UNC_H_SNOOP_OCCUPANCY.REMOTE",
brief_description:
"Tracker Snoops Outstanding Accumulator; Remote Requests",
public_description:
Some("Accumulates the occupancy of either the local HA tracker pool that have snoops pending in every cycle. This can be used in conjection with the \'not empty\' stat to calculate average queue occupancy or the \'allocations\' stat in order to calculate average queue latency. HA trackers are allocated as soon as a request enters the HA if an HT (HomeTracker) entry is available and this occupancy is decremented when all the snoop responses have returned.; This filter includes only requests coming from remote sockets."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_OCCUPANCY_HOM.VN0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(24),
umask:
Tuple::One(1),
event_name:
"UNC_Q_RxL_OCCUPANCY_HOM.VN0",
brief_description:
"RxQ Occupancy - HOM; for VN0",
public_description:
Some("Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors HOM flits only."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_H_RING_AD_USED.CCW_ODD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(62),
umask:
Tuple::One(8),
event_name:
"UNC_H_RING_AD_USED.CCW_ODD",
brief_description:
"HA AD Ring in Use; Counterclockwise and Odd",
public_description:
Some("Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(42),
umask:
Tuple::One(2),
event_name:
"UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN1",
brief_description:
"R3QPI Egress Credit Occupancy - DRS; for VN1",
public_description:
Some("Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_HOM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(32),
umask:
Tuple::One(16),
event_name:
"UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_HOM",
brief_description:
"QPI0 AD Credits Empty",
public_description:
Some("No credits available to send to QPI0 on the AD Ring; VN1 HOM Messages"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_OCCUPANCY_NDR.VN1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(26),
umask:
Tuple::One(2),
event_name:
"UNC_Q_RxL_OCCUPANCY_NDR.VN1",
brief_description:
"RxQ Occupancy - NDR; for VN1",
public_description:
Some("Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NDR flits only."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_Q_TxL_OCCUPANCY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(7),
umask:
Tuple::One(0),
event_name:
"UNC_Q_TxL_OCCUPANCY",
brief_description:
"Tx Flit Buffer Occupancy",
public_description:
Some("Accumulates the number of flits in the TxQ. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This can be used with the cycles not empty event to track average occupancy, or the allocations event to track average lifetime in the TxQ."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK0.BANK3",
IntelPerformanceCounterDescription{event_code:
Tuple::One(176),
umask:
Tuple::One(3),
event_name:
"UNC_M_RD_CAS_RANK0.BANK3",
brief_description:
"RD_CAS Access to Rank 0; Bank 3",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO11",
IntelPerformanceCounterDescription{event_code:
Tuple::One(31),
umask:
Tuple::One(8),
event_name:
"UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO11",
brief_description:
"CBox AD Credits Empty",
public_description:
Some("No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 11"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxL_CRC_NO_CREDITS.FULL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(2),
umask:
Tuple::One(1),
event_name:
"UNC_Q_TxL_CRC_NO_CREDITS.FULL",
brief_description:
"Cycles Stalled with no LLR Credits; LLR is full",
public_description:
Some("Number of cycles when the Tx side ran out of Link Layer Retry credits, causing the Tx to stall.; When LLR is totally full, we are not allowed to send any packets."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_R3_HA_R2_BL_CREDITS_EMPTY.R2_NCS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(45),
umask:
Tuple::One(8),
event_name:
"UNC_R3_HA_R2_BL_CREDITS_EMPTY.R2_NCS",
brief_description:
"HA/R2 AD Credits Empty",
public_description:
Some("No credits available to send to either HA or R2 on the BL Ring; R2 NCS Messages"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_H_HITME_HIT.RSPFWDI_LOCAL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(113),
umask:
Tuple::One(32),
event_name:
"UNC_H_HITME_HIT.RSPFWDI_LOCAL",
brief_description:
"Counts Number of Hits in HitMe Cache; op is RspIFwd or RspIFwdWb for a local request",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_C_RING_SINK_STARVED.IV",
IntelPerformanceCounterDescription{event_code:
Tuple::One(6),
umask:
Tuple::One(8),
event_name:
"UNC_C_RING_SINK_STARVED.IV",
brief_description:
"IV",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_C_TOR_INSERTS.MISS_LOCAL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(53),
umask:
Tuple::One(42),
event_name:
"UNC_C_TOR_INSERTS.MISS_LOCAL",
brief_description:
"TOR Inserts; Misses to Local Memory",
public_description:
Some("Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent \'filters\' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select \'MISS_OPC_MATCH\' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that are satisifed by locally HOMed memory."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_R3_SBO1_CREDITS_ACQUIRED.BL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(41),
umask:
Tuple::One(2),
event_name:
"UNC_R3_SBO1_CREDITS_ACQUIRED.BL",
brief_description:
"SBo1 Credits Acquired; For BL Ring",
public_description:
Some("Number of Sbo 1 credits acquired in a given cycle, per ring."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_S_FAST_ASSERTED",
IntelPerformanceCounterDescription{event_code:
Tuple::One(9),
umask:
Tuple::One(0),
event_name:
"UNC_S_FAST_ASSERTED",
brief_description:
"FaST wire asserted",
public_description:
Some("Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_OCCUPANCY_NDR.VN0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(26),
umask:
Tuple::One(1),
event_name:
"UNC_Q_RxL_OCCUPANCY_NDR.VN0",
brief_description:
"RxQ Occupancy - NDR; for VN0",
public_description:
Some("Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NDR flits only."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_Q_RxL_FLITS_G1.DRS_DATA",
IntelPerformanceCounterDescription{event_code:
Tuple::One(2),
umask:
Tuple::One(8),
event_name:
"UNC_Q_RxL_FLITS_G1.DRS_DATA",
brief_description:
"Flits Received - Group 1; DRS Data Flits",
public_description:
Some("Counts the number of flits received from the QPI Link. This is one of three \'groups\' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each \'flit\' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four \'fits\', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI \'speed\' (for example, 8.0 GT/s), the \'transfers\' here refer to \'fits\'. Therefore, in L0, the system will transfer 1 \'flit\' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as \'data\' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual \'data\' and an additional 16 bits of other information. To calculate \'data\' bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of data flits received over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits received over the NCB channel which transmits non-coherent data. This includes only the data flits (not the header)."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_C_RxR_IRQ_RETRY.NID",
IntelPerformanceCounterDescription{event_code:
Tuple::One(50),
umask:
Tuple::One(64),
event_name:
"UNC_C_RxR_IRQ_RETRY.NID",
brief_description:
"Ingress Request Queue Rejects",
public_description:
Some("Qualify one of the other subevents by a given RTID destination NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER1.nid."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
Some("CBoFilter1[15:0]"),
extsel:
false,}),
("UNC_R3_RING_AD_USED.CCW",
IntelPerformanceCounterDescription{event_code:
Tuple::One(7),
umask:
Tuple::One(12),
event_name:
"UNC_R3_RING_AD_USED.CCW",
brief_description:
"R3 AD Ring in Use; Counterclockwise",
public_description:
Some("Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop."),
counter:
Counter::Programmable(7),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_C_RING_BL_USED.DOWN_ODD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(29),
umask:
Tuple::One(8),
event_name:
"UNC_C_RING_BL_USED.DOWN_ODD",
brief_description:
"BL Ring in Use; Down and Odd",
public_description:
Some("Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the \'UP\' direction is on the clockwise ring and \'DN\' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_BL_CYCLES_NE.SCHED1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(53),
umask:
Tuple::One(2),
event_name:
"UNC_H_TxR_BL_CYCLES_NE.SCHED1",
brief_description:
"BL Egress Not Empty; Scheduler 1",
public_description:
Some("BL Egress Not Empty; Filter for cycles not empty from scheduler bank 1"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK5.BANK7",
IntelPerformanceCounterDescription{event_code:
Tuple::One(181),
umask:
Tuple::One(7),
event_name:
"UNC_M_RD_CAS_RANK5.BANK7",
brief_description:
"RD_CAS Access to Rank 5; Bank 7",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK7.BANK10",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(10),
event_name:
"UNC_M_RD_CAS_RANK7.BANK10",
brief_description:
"RD_CAS Access to Rank 7; Bank 10",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_C_RxR_ISMQ_RETRY.IIO_CREDITS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(51),
umask:
Tuple::One(32),
event_name:
"UNC_C_RxR_ISMQ_RETRY.IIO_CREDITS",
brief_description:
"ISMQ Retries; No IIO Credits",
public_description:
Some("Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Number of times a request attempted to acquire the NCS/NCB credit for sending messages on BL to the IIO. There is a single credit in each CBo that is shared between the NCS and NCB message classes for sending transactions on the BL ring (such as read data) to the IIO."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK4.BANK6",
IntelPerformanceCounterDescription{event_code:
Tuple::One(188),
umask:
Tuple::One(6),
event_name:
"UNC_M_WR_CAS_RANK4.BANK6",
brief_description:
"WR_CAS Access to Rank 4; Bank 6",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_H_HITME_HIT_PV_BITS_SET.ALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(114),
umask:
Tuple::One(255),
event_name:
"UNC_H_HITME_HIT_PV_BITS_SET.ALL",
brief_description:
"Accumulates Number of PV bits set on HitMe Cache Hits; All Requests",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_C_RxR_INT_STARVED.IPQ",
IntelPerformanceCounterDescription{event_code:
Tuple::One(20),
umask:
Tuple::One(4),
event_name:
"UNC_C_RxR_INT_STARVED.IPQ",
brief_description:
"Ingress Internal Starvation Cycles; IPQ",
public_description:
Some("Counts cycles in internal starvation. This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.; Cycles with the IPQ in Internal Starvation."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK0.BANK14",
IntelPerformanceCounterDescription{event_code:
Tuple::One(176),
umask:
Tuple::One(14),
event_name:
"UNC_M_RD_CAS_RANK0.BANK14",
brief_description:
"RD_CAS Access to Rank 0; Bank 14",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_R3_RING_SINK_STARVED.AK",
IntelPerformanceCounterDescription{event_code:
Tuple::One(14),
umask:
Tuple::One(2),
event_name:
"UNC_R3_RING_SINK_STARVED.AK",
brief_description:
"Ring Stop Starved; AK",
public_description:
Some("Number of cycles the ringstop is in starvation (per ring)"),
counter:
Counter::Programmable(7),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_R3_RING_IV_USED.ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(10),
umask:
Tuple::One(15),
event_name:
"UNC_R3_RING_IV_USED.ANY",
brief_description:
"R3 IV Ring in Use; Any",
public_description:
Some("Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop."),
counter:
Counter::Programmable(7),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_OCCUPANCY_NCS.VN0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(23),
umask:
Tuple::One(1),
event_name:
"UNC_Q_RxL_OCCUPANCY_NCS.VN0",
brief_description:
"RxQ Occupancy - NCS; for VN0",
public_description:
Some("Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCS flits only."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_I_MISC0.FAST_XFER",
IntelPerformanceCounterDescription{event_code:
Tuple::One(20),
umask:
Tuple::One(32),
event_name:
"UNC_I_MISC0.FAST_XFER",
brief_description:
"Misc Events - Set 0; Fastpath Transfers From Primary to Secondary",
public_description:
None,
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK4.BANKG1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(180),
umask:
Tuple::One(18),
event_name:
"UNC_M_RD_CAS_RANK4.BANKG1",
brief_description:
"RD_CAS Access to Rank 4; Bank Group 1 (Banks 4-7)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_I_COHERENT_OPS.DRD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(19),
umask:
Tuple::One(4),
event_name:
"UNC_I_COHERENT_OPS.DRD",
brief_description:
"Coherent Ops; DRd",
public_description:
Some("Counts the number of coherency related operations servied by the IRP"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_R3_TxR_NACK.DN_AD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(38),
umask:
Tuple::One(1),
event_name:
"UNC_R3_TxR_NACK.DN_AD",
brief_description:
"Egress CCW NACK; AD CCW",
public_description:
Some("AD CounterClockwise Egress Queue"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_OCCUPANCY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(11),
umask:
Tuple::One(0),
event_name:
"UNC_Q_RxL_OCCUPANCY",
brief_description:
"RxQ Occupancy - All Packets",
public_description:
Some("Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK7.BANK9",
IntelPerformanceCounterDescription{event_code:
Tuple::One(191),
umask:
Tuple::One(9),
event_name:
"UNC_M_WR_CAS_RANK7.BANK9",
brief_description:
"WR_CAS Access to Rank 7; Bank 9",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_I_MISC1.LOST_FWD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(21),
umask:
Tuple::One(16),
event_name:
"UNC_I_MISC1.LOST_FWD",
brief_description:
"Misc Events - Set 1",
public_description:
None,
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_C_RING_AK_USED.UP_ODD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(28),
umask:
Tuple::One(2),
event_name:
"UNC_C_RING_AK_USED.UP_ODD",
brief_description:
"AK Ring In Use; Up and Odd",
public_description:
Some("Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the \'UP\' direction is on the clockwise ring and \'DN\' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK0.BANK7",
IntelPerformanceCounterDescription{event_code:
Tuple::One(176),
umask:
Tuple::One(7),
event_name:
"UNC_M_RD_CAS_RANK0.BANK7",
brief_description:
"RD_CAS Access to Rank 0; Bank 7",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxR_BL_NCS_CREDIT_ACQUIRED.VN0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(44),
umask:
Tuple::One(1),
event_name:
"UNC_Q_TxR_BL_NCS_CREDIT_ACQUIRED.VN0",
brief_description:
"R3QPI Egress Credit Occupancy - NCS; for VN0",
public_description:
Some("Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCS message class to BL Egress."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_S_RxR_OCCUPANCY.AD_CRD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(17),
umask:
Tuple::One(1),
event_name:
"UNC_S_RxR_OCCUPANCY.AD_CRD",
brief_description:
"Ingress Occupancy; AD - Credits",
public_description:
Some("Occupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_OCCUPANCY_SNP.VN0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(25),
umask:
Tuple::One(1),
event_name:
"UNC_Q_RxL_OCCUPANCY_SNP.VN0",
brief_description:
"RxQ Occupancy - SNP; for VN0",
public_description:
Some("Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors SNP flits only."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_R3_RxR_INSERTS.SNP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(17),
umask:
Tuple::One(2),
event_name:
"UNC_R3_RxR_INSERTS.SNP",
brief_description:
"Ingress Allocations; SNP",
public_description:
Some("Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_M_WPQ_READ_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(35),
umask:
Tuple::One(0),
event_name:
"UNC_M_WPQ_READ_HIT",
brief_description:
"Write Pending Queue CAM Match",
public_description:
Some("Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_C_TOR_OCCUPANCY.LOCAL_OPCODE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(54),
umask:
Tuple::One(33),
event_name:
"UNC_C_TOR_OCCUPANCY.LOCAL_OPCODE",
brief_description:
"TOR Occupancy; Local Memory - Opcode Matched",
public_description:
Some("For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent \'filters\' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select \'MISS_OPC_MATCH\' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding transactions, satisifed by an opcode, in the TOR that are satisifed by locally HOMed memory."),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
Some("CBoFilter1[28:20]"),
extsel:
false,}),
("UNC_U_U2C_EVENTS.CMC",
IntelPerformanceCounterDescription{event_code:
Tuple::One(67),
umask:
Tuple::One(16),
event_name:
"UNC_U_U2C_EVENTS.CMC",
brief_description:
"Monitor Sent to T0; Correctable Machine Check",
public_description:
Some("Events coming from Uncore can be sent to one or all cores"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("UBOX"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxR_AD_NDR_CREDIT_ACQUIRED.VN0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(40),
umask:
Tuple::One(1),
event_name:
"UNC_Q_TxR_AD_NDR_CREDIT_ACQUIRED.VN0",
brief_description:
"R3QPI Egress Credit Occupancy - AD NDR; for VN0",
public_description:
Some("Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for NDR messages on AD."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_M_RD_CAS_RANK6.BANK5",
IntelPerformanceCounterDescription{event_code:
Tuple::One(182),
umask:
Tuple::One(5),
event_name:
"UNC_M_RD_CAS_RANK6.BANK5",
brief_description:
"RD_CAS Access to Rank 6; Bank 5",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxR_BL_NCB_CREDIT_OCCUPANCY.VN0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(32),
umask:
Tuple::One(1),
event_name:
"UNC_Q_TxR_BL_NCB_CREDIT_OCCUPANCY.VN0",
brief_description:
"R3QPI Egress Credit Occupancy - BL NCB; for VN0",
public_description:
Some("Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. NCB message class to BL Egress."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_R3_RxR_INSERTS.HOM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(17),
umask:
Tuple::One(1),
event_name:
"UNC_R3_RxR_INSERTS.HOM",
brief_description:
"Ingress Allocations; HOM",
public_description:
Some("Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK4.BANK5",
IntelPerformanceCounterDescription{event_code:
Tuple::One(180),
umask:
Tuple::One(5),
event_name:
"UNC_M_RD_CAS_RANK4.BANK5",
brief_description:
"RD_CAS Access to Rank 4; Bank 5",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_S_RxR_INSERTS.AK",
IntelPerformanceCounterDescription{event_code:
Tuple::One(19),
umask:
Tuple::One(16),
event_name:
"UNC_S_RxR_INSERTS.AK",
brief_description:
"Ingress Allocations; AK",
public_description:
Some("Number of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_H_REQUESTS.INVITOE_LOCAL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(1),
umask:
Tuple::One(16),
event_name:
"UNC_H_REQUESTS.INVITOE_LOCAL",
brief_description:
"Read and Write Requests; Local InvItoEs",
public_description:
Some("Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only InvItoEs coming from the local socket."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_POWER_CKE_CYCLES.RANK6",
IntelPerformanceCounterDescription{event_code:
Tuple::One(131),
umask:
Tuple::One(64),
event_name:
"UNC_M_POWER_CKE_CYCLES.RANK6",
brief_description:
"CKE_ON_CYCLES by Rank; DIMM ID",
public_description:
Some("Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary)."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_BL_CYCLES_NE.ALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(53),
umask:
Tuple::One(3),
event_name:
"UNC_H_TxR_BL_CYCLES_NE.ALL",
brief_description:
"BL Egress Not Empty; All",
public_description:
Some("BL Egress Not Empty; Cycles full from both schedulers"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_P_DEMOTIONS_CORE2",
IntelPerformanceCounterDescription{event_code:
Tuple::One(50),
umask:
Tuple::One(0),
event_name:
"UNC_P_DEMOTIONS_CORE2",
brief_description:
"Core C State Demotions",
public_description:
Some("Counts the number of times when a configurable cores had a C-state demotion"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK4.BANK0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(188),
umask:
Tuple::One(0),
event_name:
"UNC_M_WR_CAS_RANK4.BANK0",
brief_description:
"WR_CAS Access to Rank 4; Bank 0",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK0.BANK13",
IntelPerformanceCounterDescription{event_code:
Tuple::One(184),
umask:
Tuple::One(13),
event_name:
"UNC_M_WR_CAS_RANK0.BANK13",
brief_description:
"WR_CAS Access to Rank 0; Bank 13",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_R3_SBO0_CREDIT_OCCUPANCY.AD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(42),
umask:
Tuple::One(1),
event_name:
"UNC_R3_SBO0_CREDIT_OCCUPANCY.AD",
brief_description:
"SBo0 Credits Occupancy; For AD Ring",
public_description:
Some("Number of Sbo 0 credits in use in a given cycle, per ring."),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_S_RING_AD_USED.DOWN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(27),
umask:
Tuple::One(12),
event_name:
"UNC_S_RING_AD_USED.DOWN",
brief_description:
"AD Ring In Use; Down",
public_description:
Some("Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the \'UP\' direction is on the clockwise ring and \'DN\' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_R3_RxR_OCCUPANCY_VN1.SNP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(19),
umask:
Tuple::One(2),
event_name:
"UNC_R3_RxR_OCCUPANCY_VN1.SNP",
brief_description:
"VN1 Ingress Occupancy Accumulator; SNP",
public_description:
Some("Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.; SNP Ingress Queue"),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(19),
umask:
Tuple::One(8),
event_name:
"UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT",
brief_description:
"Direct 2 Core Spawning; Spawn Failure - Egress and RBT Invalid",
public_description:
Some("Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exlusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because there were not enough Egress credits AND the RBT bit was not set, but the RBT tag matched."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_R3_RxR_INSERTS_VN1.SNP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(21),
umask:
Tuple::One(2),
event_name:
"UNC_R3_RxR_INSERTS_VN1.SNP",
brief_description:
"VN1 Ingress Allocations; SNP",
public_description:
Some("Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_SNP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(32),
umask:
Tuple::One(4),
event_name:
"UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_SNP",
brief_description:
"QPI0 AD Credits Empty",
public_description:
Some("No credits available to send to QPI0 on the AD Ring; VN0 SNP Messages"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_C_TxR_INSERTS.BL_CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(2),
umask:
Tuple::One(64),
event_name:
"UNC_C_TxR_INSERTS.BL_CORE",
brief_description:
"Egress Allocations; BL - Corebo",
public_description:
Some("Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the BL ring. This is commonly used for transfering writeback data to the cache."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN3",
IntelPerformanceCounterDescription{event_code:
Tuple::One(22),
umask:
Tuple::One(8),
event_name:
"UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN3",
brief_description:
"iMC RPQ Credits Empty - Special; Channel 3",
public_description:
Some("Counts the number of cycles when there are no \'special\' credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC\'s RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and \'special\' requests such as ISOCH reads. This count only tracks the \'special\' credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK7.BANK6",
IntelPerformanceCounterDescription{event_code:
Tuple::One(191),
umask:
Tuple::One(6),
event_name:
"UNC_M_WR_CAS_RANK7.BANK6",
brief_description:
"WR_CAS Access to Rank 7; Bank 6",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_AD_INSERTS.SCHED0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(39),
umask:
Tuple::One(1),
event_name:
"UNC_H_TxR_AD_INSERTS.SCHED0",
brief_description:
"AD Egress Allocations; Scheduler 0",
public_description:
Some("AD Egress Allocations; Filter for allocations from scheduler bank 0"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK4.BANK3",
IntelPerformanceCounterDescription{event_code:
Tuple::One(180),
umask:
Tuple::One(3),
event_name:
"UNC_M_RD_CAS_RANK4.BANK3",
brief_description:
"RD_CAS Access to Rank 4; Bank 3",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_CREDITS_CONSUMED_VN1.NDR",
IntelPerformanceCounterDescription{event_code:
Tuple::One(57),
umask:
Tuple::One(32),
event_name:
"UNC_Q_RxL_CREDITS_CONSUMED_VN1.NDR",
brief_description:
"VN1 Credit Consumed; NDR",
public_description:
Some("Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the NDR message class."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_R2_TxR_CYCLES_NE.BL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(35),
umask:
Tuple::One(4),
event_name:
"UNC_R2_TxR_CYCLES_NE.BL",
brief_description:
"Egress Cycles Not Empty; BL",
public_description:
Some("Counts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity.; BL Egress Queue"),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK4.BANK9",
IntelPerformanceCounterDescription{event_code:
Tuple::One(188),
umask:
Tuple::One(9),
event_name:
"UNC_M_WR_CAS_RANK4.BANK9",
brief_description:
"WR_CAS Access to Rank 4; Bank 9",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_INSERTS_DRS.VN1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(9),
umask:
Tuple::One(2),
event_name:
"UNC_Q_RxL_INSERTS_DRS.VN1",
brief_description:
"Rx Flit Buffer Allocations - DRS; for VN1",
public_description:
Some("Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only DRS flits."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_M_RD_CAS_RANK6.BANKG1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(182),
umask:
Tuple::One(18),
event_name:
"UNC_M_RD_CAS_RANK6.BANKG1",
brief_description:
"RD_CAS Access to Rank 6; Bank Group 1 (Banks 4-7)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_INSERTS_SNP.VN1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(13),
umask:
Tuple::One(2),
event_name:
"UNC_Q_RxL_INSERTS_SNP.VN1",
brief_description:
"Rx Flit Buffer Allocations - SNP; for VN1",
public_description:
Some("Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only SNP flits."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_H_HITME_HIT.ALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(113),
umask:
Tuple::One(255),
event_name:
"UNC_H_HITME_HIT.ALL",
brief_description:
"Counts Number of Hits in HitMe Cache; All Requests",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK7.BANK1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(191),
umask:
Tuple::One(1),
event_name:
"UNC_M_WR_CAS_RANK7.BANK1",
brief_description:
"WR_CAS Access to Rank 7; Bank 1",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK1.BANKG1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(177),
umask:
Tuple::One(18),
event_name:
"UNC_M_RD_CAS_RANK1.BANKG1",
brief_description:
"RD_CAS Access to Rank 1; Bank Group 1 (Banks 4-7)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_AD_INSERTS.SCHED1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(39),
umask:
Tuple::One(2),
event_name:
"UNC_H_TxR_AD_INSERTS.SCHED1",
brief_description:
"AD Egress Allocations; Scheduler 1",
public_description:
Some("AD Egress Allocations; Filter for allocations from scheduler bank 1"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_S_RxR_CRD_STARVED.AD_CRD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(20),
umask:
Tuple::One(1),
event_name:
"UNC_S_RxR_CRD_STARVED.AD_CRD",
brief_description:
"Injection Starvation; AD - Credits",
public_description:
Some("Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK4.BANKG2",
IntelPerformanceCounterDescription{event_code:
Tuple::One(180),
umask:
Tuple::One(19),
event_name:
"UNC_M_RD_CAS_RANK4.BANKG2",
brief_description:
"RD_CAS Access to Rank 4; Bank Group 2 (Banks 8-11)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_C_TOR_OCCUPANCY.NID_ALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(54),
umask:
Tuple::One(72),
event_name:
"UNC_C_TOR_OCCUPANCY.NID_ALL",
brief_description:
"TOR Occupancy; NID Matched",
public_description:
Some("For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent \'filters\' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select \'MISS_OPC_MATCH\' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of NID matched outstanding requests in the TOR. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid.In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system."),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
Some("CBoFilter1[15:0]"),
extsel:
false,}),
("UNC_Q_RxL_OCCUPANCY_NCB.VN0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(22),
umask:
Tuple::One(1),
event_name:
"UNC_Q_RxL_OCCUPANCY_NCB.VN0",
brief_description:
"RxQ Occupancy - NCB; for VN0",
public_description:
Some("Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCB flits only."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_M_WR_CAS_RANK5.BANK15",
IntelPerformanceCounterDescription{event_code:
Tuple::One(189),
umask:
Tuple::One(15),
event_name:
"UNC_M_WR_CAS_RANK5.BANK15",
brief_description:
"WR_CAS Access to Rank 5; Bank 15",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_H_TAD_REQUESTS_G0.REGION5",
IntelPerformanceCounterDescription{event_code:
Tuple::One(27),
umask:
Tuple::One(32),
event_name:
"UNC_H_TAD_REQUESTS_G0.REGION5",
brief_description:
"HA Requests to a TAD Region - Group 0; TAD Region 5",
public_description:
Some("Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for \'Monroe\' systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 5"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_C_RxR_IPQ_RETRY2.TARGET",
IntelPerformanceCounterDescription{event_code:
Tuple::One(40),
umask:
Tuple::One(64),
event_name:
"UNC_C_RxR_IPQ_RETRY2.TARGET",
brief_description:
"Probe Queue Retries; Target Node Filter",
public_description:
Some("Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.; Counts the number of times that a request from the IPQ was retried filtered by the Target NodeID as specified in the Cbox\'s Filter register."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
Some("CBoFilter1[15:0]"),
extsel:
false,}),
("UNC_C_RING_AK_USED.DOWN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(28),
umask:
Tuple::One(12),
event_name:
"UNC_C_RING_AK_USED.DOWN",
brief_description:
"AK Ring In Use; Down",
public_description:
Some("Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the \'UP\' direction is on the clockwise ring and \'DN\' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_C_TOR_INSERTS.NID_MISS_OPCODE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(53),
umask:
Tuple::One(67),
event_name:
"UNC_C_TOR_INSERTS.NID_MISS_OPCODE",
brief_description:
"TOR Inserts; NID and Opcode Matched Miss",
public_description:
Some("Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent \'filters\' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select \'MISS_OPC_MATCH\' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match a NID and an opcode."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
Some("CBoFilter1[28:20], CBoFilter1[15:0]"),
extsel:
false,}),
("UNC_I_RxR_BL_NCS_CYCLES_FULL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(6),
umask:
Tuple::One(0),
event_name:
"UNC_I_RxR_BL_NCS_CYCLES_FULL",
brief_description:
"tbd",
public_description:
Some("Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_BL_HAZARD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(81),
umask:
Tuple::One(4),
event_name:
"UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_BL_HAZARD",
brief_description:
"BT to HT Not Issued; Incoming Data Hazard",
public_description:
Some("Counts the number of cycles when the HA does not issue transaction from BT to HT.; Cycles unable to issue from BT due to incoming BL data hazard"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_R3_VNA_CREDITS_REJECT.SNP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(52),
umask:
Tuple::One(2),
event_name:
"UNC_R3_VNA_CREDITS_REJECT.SNP",
brief_description:
"VNA Credit Reject; SNP Message Class",
public_description:
Some("Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_C_CLOCKTICKS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(0),
umask:
Tuple::One(0),
event_name:
"UNC_C_CLOCKTICKS",
brief_description:
"Uncore Clocks",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_R3_VN1_CREDITS_REJECT.HOM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(57),
umask:
Tuple::One(1),
event_name:
"UNC_R3_VN1_CREDITS_REJECT.HOM",
brief_description:
"VN1 Credit Acquisition Failed on DRS; HOM Message Class",
public_description:
Some("Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_P_CORE17_TRANSITION_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(113),
umask:
Tuple::One(0),
event_name:
"UNC_P_CORE17_TRANSITION_CYCLES",
brief_description:
"Core C State Transition Cycles",
public_description:
Some("Number of cycles spent performing core C state transitions. There is one event per core."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_S_RxR_OCCUPANCY.AK",
IntelPerformanceCounterDescription{event_code:
Tuple::One(17),
umask:
Tuple::One(16),
event_name:
"UNC_S_RxR_OCCUPANCY.AK",
brief_description:
"Ingress Occupancy; AK",
public_description:
Some("Occupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_M_POWER_CKE_CYCLES.RANK0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(131),
umask:
Tuple::One(1),
event_name:
"UNC_M_POWER_CKE_CYCLES.RANK0",
brief_description:
"CKE_ON_CYCLES by Rank; DIMM ID",
public_description:
Some("Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary)."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_H_IOT_CTS_WEST_LO.CTS0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(98),
umask:
Tuple::One(1),
event_name:
"UNC_H_IOT_CTS_WEST_LO.CTS0",
brief_description:
"IOT Common Trigger Sequencer - Lo",
public_description:
Some("Debug Mask/Match Tie-Ins"),
counter:
Counter::Programmable(7),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_I_RxR_BL_DRS_CYCLES_FULL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(4),
umask:
Tuple::One(0),
event_name:
"UNC_I_RxR_BL_DRS_CYCLES_FULL",
brief_description:
"tbd",
public_description:
Some("Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_Q_DIRECT2CORE.FAILURE_CREDITS_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(19),
umask:
Tuple::One(32),
event_name:
"UNC_Q_DIRECT2CORE.FAILURE_CREDITS_MISS",
brief_description:
"Direct 2 Core Spawning; Spawn Failure - Egress and RBT Miss",
public_description:
Some("Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exlusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match and there weren\'t enough Egress credits. The valid bit was set."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_H_TRACKER_CYCLES_FULL.ALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(2),
umask:
Tuple::One(2),
event_name:
"UNC_H_TRACKER_CYCLES_FULL.ALL",
brief_description:
"Tracker Cycles Full; Cycles Completely Used",
public_description:
Some("Counts the number of cycles when the local HA tracker pool is completely used. This can be used with edge detect to identify the number of situations when the pool became fully utilized. This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure. In other words, the system could be starved for RTIDs but not fill up the HA trackers. HA trackers are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; Counts the number of cycles when the HA tracker pool (HT) is completely used including reserved HT entries. It will not return valid count when BT is disabled."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK6.BANK9",
IntelPerformanceCounterDescription{event_code:
Tuple::One(190),
umask:
Tuple::One(9),
event_name:
"UNC_M_WR_CAS_RANK6.BANK9",
brief_description:
"WR_CAS Access to Rank 6; Bank 9",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxR_AD_HOM_CREDIT_OCCUPANCY.VN0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(34),
umask:
Tuple::One(1),
event_name:
"UNC_Q_TxR_AD_HOM_CREDIT_OCCUPANCY.VN0",
brief_description:
"R3QPI Egress Credit Occupancy - AD HOM; for VN0",
public_description:
Some("Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for HOM messages on AD."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_S_RxR_CRD_STARVED.IV",
IntelPerformanceCounterDescription{event_code:
Tuple::One(20),
umask:
Tuple::One(32),
event_name:
"UNC_S_RxR_CRD_STARVED.IV",
brief_description:
"Injection Starvation; IV",
public_description:
Some("Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(34),
umask:
Tuple::One(1),
event_name:
"UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO0",
brief_description:
"CBox AD Credits Empty",
public_description:
Some("No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 0"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK5.BANKG0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(189),
umask:
Tuple::One(17),
event_name:
"UNC_M_WR_CAS_RANK5.BANKG0",
brief_description:
"WR_CAS Access to Rank 5; Bank Group 0 (Banks 0-3)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK4.BANK5",
IntelPerformanceCounterDescription{event_code:
Tuple::One(188),
umask:
Tuple::One(5),
event_name:
"UNC_M_WR_CAS_RANK4.BANK5",
brief_description:
"WR_CAS Access to Rank 4; Bank 5",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_S_TxR_OCCUPANCY.AK",
IntelPerformanceCounterDescription{event_code:
Tuple::One(1),
umask:
Tuple::One(16),
event_name:
"UNC_S_TxR_OCCUPANCY.AK",
brief_description:
"Egress Occupancy; AK",
public_description:
Some("Occupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_CREDITS_CONSUMED_VN0.DRS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(30),
umask:
Tuple::One(1),
event_name:
"UNC_Q_RxL_CREDITS_CONSUMED_VN0.DRS",
brief_description:
"VN0 Credit Consumed; DRS",
public_description:
Some("Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the DRS message class."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_M_WR_CAS_RANK7.BANK2",
IntelPerformanceCounterDescription{event_code:
Tuple::One(191),
umask:
Tuple::One(2),
event_name:
"UNC_M_WR_CAS_RANK7.BANK2",
brief_description:
"WR_CAS Access to Rank 7; Bank 2",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxR_AD_HOM_CREDIT_OCCUPANCY.VN1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(34),
umask:
Tuple::One(2),
event_name:
"UNC_Q_TxR_AD_HOM_CREDIT_OCCUPANCY.VN1",
brief_description:
"R3QPI Egress Credit Occupancy - AD HOM; for VN1",
public_description:
Some("Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for HOM messages on AD."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_NDR",
IntelPerformanceCounterDescription{event_code:
Tuple::One(46),
umask:
Tuple::One(64),
event_name:
"UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_NDR",
brief_description:
"QPI1 AD Credits Empty",
public_description:
Some("No credits available to send to QPI1 on the AD Ring; VN1 NDR Messages"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_R3_RING_AD_USED.CW",
IntelPerformanceCounterDescription{event_code:
Tuple::One(7),
umask:
Tuple::One(3),
event_name:
"UNC_R3_RING_AD_USED.CW",
brief_description:
"R3 AD Ring in Use; Clockwise",
public_description:
Some("Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop."),
counter:
Counter::Programmable(7),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_M_POWER_PCU_THROTTLING",
IntelPerformanceCounterDescription{event_code:
Tuple::One(66),
umask:
Tuple::One(0),
event_name:
"UNC_M_POWER_PCU_THROTTLING",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxR_AD_SNP_CREDIT_OCCUPANCY.VN0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(35),
umask:
Tuple::One(1),
event_name:
"UNC_Q_TxR_AD_SNP_CREDIT_OCCUPANCY.VN0",
brief_description:
"R3QPI Egress Credit Occupancy - AD SNP; for VN0",
public_description:
Some("Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO fro Snoop messages on AD."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_R3_RING_AK_USED.CCW",
IntelPerformanceCounterDescription{event_code:
Tuple::One(8),
umask:
Tuple::One(12),
event_name:
"UNC_R3_RING_AK_USED.CCW",
brief_description:
"R3 AK Ring in Use; Counterclockwise",
public_description:
Some("Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop."),
counter:
Counter::Programmable(7),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK6.BANK14",
IntelPerformanceCounterDescription{event_code:
Tuple::One(190),
umask:
Tuple::One(14),
event_name:
"UNC_M_WR_CAS_RANK6.BANK14",
brief_description:
"WR_CAS Access to Rank 6; Bank 14",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_S_RxR_CRD_STARVED.BL_BNC",
IntelPerformanceCounterDescription{event_code:
Tuple::One(20),
umask:
Tuple::One(8),
event_name:
"UNC_S_RxR_CRD_STARVED.BL_BNC",
brief_description:
"Injection Starvation; BL - Bounces",
public_description:
Some("Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK2.BANK0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(178),
umask:
Tuple::One(0),
event_name:
"UNC_M_RD_CAS_RANK2.BANK0",
brief_description:
"RD_CAS Access to Rank 2; Bank 0",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxR_AD_NDR_CREDIT_OCCUPANCY.VN0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(36),
umask:
Tuple::One(1),
event_name:
"UNC_Q_TxR_AD_NDR_CREDIT_OCCUPANCY.VN0",
brief_description:
"R3QPI Egress Credit Occupancy - AD NDR; for VN0",
public_description:
Some("Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for NDR messages on AD."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_R3_RxR_OCCUPANCY_VN1.NDR",
IntelPerformanceCounterDescription{event_code:
Tuple::One(19),
umask:
Tuple::One(4),
event_name:
"UNC_R3_RxR_OCCUPANCY_VN1.NDR",
brief_description:
"VN1 Ingress Occupancy Accumulator; NDR",
public_description:
Some("Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.; NDR Ingress Queue"),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_C_SBO_CREDIT_OCCUPANCY.BL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(62),
umask:
Tuple::One(2),
event_name:
"UNC_C_SBO_CREDIT_OCCUPANCY.BL",
brief_description:
"SBo Credits Occupancy; For BL Ring",
public_description:
Some("Number of Sbo credits in use in a given cycle, per ring. Each Cbo is assigned an Sbo it can communicate with."),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_CYCLES_NE_SNP.VN0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(19),
umask:
Tuple::One(1),
event_name:
"UNC_Q_RxL_CYCLES_NE_SNP.VN0",
brief_description:
"RxQ Cycles Not Empty - SNP; for VN0",
public_description:
Some("Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors SNP flits only."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_H_TxR_BL_CYCLES_FULL.SCHED1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(54),
umask:
Tuple::One(2),
event_name:
"UNC_H_TxR_BL_CYCLES_FULL.SCHED1",
brief_description:
"BL Egress Full; Scheduler 1",
public_description:
Some("BL Egress Full; Filter for cycles full from scheduler bank 1"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_R2_IIO_CREDITS_USED.NCS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(50),
umask:
Tuple::One(32),
event_name:
"UNC_R2_IIO_CREDITS_USED.NCS",
brief_description:
"R2PCIe IIO Credits in Use; NCS",
public_description:
Some("Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCS message class."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_P_FREQ_BAND3_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(14),
umask:
Tuple::One(0),
event_name:
"UNC_P_FREQ_BAND3_CYCLES",
brief_description:
"Frequency Residency",
public_description:
Some("Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter. One can use all four counters with this event, so it is possible to track up to 4 configurable bands. One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
Some("PCUFilter[31:24]"),
extsel:
false,}),
("UNC_C_TxR_ADS_USED.AK",
IntelPerformanceCounterDescription{event_code:
Tuple::One(4),
umask:
Tuple::One(2),
event_name:
"UNC_C_TxR_ADS_USED.AK",
brief_description:
"Onto AK Ring",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxL_FLITS_G1.SNP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(0),
umask:
Tuple::One(1),
event_name:
"UNC_Q_TxL_FLITS_G1.SNP",
brief_description:
"Flits Transferred - Group 1; SNP Flits",
public_description:
Some("Counts the number of flits trasmitted across the QPI Link. This is one of three \'groups\' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each \'flit\' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four \'fits\', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI \'speed\' (for example, 8.0 GT/s), the \'transfers\' here refer to \'fits\'. Therefore, in L0, the system will transfer 1 \'flit\' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as \'data\' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual \'data\' and an additional 16 bits of other information. To calculate \'data\' bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of snoop request flits transmitted over QPI. These requests are contained in the snoop channel. This does not include snoop responses, which are transmitted on the home channel."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_H_TRACKER_OCCUPANCY.INVITOE_REMOTE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(4),
umask:
Tuple::One(128),
event_name:
"UNC_H_TRACKER_OCCUPANCY.INVITOE_REMOTE",
brief_description:
"Tracker Occupancy Accumultor; Remote InvItoE Requests",
public_description:
Some("Accumulates the occupancy of the local HA tracker pool in every cycle. This can be used in conjection with the \'not empty\' stat to calculate average queue occupancy or the \'allocations\' stat in order to calculate average queue latency. HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_S_RxR_OCCUPANCY.BL_CRD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(17),
umask:
Tuple::One(4),
event_name:
"UNC_S_RxR_OCCUPANCY.BL_CRD",
brief_description:
"Ingress Occupancy; BL - Credits",
public_description:
Some("Occupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_M_WPQ_CYCLES_FULL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(34),
umask:
Tuple::One(0),
event_name:
"UNC_M_WPQ_CYCLES_FULL",
brief_description:
"Write Pending Queue Full Cycles",
public_description:
Some("Counts the number of cycles when the Write Pending Queue is full. When the WPQ is full, the HA will not be able to issue any additional read requests into the iMC. This count should be similar count in the HA which tracks the number of cycles that the HA has no WPQ credits, just somewhat smaller to account for the credit return overhead."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_R3_SBO1_CREDIT_OCCUPANCY.BL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(43),
umask:
Tuple::One(2),
event_name:
"UNC_R3_SBO1_CREDIT_OCCUPANCY.BL",
brief_description:
"SBo1 Credits Occupancy; For BL Ring",
public_description:
Some("Number of Sbo 1 credits in use in a given cycle, per ring."),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK5.ALLBANKS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(181),
umask:
Tuple::One(16),
event_name:
"UNC_M_RD_CAS_RANK5.ALLBANKS",
brief_description:
"RD_CAS Access to Rank 5; All Banks",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_INSERTS_NCS.VN1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(11),
umask:
Tuple::One(2),
event_name:
"UNC_Q_RxL_INSERTS_NCS.VN1",
brief_description:
"Rx Flit Buffer Allocations - NCS; for VN1",
public_description:
Some("Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCS flits."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_U_U2C_EVENTS.MONITOR_T0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(67),
umask:
Tuple::One(1),
event_name:
"UNC_U_U2C_EVENTS.MONITOR_T0",
brief_description:
"Monitor Sent to T0; Monitor T0",
public_description:
Some("Events coming from Uncore can be sent to one or all cores; Filter by core"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("UBOX"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxL0P_POWER_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(13),
umask:
Tuple::One(0),
event_name:
"UNC_Q_TxL0P_POWER_CYCLES",
brief_description:
"Cycles in L0p",
public_description:
Some("Number of QPI qfclk cycles spent in L0p power mode. L0p is a mode where we disable 1/2 of the QPI lanes, decreasing our bandwidth in order to save power. It increases snoop and data transfer latencies and decreases overall bandwidth. This mode can be very useful in NUMA optimized workloads that largely only utilize QPI for snoops and their responses. Use edge detect to count the number of instances when the QPI link entered L0p. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_R2_RxR_OCCUPANCY.DRS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(19),
umask:
Tuple::One(8),
event_name:
"UNC_R2_RxR_OCCUPANCY.DRS",
brief_description:
"Ingress Occupancy Accumulator; DRS",
public_description:
Some("Accumulates the occupancy of a given R2PCIe Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the R2PCIe Ingress Not Empty event to calculate average occupancy or the R2PCIe Ingress Allocations event in order to calculate average queuing latency.; DRS Ingress Queue"),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_H_HITME_LOOKUP.WBMTOI",
IntelPerformanceCounterDescription{event_code:
Tuple::One(112),
umask:
Tuple::One(2),
event_name:
"UNC_H_HITME_LOOKUP.WBMTOI",
brief_description:
"Counts Number of times HitMe Cache is accessed; op is WbMtoI",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK5.BANK3",
IntelPerformanceCounterDescription{event_code:
Tuple::One(181),
umask:
Tuple::One(3),
event_name:
"UNC_M_RD_CAS_RANK5.BANK3",
brief_description:
"RD_CAS Access to Rank 5; Bank 3",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK6.BANK4",
IntelPerformanceCounterDescription{event_code:
Tuple::One(190),
umask:
Tuple::One(4),
event_name:
"UNC_M_WR_CAS_RANK6.BANK4",
brief_description:
"WR_CAS Access to Rank 6; Bank 4",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK1.BANK7",
IntelPerformanceCounterDescription{event_code:
Tuple::One(177),
umask:
Tuple::One(7),
event_name:
"UNC_M_RD_CAS_RANK1.BANK7",
brief_description:
"RD_CAS Access to Rank 1; Bank 7",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_H_SNP_RESP_RECV_LOCAL.RSPSFWD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(96),
umask:
Tuple::One(8),
event_name:
"UNC_H_SNP_RESP_RECV_LOCAL.RSPSFWD",
brief_description:
"Snoop Responses Received Local; RspSFwd",
public_description:
Some("Number of snoop responses received for a Local request; Filters for a snoop response of RspSFwd. This is returned when a remote caching agent forwards data but holds on to its currentl copy. This is common for data and code reads that hit in a remote socket in E or F state."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_R3_QPI1_BL_CREDITS_EMPTY.VNA",
IntelPerformanceCounterDescription{event_code:
Tuple::One(47),
umask:
Tuple::One(1),
event_name:
"UNC_R3_QPI1_BL_CREDITS_EMPTY.VNA",
brief_description:
"QPI1 BL Credits Empty",
public_description:
Some("No credits available to send to QPI1 on the BL Ring; VNA"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_C_TxR_INSERTS.AD_CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(2),
umask:
Tuple::One(16),
event_name:
"UNC_C_TxR_INSERTS.AD_CORE",
brief_description:
"Egress Allocations; AD - Corebo",
public_description:
Some("Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the AD ring. This is commonly used for outbound requests."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_C_TOR_INSERTS.REMOTE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(53),
umask:
Tuple::One(136),
event_name:
"UNC_C_TOR_INSERTS.REMOTE",
brief_description:
"TOR Inserts; Remote Memory",
public_description:
Some("Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent \'filters\' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select \'MISS_OPC_MATCH\' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted into the TOR that are satisifed by remote caches or remote memory."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_R3_IOT_CTS_HI.CTS3",
IntelPerformanceCounterDescription{event_code:
Tuple::One(13),
umask:
Tuple::One(2),
event_name:
"UNC_R3_IOT_CTS_HI.CTS3",
brief_description:
"IOT Common Trigger Sequencer - Hi",
public_description:
Some("Debug Mask/Match Tie-Ins"),
counter:
Counter::Programmable(7),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_INSERTS_HOM.VN1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(12),
umask:
Tuple::One(2),
event_name:
"UNC_Q_RxL_INSERTS_HOM.VN1",
brief_description:
"Rx Flit Buffer Allocations - HOM; for VN1",
public_description:
Some("Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only HOM flits."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_H_SNOOP_RESP.RSPSFWD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(33),
umask:
Tuple::One(8),
event_name:
"UNC_H_SNOOP_RESP.RSPSFWD",
brief_description:
"Snoop Responses Received; RspSFwd",
public_description:
Some("Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of RspSFwd. This is returned when a remote caching agent forwards data but holds on to its currentl copy. This is common for data and code reads that hit in a remote socket in E or F state."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK6.BANK7",
IntelPerformanceCounterDescription{event_code:
Tuple::One(190),
umask:
Tuple::One(7),
event_name:
"UNC_M_WR_CAS_RANK6.BANK7",
brief_description:
"WR_CAS Access to Rank 6; Bank 7",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK0.BANK7",
IntelPerformanceCounterDescription{event_code:
Tuple::One(184),
umask:
Tuple::One(7),
event_name:
"UNC_M_WR_CAS_RANK0.BANK7",
brief_description:
"WR_CAS Access to Rank 0; Bank 7",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_POWER_CRITICAL_THROTTLE_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(134),
umask:
Tuple::One(0),
event_name:
"UNC_M_POWER_CRITICAL_THROTTLE_CYCLES",
brief_description:
"Critical Throttle Cycles",
public_description:
Some("Counts the number of cycles when the iMC is in critical thermal throttling. When this happens, all traffic is blocked. This should be rare unless something bad is going on in the platform. There is no filtering by rank for this event."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK5.BANK3",
IntelPerformanceCounterDescription{event_code:
Tuple::One(189),
umask:
Tuple::One(3),
event_name:
"UNC_M_WR_CAS_RANK5.BANK3",
brief_description:
"WR_CAS Access to Rank 5; Bank 3",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_R2_RING_AD_USED.CW",
IntelPerformanceCounterDescription{event_code:
Tuple::One(7),
umask:
Tuple::One(3),
event_name:
"UNC_R2_RING_AD_USED.CW",
brief_description:
"R2 AD Ring in Use; Clockwise",
public_description:
Some("Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_HOM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(32),
umask:
Tuple::One(2),
event_name:
"UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_HOM",
brief_description:
"QPI0 AD Credits Empty",
public_description:
Some("No credits available to send to QPI0 on the AD Ring; VN0 HOM Messages"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_C_RING_BOUNCES.BL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(5),
umask:
Tuple::One(4),
event_name:
"UNC_C_RING_BOUNCES.BL",
brief_description:
"Number of LLC responses that bounced on the Ring.; BL",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_S_RING_BL_USED.DOWN_EVEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(29),
umask:
Tuple::One(4),
event_name:
"UNC_S_RING_BL_USED.DOWN_EVEN",
brief_description:
"BL Ring in Use; Down and Event",
public_description:
Some("Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the \'UP\' direction is on the clockwise ring and \'DN\' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Event ring polarity."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL0P_POWER_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(16),
umask:
Tuple::One(0),
event_name:
"UNC_Q_RxL0P_POWER_CYCLES",
brief_description:
"Cycles in L0p",
public_description:
Some("Number of QPI qfclk cycles spent in L0p power mode. L0p is a mode where we disable 1/2 of the QPI lanes, decreasing our bandwidth in order to save power. It increases snoop and data transfer latencies and decreases overall bandwidth. This mode can be very useful in NUMA optimized workloads that largely only utilize QPI for snoops and their responses. Use edge detect to count the number of instances when the QPI link entered L0p. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_AD_CYCLES_NE.SCHED0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(41),
umask:
Tuple::One(1),
event_name:
"UNC_H_TxR_AD_CYCLES_NE.SCHED0",
brief_description:
"AD Egress Not Empty; Scheduler 0",
public_description:
Some("AD Egress Not Empty; Filter for cycles not empty from scheduler bank 0"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK7.BANK0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(0),
event_name:
"UNC_M_RD_CAS_RANK7.BANK0",
brief_description:
"RD_CAS Access to Rank 7; Bank 0",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_ACT_COUNT.BYP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(1),
umask:
Tuple::One(8),
event_name:
"UNC_M_ACT_COUNT.BYP",
brief_description:
"DRAM Activate Count; Activate due to Write",
public_description:
Some("Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_S_RxR_BUSY_STARVED.BL_CRD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(21),
umask:
Tuple::One(4),
event_name:
"UNC_S_RxR_BUSY_STARVED.BL_CRD",
brief_description:
"Injection Starvation; BL - Credits",
public_description:
Some("Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress because a message (credited/bounceable) is being sent."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(53),
umask:
Tuple::One(131),
event_name:
"UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE",
brief_description:
"TOR Inserts; Misses to Remote Memory - Opcode Matched",
public_description:
Some("Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent \'filters\' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select \'MISS_OPC_MATCH\' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions, satisifed by an opcode, inserted into the TOR that are satisifed by remote caches or remote memory."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
Some("CBoFilter1[28:20]"),
extsel:
false,}),
("UNC_M_RD_CAS_RANK4.ALLBANKS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(180),
umask:
Tuple::One(16),
event_name:
"UNC_M_RD_CAS_RANK4.ALLBANKS",
brief_description:
"RD_CAS Access to Rank 4; All Banks",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO10",
IntelPerformanceCounterDescription{event_code:
Tuple::One(31),
umask:
Tuple::One(4),
event_name:
"UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO10",
brief_description:
"CBox AD Credits Empty",
public_description:
Some("No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 10"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_R2_RING_AK_BOUNCES.UP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(18),
umask:
Tuple::One(1),
event_name:
"UNC_R2_RING_AK_BOUNCES.UP",
brief_description:
"AK Ingress Bounced; Up",
public_description:
Some("Counts the number of times when a request destined for the AK ingress bounced."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_R3_TxR_NACK.DN_BL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(38),
umask:
Tuple::One(2),
event_name:
"UNC_R3_TxR_NACK.DN_BL",
brief_description:
"Egress CCW NACK; BL CCW",
public_description:
Some("BL CounterClockwise Egress Queue"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_PRIO.HIGH",
IntelPerformanceCounterDescription{event_code:
Tuple::One(160),
umask:
Tuple::One(4),
event_name:
"UNC_M_RD_CAS_PRIO.HIGH",
brief_description:
"Read CAS issued with HIGH priority",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_INSERTS_NCB.VN0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(10),
umask:
Tuple::One(1),
event_name:
"UNC_Q_RxL_INSERTS_NCB.VN0",
brief_description:
"Rx Flit Buffer Allocations - NCB; for VN0",
public_description:
Some("Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCB flits."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_M_WR_CAS_RANK7.BANKG1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(191),
umask:
Tuple::One(18),
event_name:
"UNC_M_WR_CAS_RANK7.BANKG1",
brief_description:
"WR_CAS Access to Rank 7; Bank Group 1 (Banks 4-7)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_R2_RxR_CYCLES_NE.NCB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(16),
umask:
Tuple::One(16),
event_name:
"UNC_R2_RxR_CYCLES_NE.NCB",
brief_description:
"Ingress Cycles Not Empty; NCB",
public_description:
Some("Counts the number of cycles when the R2PCIe Ingress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxL_FLITS_G1.HOM_NONREQ",
IntelPerformanceCounterDescription{event_code:
Tuple::One(0),
umask:
Tuple::One(4),
event_name:
"UNC_Q_TxL_FLITS_G1.HOM_NONREQ",
brief_description:
"Flits Transferred - Group 1; HOM Non-Request Flits",
public_description:
Some("Counts the number of flits trasmitted across the QPI Link. This is one of three \'groups\' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each \'flit\' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four \'fits\', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI \'speed\' (for example, 8.0 GT/s), the \'transfers\' here refer to \'fits\'. Therefore, in L0, the system will transfer 1 \'flit\' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as \'data\' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual \'data\' and an additional 16 bits of other information. To calculate \'data\' bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of non-request flits transmitted over QPI on the home channel. These are most commonly snoop responses, and this event can be used as a proxy for that."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_C_TOR_OCCUPANCY.WB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(54),
umask:
Tuple::One(16),
event_name:
"UNC_C_TOR_OCCUPANCY.WB",
brief_description:
"TOR Occupancy; Writebacks",
public_description:
Some("For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent \'filters\' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select \'MISS_OPC_MATCH\' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Write transactions in the TOR. This does not include \'RFO\', but actual operations that contain data being sent from the core."),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_S_TxR_OCCUPANCY.BL_CRD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(1),
umask:
Tuple::One(4),
event_name:
"UNC_S_TxR_OCCUPANCY.BL_CRD",
brief_description:
"Egress Occupancy; BL - Credits",
public_description:
Some("Occupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK5.BANK13",
IntelPerformanceCounterDescription{event_code:
Tuple::One(189),
umask:
Tuple::One(13),
event_name:
"UNC_M_WR_CAS_RANK5.BANK13",
brief_description:
"WR_CAS Access to Rank 5; Bank 13",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK4.BANK4",
IntelPerformanceCounterDescription{event_code:
Tuple::One(180),
umask:
Tuple::One(4),
event_name:
"UNC_M_RD_CAS_RANK4.BANK4",
brief_description:
"RD_CAS Access to Rank 4; Bank 4",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_CAS_COUNT.RD_RMM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(4),
umask:
Tuple::One(32),
event_name:
"UNC_M_CAS_COUNT.RD_RMM",
brief_description:
"DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in RMM",
public_description:
Some("DRAM RD_CAS and WR_CAS Commands"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_C_TxR_INSERTS.IV_CACHE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(2),
umask:
Tuple::One(8),
event_name:
"UNC_C_TxR_INSERTS.IV_CACHE",
brief_description:
"Egress Allocations; IV - Cachebo",
public_description:
Some("Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the IV ring. This is commonly used for snoops to the cores."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_R3_RxR_OCCUPANCY_VN1.DRS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(19),
umask:
Tuple::One(8),
event_name:
"UNC_R3_RxR_OCCUPANCY_VN1.DRS",
brief_description:
"VN1 Ingress Occupancy Accumulator; DRS",
public_description:
Some("Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.; DRS Ingress Queue"),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_C_RING_IV_USED.ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(30),
umask:
Tuple::One(15),
event_name:
"UNC_C_RING_IV_USED.ANY",
brief_description:
"BL Ring in Use; Any",
public_description:
Some("Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring in HSX Therefore, if one wants to monitor the \'Even\' ring, they should select both UP_EVEN and DN_EVEN. To monitor the \'Odd\' ring, they should select both UP_ODD and DN_ODD.; Filters any polarity"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_R2_RING_AD_USED.CW_ODD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(7),
umask:
Tuple::One(2),
event_name:
"UNC_R2_RING_AD_USED.CW_ODD",
brief_description:
"R2 AD Ring in Use; Clockwise and Odd",
public_description:
Some("Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_P_DEMOTIONS_CORE17",
IntelPerformanceCounterDescription{event_code:
Tuple::One(65),
umask:
Tuple::One(0),
event_name:
"UNC_P_DEMOTIONS_CORE17",
brief_description:
"Core C State Demotions",
public_description:
Some("Counts the number of times when a configurable cores had a C-state demotion"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_R3_VNA_CREDITS_REJECT.DRS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(52),
umask:
Tuple::One(8),
event_name:
"UNC_R3_VNA_CREDITS_REJECT.DRS",
brief_description:
"VNA Credit Reject; DRS Message Class",
public_description:
Some("Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_H_IMC_WRITES.FULL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(26),
umask:
Tuple::One(1),
event_name:
"UNC_H_IMC_WRITES.FULL",
brief_description:
"HA to iMC Full Line Writes Issued; Full Line Non-ISOCH",
public_description:
Some("Counts the total number of full line writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_POWER_THROTTLE_CYCLES.RANK6",
IntelPerformanceCounterDescription{event_code:
Tuple::One(65),
umask:
Tuple::One(64),
event_name:
"UNC_M_POWER_THROTTLE_CYCLES.RANK6",
brief_description:
"Throttle Cycles for Rank 0; DIMM ID",
public_description:
Some("Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_C_TOR_INSERTS.REMOTE_OPCODE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(53),
umask:
Tuple::One(129),
event_name:
"UNC_C_TOR_INSERTS.REMOTE_OPCODE",
brief_description:
"TOR Inserts; Remote Memory - Opcode Matched",
public_description:
Some("Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent \'filters\' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select \'MISS_OPC_MATCH\' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions, satisifed by an opcode, inserted into the TOR that are satisifed by remote caches or remote memory."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
Some("CBoFilter1[28:20]"),
extsel:
false,}),
("UNC_Q_RxL_CYCLES_NE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(10),
umask:
Tuple::One(0),
event_name:
"UNC_Q_RxL_CYCLES_NE",
brief_description:
"RxQ Cycles Not Empty",
public_description:
Some("Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_C_RING_SRC_THRTL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(7),
umask:
Tuple::One(0),
event_name:
"UNC_C_RING_SRC_THRTL",
brief_description:
"Number of cycles the Cbo is actively throttling traffic onto the Ring in order to limit bounce traffic.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_I_TRANSACTIONS.READS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(22),
umask:
Tuple::One(1),
event_name:
"UNC_I_TRANSACTIONS.READS",
brief_description:
"Inbound Transaction Count; Reads",
public_description:
Some("Counts the number of \'Inbound\' transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only read requests (not including read prefetches)."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK0.BANKG3",
IntelPerformanceCounterDescription{event_code:
Tuple::One(184),
umask:
Tuple::One(20),
event_name:
"UNC_M_WR_CAS_RANK0.BANKG3",
brief_description:
"WR_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_H_TRACKER_CYCLES_FULL.GP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(2),
umask:
Tuple::One(1),
event_name:
"UNC_H_TRACKER_CYCLES_FULL.GP",
brief_description:
"Tracker Cycles Full; Cycles GP Completely Used",
public_description:
Some("Counts the number of cycles when the local HA tracker pool is completely used. This can be used with edge detect to identify the number of situations when the pool became fully utilized. This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure. In other words, the system could be starved for RTIDs but not fill up the HA trackers. HA trackers are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; Counts the number of cycles when the general purpose (GP) HA tracker pool (HT) is completely used. It will not return valid count when BT is disabled."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_CREDITS_CONSUMED_VN1.DRS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(57),
umask:
Tuple::One(1),
event_name:
"UNC_Q_RxL_CREDITS_CONSUMED_VN1.DRS",
brief_description:
"VN1 Credit Consumed; DRS",
public_description:
Some("Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the DRS message class."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_M_RD_CAS_RANK4.BANK6",
IntelPerformanceCounterDescription{event_code:
Tuple::One(180),
umask:
Tuple::One(6),
event_name:
"UNC_M_RD_CAS_RANK4.BANK6",
brief_description:
"RD_CAS Access to Rank 4; Bank 6",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_I_SNOOP_RESP.HIT_M",
IntelPerformanceCounterDescription{event_code:
Tuple::One(23),
umask:
Tuple::One(8),
event_name:
"UNC_I_SNOOP_RESP.HIT_M",
brief_description:
"Snoop Responses; Hit M",
public_description:
None,
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_S_RxR_INSERTS.BL_BNC",
IntelPerformanceCounterDescription{event_code:
Tuple::One(19),
umask:
Tuple::One(8),
event_name:
"UNC_S_RxR_INSERTS.BL_BNC",
brief_description:
"Ingress Allocations; BL - Bounces",
public_description:
Some("Number of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_S_RxR_BYPASS.AD_CRD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(18),
umask:
Tuple::One(1),
event_name:
"UNC_S_RxR_BYPASS.AD_CRD",
brief_description:
"Bypass; AD - Credits",
public_description:
Some("Bypass the Sbo Ingress."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_R3_RxR_CYCLES_NE_VN1.DRS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(20),
umask:
Tuple::One(8),
event_name:
"UNC_R3_RxR_CYCLES_NE_VN1.DRS",
brief_description:
"VN1 Ingress Cycles Not Empty; DRS",
public_description:
Some("Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; DRS Ingress Queue"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_R3_RING_AK_USED.CCW_ODD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(8),
umask:
Tuple::One(8),
event_name:
"UNC_R3_RING_AK_USED.CCW_ODD",
brief_description:
"R3 AK Ring in Use; Counterclockwise and Odd",
public_description:
Some("Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity."),
counter:
Counter::Programmable(7),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_C_TOR_OCCUPANCY.MISS_REMOTE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(54),
umask:
Tuple::One(138),
event_name:
"UNC_C_TOR_OCCUPANCY.MISS_REMOTE",
brief_description:
"TOR Occupancy",
public_description:
Some("For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent \'filters\' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select \'MISS_OPC_MATCH\' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)"),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_R3_HA_R2_BL_CREDITS_EMPTY.HA1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(45),
umask:
Tuple::One(2),
event_name:
"UNC_R3_HA_R2_BL_CREDITS_EMPTY.HA1",
brief_description:
"HA/R2 AD Credits Empty",
public_description:
Some("No credits available to send to either HA or R2 on the BL Ring; HA1"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_CYCLES_NE_DRS.VN1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(15),
umask:
Tuple::One(2),
event_name:
"UNC_Q_RxL_CYCLES_NE_DRS.VN1",
brief_description:
"RxQ Cycles Not Empty - DRS; for VN1",
public_description:
Some("Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors DRS flits only."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_Q_RxL_CRC_ERRORS.LINK_INIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(3),
umask:
Tuple::One(1),
event_name:
"UNC_Q_RxL_CRC_ERRORS.LINK_INIT",
brief_description:
"CRC Errors Detected; LinkInit",
public_description:
Some("Number of CRC errors detected in the QPI Agent. Each QPI flit incorporates 8 bits of CRC for error detection. This counts the number of flits where the CRC was able to detect an error. After an error has been detected, the QPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it).; CRC errors detected during link initialization."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_M_PREEMPTION.RD_PREEMPT_WR",
IntelPerformanceCounterDescription{event_code:
Tuple::One(8),
umask:
Tuple::One(2),
event_name:
"UNC_M_PREEMPTION.RD_PREEMPT_WR",
brief_description:
"Read Preemption Count; Read over Write Preemption",
public_description:
Some("Counts the number of times a read in the iMC preempts another read or write. Generally reads to an open page are issued ahead of requests to closed pages. This improves the page hit rate of the system. However, high priority requests can cause pages of active requests to be closed in order to get them out. This will reduce the latency of the high-priority request at the expense of lower bandwidth and increased overall average latency.; Filter for when a read preempts a write."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_S_TxR_INSERTS.IV",
IntelPerformanceCounterDescription{event_code:
Tuple::One(2),
umask:
Tuple::One(32),
event_name:
"UNC_S_TxR_INSERTS.IV",
brief_description:
"Egress Allocations; IV",
public_description:
Some("Number of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_H_OSB.REMOTE_USEFUL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(83),
umask:
Tuple::One(64),
event_name:
"UNC_H_OSB.REMOTE_USEFUL",
brief_description:
"OSB Snoop Broadcast; Remote - Useful",
public_description:
Some("Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_STALL_NO_SBO_CREDIT.SBO1_AD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(108),
umask:
Tuple::One(2),
event_name:
"UNC_H_STALL_NO_SBO_CREDIT.SBO1_AD",
brief_description:
"Stall on No Sbo Credits; For SBo1, AD Ring",
public_description:
Some("Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_OCCUPANCY_NCB.VN1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(22),
umask:
Tuple::One(2),
event_name:
"UNC_Q_RxL_OCCUPANCY_NCB.VN1",
brief_description:
"RxQ Occupancy - NCB; for VN1",
public_description:
Some("Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCB flits only."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_M_RD_CAS_RANK5.BANK14",
IntelPerformanceCounterDescription{event_code:
Tuple::One(181),
umask:
Tuple::One(14),
event_name:
"UNC_M_RD_CAS_RANK5.BANK14",
brief_description:
"RD_CAS Access to Rank 5; Bank 14",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_BL_CYCLES_NE.SCHED0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(53),
umask:
Tuple::One(1),
event_name:
"UNC_H_TxR_BL_CYCLES_NE.SCHED0",
brief_description:
"BL Egress Not Empty; Scheduler 0",
public_description:
Some("BL Egress Not Empty; Filter for cycles not empty from scheduler bank 0"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK1.BANK8",
IntelPerformanceCounterDescription{event_code:
Tuple::One(177),
umask:
Tuple::One(8),
event_name:
"UNC_M_RD_CAS_RANK1.BANK8",
brief_description:
"RD_CAS Access to Rank 1; Bank 8",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(34),
umask:
Tuple::One(1),
event_name:
"UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI0",
brief_description:
"Cycles without QPI Ingress Credits; AD to QPI Link 0",
public_description:
Some("Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent. This can be filtered by the different credit pools and the different links."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_TRACKER_OCCUPANCY.READS_REMOTE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(4),
umask:
Tuple::One(8),
event_name:
"UNC_H_TRACKER_OCCUPANCY.READS_REMOTE",
brief_description:
"Tracker Occupancy Accumultor; Remote Read Requests",
public_description:
Some("Accumulates the occupancy of the local HA tracker pool in every cycle. This can be used in conjection with the \'not empty\' stat to calculate average queue occupancy or the \'allocations\' stat in order to calculate average queue latency. HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_I_CLOCKTICKS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(0),
umask:
Tuple::One(0),
event_name:
"UNC_I_CLOCKTICKS",
brief_description:
"Clocks in the IRP",
public_description:
Some("Number of clocks in the IRP."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_U_CLOCKTICKS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(0),
umask:
Tuple::One(0),
event_name:
"UNC_U_CLOCKTICKS",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("UBOX"),
filter:
None,
extsel:
false,}),
("UNC_C_TOR_INSERTS.NID_OPCODE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(53),
umask:
Tuple::One(65),
event_name:
"UNC_C_TOR_INSERTS.NID_OPCODE",
brief_description:
"TOR Inserts; NID and Opcode Matched",
public_description:
Some("Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent \'filters\' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select \'MISS_OPC_MATCH\' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match a NID and an opcode."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
Some("CBoFilter1[28:20], CBoFilter1[15:0]"),
extsel:
false,}),
("UNC_M_WR_CAS_RANK5.BANK1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(189),
umask:
Tuple::One(1),
event_name:
"UNC_M_WR_CAS_RANK5.BANK1",
brief_description:
"WR_CAS Access to Rank 5; Bank 1",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_P_TOTAL_TRANSITION_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(114),
umask:
Tuple::One(0),
event_name:
"UNC_P_TOTAL_TRANSITION_CYCLES",
brief_description:
"Total Core C State Transition Cycles",
public_description:
Some("Number of cycles spent performing core C state transitions across all cores."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_H_RING_AD_USED.CCW_EVEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(62),
umask:
Tuple::One(4),
event_name:
"UNC_H_RING_AD_USED.CCW_EVEN",
brief_description:
"HA AD Ring in Use; Counterclockwise and Even",
public_description:
Some("Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxR_AD_SNP_CREDIT_OCCUPANCY.VN1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(35),
umask:
Tuple::One(2),
event_name:
"UNC_Q_TxR_AD_SNP_CREDIT_OCCUPANCY.VN1",
brief_description:
"R3QPI Egress Credit Occupancy - AD SNP; for VN1",
public_description:
Some("Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO fro Snoop messages on AD."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_H_RING_BL_USED.CCW_EVEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(64),
umask:
Tuple::One(4),
event_name:
"UNC_H_RING_BL_USED.CCW_EVEN",
brief_description:
"HA BL Ring in Use; Counterclockwise and Even",
public_description:
Some("Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_PRIO.MED",
IntelPerformanceCounterDescription{event_code:
Tuple::One(160),
umask:
Tuple::One(2),
event_name:
"UNC_M_RD_CAS_PRIO.MED",
brief_description:
"Read CAS issued with MEDIUM priority",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_S_RxR_CRD_STARVED.IFV",
IntelPerformanceCounterDescription{event_code:
Tuple::One(20),
umask:
Tuple::One(64),
event_name:
"UNC_S_RxR_CRD_STARVED.IFV",
brief_description:
"Injection Starvation; IVF Credit",
public_description:
Some("Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_C_TxR_INSERTS.AK_CACHE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(2),
umask:
Tuple::One(2),
event_name:
"UNC_C_TxR_INSERTS.AK_CACHE",
brief_description:
"Egress Allocations; AK - Cachebo",
public_description:
Some("Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the AK ring. This is commonly used for credit returns and GO responses."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(25),
umask:
Tuple::One(1),
event_name:
"UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN0",
brief_description:
"HA iMC CHN0 WPQ Credits Empty - Special; Channel 0",
public_description:
Some("Counts the number of cycles when there are no \'special\' credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC\'s WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and \'special\' requests such as ISOCH writes. This count only tracks the \'special\' credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_TRACKER_OCCUPANCY.READS_LOCAL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(4),
umask:
Tuple::One(4),
event_name:
"UNC_H_TRACKER_OCCUPANCY.READS_LOCAL",
brief_description:
"Tracker Occupancy Accumultor; Local Read Requests",
public_description:
Some("Accumulates the occupancy of the local HA tracker pool in every cycle. This can be used in conjection with the \'not empty\' stat to calculate average queue occupancy or the \'allocations\' stat in order to calculate average queue latency. HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_SNP_RESP_RECV_LOCAL.RSPI",
IntelPerformanceCounterDescription{event_code:
Tuple::One(96),
umask:
Tuple::One(1),
event_name:
"UNC_H_SNP_RESP_RECV_LOCAL.RSPI",
brief_description:
"Snoop Responses Received Local; RspI",
public_description:
Some("Number of snoop responses received for a Local request; Filters for snoops responses of RspI. RspI is returned when the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO hits non-modified data)."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_CYCLES_NE_SNP.VN1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(19),
umask:
Tuple::One(2),
event_name:
"UNC_Q_RxL_CYCLES_NE_SNP.VN1",
brief_description:
"RxQ Cycles Not Empty - SNP; for VN1",
public_description:
Some("Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors SNP flits only."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_NDR",
IntelPerformanceCounterDescription{event_code:
Tuple::One(33),
umask:
Tuple::One(64),
event_name:
"UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_NDR",
brief_description:
"QPI0 BL Credits Empty",
public_description:
Some("No credits available to send to QPI0 on the BL Ring; VN1 NDR Messages"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK5.BANKG1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(181),
umask:
Tuple::One(18),
event_name:
"UNC_M_RD_CAS_RANK5.BANKG1",
brief_description:
"RD_CAS Access to Rank 5; Bank Group 1 (Banks 4-7)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_POWER_CHANNEL_DLLOFF",
IntelPerformanceCounterDescription{event_code:
Tuple::One(132),
umask:
Tuple::One(0),
event_name:
"UNC_M_POWER_CHANNEL_DLLOFF",
brief_description:
"Channel DLLOFF Cycles",
public_description:
Some("Number of cycles when all the ranks in the channel are in CKE Slow (DLLOFF) mode."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_P_DEMOTIONS_CORE1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(49),
umask:
Tuple::One(0),
event_name:
"UNC_P_DEMOTIONS_CORE1",
brief_description:
"Core C State Demotions",
public_description:
Some("Counts the number of times when a configurable cores had a C-state demotion"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_H_TAD_REQUESTS_G0.REGION4",
IntelPerformanceCounterDescription{event_code:
Tuple::One(27),
umask:
Tuple::One(16),
event_name:
"UNC_H_TAD_REQUESTS_G0.REGION4",
brief_description:
"HA Requests to a TAD Region - Group 0; TAD Region 4",
public_description:
Some("Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for \'Monroe\' systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 4"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_REQUESTS.READS_REMOTE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(1),
umask:
Tuple::One(2),
event_name:
"UNC_H_REQUESTS.READS_REMOTE",
brief_description:
"Read and Write Requests; Remote Reads",
public_description:
Some("Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only read requests coming from the remote socket. This is a good proxy for LLC Read Misses (including RFOs) from the remote socket."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK4.BANK7",
IntelPerformanceCounterDescription{event_code:
Tuple::One(188),
umask:
Tuple::One(7),
event_name:
"UNC_M_WR_CAS_RANK4.BANK7",
brief_description:
"WR_CAS Access to Rank 4; Bank 7",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_CAS_COUNT.RD_UNDERFILL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(4),
umask:
Tuple::One(2),
event_name:
"UNC_M_CAS_COUNT.RD_UNDERFILL",
brief_description:
"DRAM RD_CAS and WR_CAS Commands.; Underfill Read Issued",
public_description:
Some("DRAM RD_CAS and WR_CAS Commands; Counts the number of underfill reads that are issued by the memory controller. This will generally be about the same as the number of partial writes, but may be slightly less because of partials hitting in the WPQ. While it is possible for underfills to be issed in both WMM and RMM, this event counts both."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_S_RING_AK_USED.UP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(28),
umask:
Tuple::One(3),
event_name:
"UNC_S_RING_AK_USED.UP",
brief_description:
"AK Ring In Use; Up",
public_description:
Some("Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the \'UP\' direction is on the clockwise ring and \'DN\' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_C_RxR_IRQ_RETRY2.TARGET",
IntelPerformanceCounterDescription{event_code:
Tuple::One(41),
umask:
Tuple::One(64),
event_name:
"UNC_C_RxR_IRQ_RETRY2.TARGET",
brief_description:
"Ingress Request Queue Rejects; Target Node Filter",
public_description:
Some("Counts the number of times that a request from the IPQ was retried filtered by the Target NodeID as specified in the Cbox\'s Filter register."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
Some("CBoFilter1[15:0]"),
extsel:
false,}),
("UNC_M_RD_CAS_RANK0.BANK1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(176),
umask:
Tuple::One(1),
event_name:
"UNC_M_RD_CAS_RANK0.BANK1",
brief_description:
"RD_CAS Access to Rank 0; Bank 1",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_C_QLRU.AGE0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(60),
umask:
Tuple::One(1),
event_name:
"UNC_C_QLRU.AGE0",
brief_description:
"LRU Queue; LRU Age 0",
public_description:
Some("How often age was set to 0"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_I_MISC0.2ND_WR_INSERT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(20),
umask:
Tuple::One(8),
event_name:
"UNC_I_MISC0.2ND_WR_INSERT",
brief_description:
"Misc Events - Set 0; Cache Inserts of Write Transactions as Secondary",
public_description:
None,
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_C_TOR_INSERTS.NID_WB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(53),
umask:
Tuple::One(80),
event_name:
"UNC_C_TOR_INSERTS.NID_WB",
brief_description:
"TOR Inserts; NID Matched Writebacks",
public_description:
Some("Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent \'filters\' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select \'MISS_OPC_MATCH\' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; NID matched write transactions inserted into the TOR."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
Some("CBoFilter1[15:0]"),
extsel:
false,}),
("UNC_R2_TxR_CYCLES_FULL.BL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(37),
umask:
Tuple::One(4),
event_name:
"UNC_R2_TxR_CYCLES_FULL.BL",
brief_description:
"Egress Cycles Full; BL",
public_description:
Some("Counts the number of cycles when the R2PCIe Egress buffer is full.; BL Egress Queue"),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_H_OSB.READS_LOCAL_USEFUL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(83),
umask:
Tuple::One(32),
event_name:
"UNC_H_OSB.READS_LOCAL_USEFUL",
brief_description:
"OSB Snoop Broadcast; Reads Local - Useful",
public_description:
Some("Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_S_TxR_STARVED.AD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(3),
umask:
Tuple::One(1),
event_name:
"UNC_S_TxR_STARVED.AD",
brief_description:
"Injection Starvation; Onto AD Ring",
public_description:
Some("Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxR_AD_HOM_CREDIT_ACQUIRED.VN1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(38),
umask:
Tuple::One(2),
event_name:
"UNC_Q_TxR_AD_HOM_CREDIT_ACQUIRED.VN1",
brief_description:
"R3QPI Egress Credit Occupancy - HOM; for VN1",
public_description:
Some("Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Home messages on AD."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_M_RD_CAS_RANK0.ALLBANKS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(176),
umask:
Tuple::One(16),
event_name:
"UNC_M_RD_CAS_RANK0.ALLBANKS",
brief_description:
"RD_CAS Access to Rank 0; All Banks",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK1.BANK6",
IntelPerformanceCounterDescription{event_code:
Tuple::One(185),
umask:
Tuple::One(6),
event_name:
"UNC_M_WR_CAS_RANK1.BANK6",
brief_description:
"WR_CAS Access to Rank 1; Bank 6",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_I_SNOOP_RESP.MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(23),
umask:
Tuple::One(1),
event_name:
"UNC_I_SNOOP_RESP.MISS",
brief_description:
"Snoop Responses; Miss",
public_description:
None,
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_NDR",
IntelPerformanceCounterDescription{event_code:
Tuple::One(47),
umask:
Tuple::One(8),
event_name:
"UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_NDR",
brief_description:
"QPI1 BL Credits Empty",
public_description:
Some("No credits available to send to QPI1 on the BL Ring; VN0 NDR Messages"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_M_POWER_THROTTLE_CYCLES.RANK5",
IntelPerformanceCounterDescription{event_code:
Tuple::One(65),
umask:
Tuple::One(32),
event_name:
"UNC_M_POWER_THROTTLE_CYCLES.RANK5",
brief_description:
"Throttle Cycles for Rank 0; DIMM ID",
public_description:
Some("Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_H_SBO0_CREDITS_ACQUIRED.AD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(104),
umask:
Tuple::One(1),
event_name:
"UNC_H_SBO0_CREDITS_ACQUIRED.AD",
brief_description:
"SBo0 Credits Acquired; For AD Ring",
public_description:
Some("Number of Sbo 0 credits acquired in a given cycle, per ring."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_I_RxR_BL_DRS_OCCUPANCY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(7),
umask:
Tuple::One(0),
event_name:
"UNC_I_RxR_BL_DRS_OCCUPANCY",
brief_description:
"tbd",
public_description:
Some("Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK5.BANK13",
IntelPerformanceCounterDescription{event_code:
Tuple::One(181),
umask:
Tuple::One(13),
event_name:
"UNC_M_RD_CAS_RANK5.BANK13",
brief_description:
"RD_CAS Access to Rank 5; Bank 13",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_AK_INSERTS.SCHED0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(47),
umask:
Tuple::One(1),
event_name:
"UNC_H_TxR_AK_INSERTS.SCHED0",
brief_description:
"AK Egress Allocations; Scheduler 0",
public_description:
Some("AK Egress Allocations; Filter for allocations from scheduler bank 0"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK7.ALLBANKS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(191),
umask:
Tuple::One(16),
event_name:
"UNC_M_WR_CAS_RANK7.ALLBANKS",
brief_description:
"WR_CAS Access to Rank 7; All Banks",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_CYCLES_NE_DRS.VN0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(15),
umask:
Tuple::One(1),
event_name:
"UNC_Q_RxL_CYCLES_NE_DRS.VN0",
brief_description:
"RxQ Cycles Not Empty - DRS; for VN0",
public_description:
Some("Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors DRS flits only."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_I_TRANSACTIONS.OTHER",
IntelPerformanceCounterDescription{event_code:
Tuple::One(22),
umask:
Tuple::One(32),
event_name:
"UNC_I_TRANSACTIONS.OTHER",
brief_description:
"Inbound Transaction Count; Other",
public_description:
Some("Counts the number of \'Inbound\' transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of \'other\' kinds of transactions."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_C_QLRU.AGE2",
IntelPerformanceCounterDescription{event_code:
Tuple::One(60),
umask:
Tuple::One(4),
event_name:
"UNC_C_QLRU.AGE2",
brief_description:
"LRU Queue; LRU Age 2",
public_description:
Some("How often age was set to 2"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxR_BL_NCB_CREDIT_ACQUIRED.VN1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(43),
umask:
Tuple::One(2),
event_name:
"UNC_Q_TxR_BL_NCB_CREDIT_ACQUIRED.VN1",
brief_description:
"R3QPI Egress Credit Occupancy - NCB; for VN1",
public_description:
Some("Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCB message class to BL Egress."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_S_RxR_BYPASS.BL_CRD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(18),
umask:
Tuple::One(4),
event_name:
"UNC_S_RxR_BYPASS.BL_CRD",
brief_description:
"Bypass; BL - Credits",
public_description:
Some("Bypass the Sbo Ingress."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK5.BANK11",
IntelPerformanceCounterDescription{event_code:
Tuple::One(189),
umask:
Tuple::One(11),
event_name:
"UNC_M_WR_CAS_RANK5.BANK11",
brief_description:
"WR_CAS Access to Rank 5; Bank 11",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_R3_VN0_CREDITS_USED.NCS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(54),
umask:
Tuple::One(32),
event_name:
"UNC_R3_VN0_CREDITS_USED.NCS",
brief_description:
"VN0 Credit Used; NCS Message Class",
public_description:
Some("Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Standard (NCS). NCS is commonly used for ?"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_R3_RxR_CYCLES_NE_VN1.NCB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(20),
umask:
Tuple::One(16),
event_name:
"UNC_R3_RxR_CYCLES_NE_VN1.NCB",
brief_description:
"VN1 Ingress Cycles Not Empty; NCB",
public_description:
Some("Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_R2_IIO_CREDIT.ISOCH_QPI1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(45),
umask:
Tuple::One(8),
event_name:
"UNC_R2_IIO_CREDIT.ISOCH_QPI1",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_C_TOR_OCCUPANCY.REMOTE_OPCODE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(54),
umask:
Tuple::One(129),
event_name:
"UNC_C_TOR_OCCUPANCY.REMOTE_OPCODE",
brief_description:
"TOR Occupancy; Remote Memory - Opcode Matched",
public_description:
Some("For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent \'filters\' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select \'MISS_OPC_MATCH\' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding transactions, satisifed by an opcode, in the TOR that are satisifed by remote caches or remote memory."),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
Some("CBoFilter1[28:20]"),
extsel:
false,}),
("UNC_H_SNP_RESP_RECV_LOCAL.RSPCNFLCT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(96),
umask:
Tuple::One(64),
event_name:
"UNC_H_SNP_RESP_RECV_LOCAL.RSPCNFLCT",
brief_description:
"Snoop Responses Received Local; RspCnflct",
public_description:
Some("Number of snoop responses received for a Local request; Filters for snoops responses of RspConflict. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent. This triggers conflict resolution hardware. This covers both RspCnflct and RspCnflctWbI."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_C_SBO_CREDIT_OCCUPANCY.AD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(62),
umask:
Tuple::One(1),
event_name:
"UNC_C_SBO_CREDIT_OCCUPANCY.AD",
brief_description:
"SBo Credits Occupancy; For AD Ring",
public_description:
Some("Number of Sbo credits in use in a given cycle, per ring. Each Cbo is assigned an Sbo it can communicate with."),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_I_MISC0.FAST_REJ",
IntelPerformanceCounterDescription{event_code:
Tuple::One(20),
umask:
Tuple::One(2),
event_name:
"UNC_I_MISC0.FAST_REJ",
brief_description:
"Misc Events - Set 0; Fastpath Rejects",
public_description:
None,
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_H_HITME_LOOKUP.ACKCNFLTWBI",
IntelPerformanceCounterDescription{event_code:
Tuple::One(112),
umask:
Tuple::One(4),
event_name:
"UNC_H_HITME_LOOKUP.ACKCNFLTWBI",
brief_description:
"Counts Number of times HitMe Cache is accessed; op is AckCnfltWbI",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK4.ALLBANKS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(188),
umask:
Tuple::One(16),
event_name:
"UNC_M_WR_CAS_RANK4.ALLBANKS",
brief_description:
"WR_CAS Access to Rank 4; All Banks",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_NDR",
IntelPerformanceCounterDescription{event_code:
Tuple::One(47),
umask:
Tuple::One(64),
event_name:
"UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_NDR",
brief_description:
"QPI1 BL Credits Empty",
public_description:
Some("No credits available to send to QPI1 on the BL Ring; VN1 NDR Messages"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(24),
umask:
Tuple::One(2),
event_name:
"UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN1",
brief_description:
"HA iMC CHN0 WPQ Credits Empty - Regular; Channel 1",
public_description:
Some("Counts the number of cycles when there are no \'regular\' credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC\'s WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and \'special\' requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxL_BYPASSED",
IntelPerformanceCounterDescription{event_code:
Tuple::One(5),
umask:
Tuple::One(0),
event_name:
"UNC_Q_TxL_BYPASSED",
brief_description:
"Tx Flit Buffer Bypassed",
public_description:
Some("Counts the number of times that an incoming flit was able to bypass the Tx flit buffer and pass directly out the QPI Link. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_R2_RING_AD_USED.CCW_EVEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(7),
umask:
Tuple::One(4),
event_name:
"UNC_R2_RING_AD_USED.CCW_EVEN",
brief_description:
"R2 AD Ring in Use; Counterclockwise and Even",
public_description:
Some("Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_R3_VN0_CREDITS_REJECT.NCB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(55),
umask:
Tuple::One(16),
event_name:
"UNC_R3_VN0_CREDITS_REJECT.NCB",
brief_description:
"VN0 Credit Acquisition Failed on DRS; NCB Message Class",
public_description:
Some("Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_C_LLC_VICTIMS.NID",
IntelPerformanceCounterDescription{event_code:
Tuple::One(55),
umask:
Tuple::One(64),
event_name:
"UNC_C_LLC_VICTIMS.NID",
brief_description:
"Lines Victimized; Victimized Lines that Match NID",
public_description:
Some("Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.; Qualify one of the other subevents by the Target NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid. In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
Some("CBoFilter1[17:10]"),
extsel:
false,}),
("UNC_C_RxR_INT_STARVED.IRQ",
IntelPerformanceCounterDescription{event_code:
Tuple::One(20),
umask:
Tuple::One(1),
event_name:
"UNC_C_RxR_INT_STARVED.IRQ",
brief_description:
"Ingress Internal Starvation Cycles; IRQ",
public_description:
Some("Counts cycles in internal starvation. This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.; Cycles with the IRQ in Internal Starvation."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_R3_HA_R2_BL_CREDITS_EMPTY.HA0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(45),
umask:
Tuple::One(1),
event_name:
"UNC_R3_HA_R2_BL_CREDITS_EMPTY.HA0",
brief_description:
"HA/R2 AD Credits Empty",
public_description:
Some("No credits available to send to either HA or R2 on the BL Ring; HA0"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_S_TxR_ADS_USED.AK",
IntelPerformanceCounterDescription{event_code:
Tuple::One(4),
umask:
Tuple::One(2),
event_name:
"UNC_S_TxR_ADS_USED.AK",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_R3_QPI1_AD_CREDITS_EMPTY.VNA",
IntelPerformanceCounterDescription{event_code:
Tuple::One(46),
umask:
Tuple::One(1),
event_name:
"UNC_R3_QPI1_AD_CREDITS_EMPTY.VNA",
brief_description:
"QPI1 AD Credits Empty",
public_description:
Some("No credits available to send to QPI1 on the AD Ring; VNA"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_P_POWER_STATE_OCCUPANCY.CORES_C0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(128),
umask:
Tuple::One(64),
event_name:
"UNC_P_POWER_STATE_OCCUPANCY.CORES_C0",
brief_description:
"Number of cores in C-State; C0 and C1",
public_description:
Some("This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_CYCLES_NE_HOM.VN1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(18),
umask:
Tuple::One(2),
event_name:
"UNC_Q_RxL_CYCLES_NE_HOM.VN1",
brief_description:
"RxQ Cycles Not Empty - HOM; for VN1",
public_description:
Some("Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors HOM flits only."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_SNP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(32),
umask:
Tuple::One(32),
event_name:
"UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_SNP",
brief_description:
"QPI0 AD Credits Empty",
public_description:
Some("No credits available to send to QPI0 on the AD Ring; VN1 SNP Messages"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_R3_SBO0_CREDIT_OCCUPANCY.BL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(42),
umask:
Tuple::One(2),
event_name:
"UNC_R3_SBO0_CREDIT_OCCUPANCY.BL",
brief_description:
"SBo0 Credits Occupancy; For BL Ring",
public_description:
Some("Number of Sbo 0 credits in use in a given cycle, per ring."),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_R3_VN1_CREDITS_REJECT.SNP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(57),
umask:
Tuple::One(2),
event_name:
"UNC_R3_VN1_CREDITS_REJECT.SNP",
brief_description:
"VN1 Credit Acquisition Failed on DRS; SNP Message Class",
public_description:
Some("Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_H_TAD_REQUESTS_G1.REGION11",
IntelPerformanceCounterDescription{event_code:
Tuple::One(28),
umask:
Tuple::One(8),
event_name:
"UNC_H_TAD_REQUESTS_G1.REGION11",
brief_description:
"HA Requests to a TAD Region - Group 1; TAD Region 11",
public_description:
Some("Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 8 to 10. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for \'Monroe\' systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 11"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_INSERTS_NCB.VN1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(10),
umask:
Tuple::One(2),
event_name:
"UNC_Q_RxL_INSERTS_NCB.VN1",
brief_description:
"Rx Flit Buffer Allocations - NCB; for VN1",
public_description:
Some("Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCB flits."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_H_TAD_REQUESTS_G0.REGION3",
IntelPerformanceCounterDescription{event_code:
Tuple::One(27),
umask:
Tuple::One(8),
event_name:
"UNC_H_TAD_REQUESTS_G0.REGION3",
brief_description:
"HA Requests to a TAD Region - Group 0; TAD Region 3",
public_description:
Some("Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for \'Monroe\' systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 3"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_TRACKER_OCCUPANCY.INVITOE_LOCAL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(4),
umask:
Tuple::One(64),
event_name:
"UNC_H_TRACKER_OCCUPANCY.INVITOE_LOCAL",
brief_description:
"Tracker Occupancy Accumultor; Local InvItoE Requests",
public_description:
Some("Accumulates the occupancy of the local HA tracker pool in every cycle. This can be used in conjection with the \'not empty\' stat to calculate average queue occupancy or the \'allocations\' stat in order to calculate average queue latency. HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_P_CORE2_TRANSITION_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(98),
umask:
Tuple::One(0),
event_name:
"UNC_P_CORE2_TRANSITION_CYCLES",
brief_description:
"Core C State Transition Cycles",
public_description:
Some("Number of cycles spent performing core C state transitions. There is one event per core."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_P_CORE3_TRANSITION_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(99),
umask:
Tuple::One(0),
event_name:
"UNC_P_CORE3_TRANSITION_CYCLES",
brief_description:
"Core C State Transition Cycles",
public_description:
Some("Number of cycles spent performing core C state transitions. There is one event per core."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK0.BANK2",
IntelPerformanceCounterDescription{event_code:
Tuple::One(176),
umask:
Tuple::One(2),
event_name:
"UNC_M_RD_CAS_RANK0.BANK2",
brief_description:
"RD_CAS Access to Rank 0; Bank 2",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_R3_RxR_INSERTS_VN1.DRS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(21),
umask:
Tuple::One(8),
event_name:
"UNC_R3_RxR_INSERTS_VN1.DRS",
brief_description:
"VN1 Ingress Allocations; DRS",
public_description:
Some("Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; DRS Ingress Queue"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_H_HITME_LOOKUP.ALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(112),
umask:
Tuple::One(255),
event_name:
"UNC_H_HITME_LOOKUP.ALL",
brief_description:
"Counts Number of times HitMe Cache is accessed; All Requests",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_R3_RxR_INSERTS_VN1.NCS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(21),
umask:
Tuple::One(32),
event_name:
"UNC_R3_RxR_INSERTS_VN1.NCS",
brief_description:
"VN1 Ingress Allocations; NCS",
public_description:
Some("Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(31),
umask:
Tuple::One(1),
event_name:
"UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN0",
brief_description:
"R3QPI Egress Credit Occupancy - BL DRS; for VN0",
public_description:
Some("Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. DRS message class to BL Egress."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_I_SNOOP_RESP.HIT_I",
IntelPerformanceCounterDescription{event_code:
Tuple::One(23),
umask:
Tuple::One(2),
event_name:
"UNC_I_SNOOP_RESP.HIT_I",
brief_description:
"Snoop Responses; Hit I",
public_description:
None,
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK7.BANKG0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(191),
umask:
Tuple::One(17),
event_name:
"UNC_M_WR_CAS_RANK7.BANKG0",
brief_description:
"WR_CAS Access to Rank 7; Bank Group 0 (Banks 0-3)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN_SHR",
IntelPerformanceCounterDescription{event_code:
Tuple::One(31),
umask:
Tuple::One(4),
event_name:
"UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN_SHR",
brief_description:
"R3QPI Egress Credit Occupancy - BL DRS; for Shared VN",
public_description:
Some("Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. DRS message class to BL Egress."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_H_RING_AK_USED.CCW",
IntelPerformanceCounterDescription{event_code:
Tuple::One(63),
umask:
Tuple::One(12),
event_name:
"UNC_H_RING_AK_USED.CCW",
brief_description:
"HA AK Ring in Use; Counterclockwise",
public_description:
Some("Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_C_TxR_STARVED.AK_BOTH",
IntelPerformanceCounterDescription{event_code:
Tuple::One(3),
umask:
Tuple::One(2),
event_name:
"UNC_C_TxR_STARVED.AK_BOTH",
brief_description:
"Injection Starvation; Onto AK Ring",
public_description:
Some("Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that both AK egresses spent in starvation"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_S_RING_IV_USED.DN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(30),
umask:
Tuple::One(12),
event_name:
"UNC_S_RING_IV_USED.DN",
brief_description:
"BL Ring in Use; Any",
public_description:
Some("Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. There is only 1 IV ring in HSX. Therefore, if one wants to monitor the \'Even\' ring, they should select both UP_EVEN and DN_EVEN. To monitor the \'Odd\' ring, they should select both UP_ODD and DN_ODD.; Filters any polarity"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_R3_VN1_CREDITS_REJECT.NCS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(57),
umask:
Tuple::One(32),
event_name:
"UNC_R3_VN1_CREDITS_REJECT.NCS",
brief_description:
"VN1 Credit Acquisition Failed on DRS; NCS Message Class",
public_description:
Some("Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for Non-Coherent Standard (NCS). NCS is commonly used for ?"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO4",
IntelPerformanceCounterDescription{event_code:
Tuple::One(34),
umask:
Tuple::One(16),
event_name:
"UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO4",
brief_description:
"CBox AD Credits Empty",
public_description:
Some("No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 4"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_AD_INSERTS.ALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(39),
umask:
Tuple::One(3),
event_name:
"UNC_H_TxR_AD_INSERTS.ALL",
brief_description:
"AD Egress Allocations; All",
public_description:
Some("AD Egress Allocations; Allocations from both schedulers"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_C_MISC.CVZERO_PREFETCH_VICTIM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(57),
umask:
Tuple::One(16),
event_name:
"UNC_C_MISC.CVZERO_PREFETCH_VICTIM",
brief_description:
"Cbo Misc; Clean Victim with raw CV=0",
public_description:
Some("Miscellaneous events in the Cbo."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_R2_CLOCKTICKS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(1),
umask:
Tuple::One(0),
event_name:
"UNC_R2_CLOCKTICKS",
brief_description:
"Number of uclks in domain",
public_description:
Some("Counts the number of uclks in the R2PCIe uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the R2PCIe is close to the Ubox, they generally should not diverge by more than a handful of cycles."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_S_RING_BL_USED.DOWN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(29),
umask:
Tuple::One(12),
event_name:
"UNC_S_RING_BL_USED.DOWN",
brief_description:
"BL Ring in Use; Down",
public_description:
Some("Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the \'UP\' direction is on the clockwise ring and \'DN\' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_C_RING_AD_USED.DOWN_ODD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(27),
umask:
Tuple::One(8),
event_name:
"UNC_C_RING_AD_USED.DOWN_ODD",
brief_description:
"AD Ring In Use; Down and Odd",
public_description:
Some("Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the \'UP\' direction is on the clockwise ring and \'DN\' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_C_LLC_LOOKUP.READ",
IntelPerformanceCounterDescription{event_code:
Tuple::One(52),
umask:
Tuple::One(33),
event_name:
"UNC_C_LLC_LOOKUP.READ",
brief_description:
"Cache Lookups; Any Read Request",
public_description:
Some("Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Read transactions"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
Some("CBoFilter0[22:18]"),
extsel:
false,}),
("UNC_I_MISC0.2ND_RD_INSERT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(20),
umask:
Tuple::One(4),
event_name:
"UNC_I_MISC0.2ND_RD_INSERT",
brief_description:
"Misc Events - Set 0; Cache Inserts of Read Transactions as Secondary",
public_description:
None,
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_FLITS_G2.NCB_NONDATA",
IntelPerformanceCounterDescription{event_code:
Tuple::One(3),
umask:
Tuple::One(8),
event_name:
"UNC_Q_RxL_FLITS_G2.NCB_NONDATA",
brief_description:
"Flits Received - Group 2; Non-Coherent non-data Rx Flits",
public_description:
Some("Counts the number of flits received from the QPI Link. This is one of three \'groups\' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each \'flit\' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four \'fits\', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI \'speed\' (for example, 8.0 GT/s), the \'transfers\' here refer to \'fits\'. Therefore, in L0, the system will transfer 1 \'flit\' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as \'data\' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual \'data\' and an additional 16 bits of other information. To calculate \'data\' bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass non-data flits. These packets are generally used to transmit non-coherent data across QPI, and the flits counted here are for headers and other non-data flits. This includes extended headers."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_C_RING_SINK_STARVED.AD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(6),
umask:
Tuple::One(1),
event_name:
"UNC_C_RING_SINK_STARVED.AD",
brief_description:
"AD",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_C_RING_IV_USED.UP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(30),
umask:
Tuple::One(3),
event_name:
"UNC_C_RING_IV_USED.UP",
brief_description:
"BL Ring in Use; Any",
public_description:
Some("Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring in HSX Therefore, if one wants to monitor the \'Even\' ring, they should select both UP_EVEN and DN_EVEN. To monitor the \'Odd\' ring, they should select both UP_ODD and DN_ODD.; Filters any polarity"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK7.BANK8",
IntelPerformanceCounterDescription{event_code:
Tuple::One(191),
umask:
Tuple::One(8),
event_name:
"UNC_M_WR_CAS_RANK7.BANK8",
brief_description:
"WR_CAS Access to Rank 7; Bank 8",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_FLITS_G2.NCB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(3),
umask:
Tuple::One(12),
event_name:
"UNC_Q_RxL_FLITS_G2.NCB",
brief_description:
"Flits Received - Group 2; Non-Coherent Rx Flits",
public_description:
Some("Counts the number of flits received from the QPI Link. This is one of three \'groups\' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each \'flit\' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four \'fits\', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI \'speed\' (for example, 8.0 GT/s), the \'transfers\' here refer to \'fits\'. Therefore, in L0, the system will transfer 1 \'flit\' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as \'data\' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual \'data\' and an additional 16 bits of other information. To calculate \'data\' bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass flits. These packets are generally used to transmit non-coherent data across QPI."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_H_DIRECTORY_LOOKUP.NO_SNP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(12),
umask:
Tuple::One(2),
event_name:
"UNC_H_DIRECTORY_LOOKUP.NO_SNP",
brief_description:
"Directory Lookups; Snoop Not Needed",
public_description:
Some("Counts the number of transactions that looked up the directory. Can be filtered by requests that had to snoop and those that did not have to.; Filters for transactions that did not have to send any snoops because the directory bit was clear."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_P_CORE16_TRANSITION_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(112),
umask:
Tuple::One(0),
event_name:
"UNC_P_CORE16_TRANSITION_CYCLES",
brief_description:
"Core C State Transition Cycles",
public_description:
Some("Number of cycles spent performing core C state transitions. There is one event per core."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_H_HITME_HIT.READ_OR_INVITOE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(113),
umask:
Tuple::One(1),
event_name:
"UNC_H_HITME_HIT.READ_OR_INVITOE",
brief_description:
"Counts Number of Hits in HitMe Cache; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_C_RxR_INSERTS.IRQ_REJ",
IntelPerformanceCounterDescription{event_code:
Tuple::One(19),
umask:
Tuple::One(2),
event_name:
"UNC_C_RxR_INSERTS.IRQ_REJ",
brief_description:
"Ingress Allocations; IRQ Rejected",
public_description:
Some("Counts number of allocations per cycle into the specified Ingress queue."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_R3_RING_BL_USED.CCW_EVEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(9),
umask:
Tuple::One(4),
event_name:
"UNC_R3_RING_BL_USED.CCW_EVEN",
brief_description:
"R3 BL Ring in Use; Counterclockwise and Even",
public_description:
Some("Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity."),
counter:
Counter::Programmable(7),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_C_TOR_OCCUPANCY.MISS_LOCAL_OPCODE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(54),
umask:
Tuple::One(35),
event_name:
"UNC_C_TOR_OCCUPANCY.MISS_LOCAL_OPCODE",
brief_description:
"TOR Occupancy; Misses to Local Memory - Opcode Matched",
public_description:
Some("For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent \'filters\' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select \'MISS_OPC_MATCH\' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss transactions, satisifed by an opcode, in the TOR that are satisifed by locally HOMed memory."),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
Some("CBoFilter1[28:20]"),
extsel:
false,}),
("UNC_Q_TxR_AD_SNP_CREDIT_ACQUIRED.VN0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(39),
umask:
Tuple::One(1),
event_name:
"UNC_Q_TxR_AD_SNP_CREDIT_ACQUIRED.VN0",
brief_description:
"R3QPI Egress Credit Occupancy - SNP; for VN0",
public_description:
Some("Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Snoop messages on AD."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_M_WR_CAS_RANK4.BANK11",
IntelPerformanceCounterDescription{event_code:
Tuple::One(188),
umask:
Tuple::One(11),
event_name:
"UNC_M_WR_CAS_RANK4.BANK11",
brief_description:
"WR_CAS Access to Rank 4; Bank 11",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK1.BANK4",
IntelPerformanceCounterDescription{event_code:
Tuple::One(185),
umask:
Tuple::One(4),
event_name:
"UNC_M_WR_CAS_RANK1.BANK4",
brief_description:
"WR_CAS Access to Rank 1; Bank 4",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_H_ADDR_OPC_MATCH.OPC",
IntelPerformanceCounterDescription{event_code:
Tuple::One(32),
umask:
Tuple::One(2),
event_name:
"UNC_H_ADDR_OPC_MATCH.OPC",
brief_description:
"QPI Address/Opcode Match; Opcode",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
Some("HA_OpcodeMatch[5:0]"),
extsel:
false,}),
("UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO14_16",
IntelPerformanceCounterDescription{event_code:
Tuple::One(31),
umask:
Tuple::One(64),
event_name:
"UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO14_16",
brief_description:
"CBox AD Credits Empty",
public_description:
Some("No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 14&16"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK6.BANK13",
IntelPerformanceCounterDescription{event_code:
Tuple::One(182),
umask:
Tuple::One(13),
event_name:
"UNC_M_RD_CAS_RANK6.BANK13",
brief_description:
"RD_CAS Access to Rank 6; Bank 13",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK0.BANK4",
IntelPerformanceCounterDescription{event_code:
Tuple::One(176),
umask:
Tuple::One(4),
event_name:
"UNC_M_RD_CAS_RANK0.BANK4",
brief_description:
"RD_CAS Access to Rank 0; Bank 4",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK1.BANKG2",
IntelPerformanceCounterDescription{event_code:
Tuple::One(185),
umask:
Tuple::One(19),
event_name:
"UNC_M_WR_CAS_RANK1.BANKG2",
brief_description:
"WR_CAS Access to Rank 1; Bank Group 2 (Banks 8-11)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_C_MISC.STARTED",
IntelPerformanceCounterDescription{event_code:
Tuple::One(57),
umask:
Tuple::One(4),
event_name:
"UNC_C_MISC.STARTED",
brief_description:
"Cbo Misc",
public_description:
Some("Miscellaneous events in the Cbo."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_AK_CYCLES_NE.ALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(49),
umask:
Tuple::One(3),
event_name:
"UNC_H_TxR_AK_CYCLES_NE.ALL",
brief_description:
"AK Egress Not Empty; All",
public_description:
Some("AK Egress Not Empty; Cycles full from both schedulers"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_S_RING_SINK_STARVED.IV_CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(6),
umask:
Tuple::One(8),
event_name:
"UNC_S_RING_SINK_STARVED.IV_CORE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK1.BANK7",
IntelPerformanceCounterDescription{event_code:
Tuple::One(185),
umask:
Tuple::One(7),
event_name:
"UNC_M_WR_CAS_RANK1.BANK7",
brief_description:
"WR_CAS Access to Rank 1; Bank 7",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_WPQ_CYCLES_NE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(33),
umask:
Tuple::One(0),
event_name:
"UNC_M_WPQ_CYCLES_NE",
brief_description:
"Write Pending Queue Not Empty",
public_description:
Some("Counts the number of cycles that the Write Pending Queue is not empty. This can then be used to calculate the average queue occupancy (in conjunction with the WPQ Occupancy Accumulation count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have \'posted\' to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(4),
umask:
Tuple::One(0),
event_name:
"UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES",
brief_description:
"Thermal Strongest Upper Limit Cycles",
public_description:
Some("Counts the number of cycles when thermal conditions are the upper limit on frequency. This is related to the THERMAL_THROTTLE CYCLES_ABOVE_TEMP event, which always counts cycles when we are above the thermal temperature. This event (STRONGEST_UPPER_LIMIT) is sampled at the output of the algorithm that determines the actual frequency, while THERMAL_THROTTLE looks at the input."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_C_MISC.RSPI_WAS_FSE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(57),
umask:
Tuple::One(1),
event_name:
"UNC_C_MISC.RSPI_WAS_FSE",
brief_description:
"Cbo Misc; Silent Snoop Eviction",
public_description:
Some("Miscellaneous events in the Cbo.; Counts the number of times when a Snoop hit in FSE states and triggered a silent eviction. This is useful because this information is lost in the PRE encodings."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxL_FLITS_G1.HOM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(0),
umask:
Tuple::One(6),
event_name:
"UNC_Q_TxL_FLITS_G1.HOM",
brief_description:
"Flits Transferred - Group 1; HOM Flits",
public_description:
Some("Counts the number of flits trasmitted across the QPI Link. This is one of three \'groups\' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each \'flit\' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four \'fits\', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI \'speed\' (for example, 8.0 GT/s), the \'transfers\' here refer to \'fits\'. Therefore, in L0, the system will transfer 1 \'flit\' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as \'data\' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual \'data\' and an additional 16 bits of other information. To calculate \'data\' bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of flits transmitted over QPI on the home channel."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_M_WR_CAS_RANK6.BANK3",
IntelPerformanceCounterDescription{event_code:
Tuple::One(190),
umask:
Tuple::One(3),
event_name:
"UNC_M_WR_CAS_RANK6.BANK3",
brief_description:
"WR_CAS Access to Rank 6; Bank 3",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(34),
umask:
Tuple::One(2),
event_name:
"UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO1",
brief_description:
"CBox AD Credits Empty",
public_description:
Some("No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 1"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_R3_IOT_CTS_LO.CTS0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(12),
umask:
Tuple::One(1),
event_name:
"UNC_R3_IOT_CTS_LO.CTS0",
brief_description:
"IOT Common Trigger Sequencer - Lo",
public_description:
Some("Debug Mask/Match Tie-Ins"),
counter:
Counter::Programmable(7),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK4.BANK1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(188),
umask:
Tuple::One(1),
event_name:
"UNC_M_WR_CAS_RANK4.BANK1",
brief_description:
"WR_CAS Access to Rank 4; Bank 1",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_H_DIRECTORY_LAT_OPT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(65),
umask:
Tuple::One(0),
event_name:
"UNC_H_DIRECTORY_LAT_OPT",
brief_description:
"Directory Lat Opt Return",
public_description:
Some("Directory Latency Optimization Data Return Path Taken. When directory mode is enabled and the directory retuned for a read is Dir=I, then data can be returned using a faster path if certain conditions are met (credits, free pipeline, etc)."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_STALLS_VN0.BGF_NCB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(53),
umask:
Tuple::One(2),
event_name:
"UNC_Q_RxL_STALLS_VN0.BGF_NCB",
brief_description:
"Stalls Sending to R3QPI on VN0; BGF Stall - SNP",
public_description:
Some("Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the SNP message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_M_CAS_COUNT.ALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(4),
umask:
Tuple::One(15),
event_name:
"UNC_M_CAS_COUNT.ALL",
brief_description:
"DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (w/ and w/out auto-pre)",
public_description:
Some("DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM CAS commands issued on this channel."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_H_DIRECT2CORE_CYCLES_DISABLED",
IntelPerformanceCounterDescription{event_code:
Tuple::One(18),
umask:
Tuple::One(0),
event_name:
"UNC_H_DIRECT2CORE_CYCLES_DISABLED",
brief_description:
"Cycles when Direct2Core was Disabled",
public_description:
Some("Number of cycles in which Direct2Core was disabled"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_S_RxR_BUSY_STARVED.AD_CRD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(21),
umask:
Tuple::One(1),
event_name:
"UNC_S_RxR_BUSY_STARVED.AD_CRD",
brief_description:
"Injection Starvation; AD - Credits",
public_description:
Some("Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress because a message (credited/bounceable) is being sent."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_R3_CLOCKTICKS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(1),
umask:
Tuple::One(0),
event_name:
"UNC_R3_CLOCKTICKS",
brief_description:
"Number of uclks in domain",
public_description:
Some("Counts the number of uclks in the QPI uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the QPI Agent is close to the Ubox, they generally should not diverge by more than a handful of cycles."),
counter:
Counter::Programmable(7),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_C_RING_IV_USED.DOWN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(30),
umask:
Tuple::One(204),
event_name:
"UNC_C_RING_IV_USED.DOWN",
brief_description:
"BL Ring in Use; Down",
public_description:
Some("Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring in HSX Therefore, if one wants to monitor the \'Even\' ring, they should select both UP_EVEN and DN_EVEN. To monitor the \'Odd\' ring, they should select both UP_ODD and DN_ODD.; Filters for Down polarity"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK6.BANK0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(190),
umask:
Tuple::One(0),
event_name:
"UNC_M_WR_CAS_RANK6.BANK0",
brief_description:
"WR_CAS Access to Rank 6; Bank 0",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_C_TOR_INSERTS.EVICTION",
IntelPerformanceCounterDescription{event_code:
Tuple::One(53),
umask:
Tuple::One(4),
event_name:
"UNC_C_TOR_INSERTS.EVICTION",
brief_description:
"TOR Inserts; Evictions",
public_description:
Some("Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent \'filters\' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select \'MISS_OPC_MATCH\' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Eviction transactions inserted into the TOR. Evictions can be quick, such as when the line is in the F, S, or E states and no core valid bits are set. They can also be longer if either CV bits are set (so the cores need to be snooped) and/or if there is a HitM (in which case it is necessary to write the request out to memory)."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_AD_CYCLES_NE.SCHED1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(41),
umask:
Tuple::One(2),
event_name:
"UNC_H_TxR_AD_CYCLES_NE.SCHED1",
brief_description:
"AD Egress Not Empty; Scheduler 1",
public_description:
Some("AD Egress Not Empty; Filter for cycles not empty from scheduler bank 1"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_R2_RING_IV_USED.ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(10),
umask:
Tuple::One(15),
event_name:
"UNC_R2_RING_IV_USED.ANY",
brief_description:
"R2 IV Ring in Use; Any",
public_description:
Some("Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK4.BANKG0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(180),
umask:
Tuple::One(17),
event_name:
"UNC_M_RD_CAS_RANK4.BANKG0",
brief_description:
"RD_CAS Access to Rank 4; Bank Group 0 (Banks 0-3)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_R3_VN0_CREDITS_REJECT.SNP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(55),
umask:
Tuple::One(2),
event_name:
"UNC_R3_VN0_CREDITS_REJECT.SNP",
brief_description:
"VN0 Credit Acquisition Failed on DRS; SNP Message Class",
public_description:
Some("Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_M_ECC_CORRECTABLE_ERRORS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(9),
umask:
Tuple::One(0),
event_name:
"UNC_M_ECC_CORRECTABLE_ERRORS",
brief_description:
"ECC Correctable Errors",
public_description:
Some("Counts the number of ECC errors detected and corrected by the iMC on this channel. This counter is only useful with ECC DRAM devices. This count will increment one time for each correction regardless of the number of bits corrected. The iMC can correct up to 4 bit errors in independent channel mode and 8 bit erros in lockstep mode."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_BYP_CMDS.ACT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(161),
umask:
Tuple::One(1),
event_name:
"UNC_M_BYP_CMDS.ACT",
brief_description:
"ACT command issued by 2 cycle bypass",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_R3_TxR_NACK.UP_AD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(38),
umask:
Tuple::One(8),
event_name:
"UNC_R3_TxR_NACK.UP_AD",
brief_description:
"Egress CCW NACK; AK CCW",
public_description:
Some("BL CounterClockwise Egress Queue"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_I_COHERENT_OPS.PCIDCAHINT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(19),
umask:
Tuple::One(32),
event_name:
"UNC_I_COHERENT_OPS.PCIDCAHINT",
brief_description:
"Coherent Ops; PCIDCAHin5t",
public_description:
Some("Counts the number of coherency related operations servied by the IRP"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_C_LLC_LOOKUP.ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(52),
umask:
Tuple::One(17),
event_name:
"UNC_C_LLC_LOOKUP.ANY",
brief_description:
"Cache Lookups; Any Request",
public_description:
Some("Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
Some("CBoFilter0[23:17]"),
extsel:
false,}),
("UNC_M_WR_CAS_RANK4.BANKG0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(188),
umask:
Tuple::One(17),
event_name:
"UNC_M_WR_CAS_RANK4.BANKG0",
brief_description:
"WR_CAS Access to Rank 4; Bank Group 0 (Banks 0-3)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_H_TRACKER_CYCLES_NE.LOCAL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(3),
umask:
Tuple::One(1),
event_name:
"UNC_H_TRACKER_CYCLES_NE.LOCAL",
brief_description:
"Tracker Cycles Not Empty; Local Requests",
public_description:
Some("Counts the number of cycles when the local HA tracker pool is not empty. This can be used with edge detect to identify the number of situations when the pool became empty. This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure. In other words, this buffer could be completely empty, but there may still be credits in use by the CBos. This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occpancy. HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; This filter includes only requests coming from the local socket."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_P_DEMOTIONS_CORE10",
IntelPerformanceCounterDescription{event_code:
Tuple::One(58),
umask:
Tuple::One(0),
event_name:
"UNC_P_DEMOTIONS_CORE10",
brief_description:
"Core C State Demotions",
public_description:
Some("Counts the number of times when a configurable cores had a C-state demotion"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_H_BYPASS_IMC.NOT_TAKEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(20),
umask:
Tuple::One(2),
event_name:
"UNC_H_BYPASS_IMC.NOT_TAKEN",
brief_description:
"HA to iMC Bypass; Not Taken",
public_description:
Some("Counts the number of times when the HA was able to bypass was attempted. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filted by when the bypass was taken and when it was not.; Filter for transactions that could not take the bypass."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_POWER_CKE_CYCLES.RANK3",
IntelPerformanceCounterDescription{event_code:
Tuple::One(131),
umask:
Tuple::One(8),
event_name:
"UNC_M_POWER_CKE_CYCLES.RANK3",
brief_description:
"CKE_ON_CYCLES by Rank; DIMM ID",
public_description:
Some("Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary)."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_H_HITME_HIT.WBMTOI",
IntelPerformanceCounterDescription{event_code:
Tuple::One(113),
umask:
Tuple::One(2),
event_name:
"UNC_H_HITME_HIT.WBMTOI",
brief_description:
"Counts Number of Hits in HitMe Cache; op is WbMtoI",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_REQUESTS.READS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(1),
umask:
Tuple::One(3),
event_name:
"UNC_H_REQUESTS.READS",
brief_description:
"Read and Write Requests; Reads",
public_description:
Some("Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).; Incoming ead requests. This is a good proxy for LLC Read Misses (including RFOs)."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN2",
IntelPerformanceCounterDescription{event_code:
Tuple::One(24),
umask:
Tuple::One(4),
event_name:
"UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN2",
brief_description:
"HA iMC CHN0 WPQ Credits Empty - Regular; Channel 2",
public_description:
Some("Counts the number of cycles when there are no \'regular\' credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC\'s WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and \'special\' requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_I_COHERENT_OPS.PCITOM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(19),
umask:
Tuple::One(16),
event_name:
"UNC_I_COHERENT_OPS.PCITOM",
brief_description:
"Coherent Ops; PCIItoM",
public_description:
Some("Counts the number of coherency related operations servied by the IRP"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_C_RING_BOUNCES.AD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(5),
umask:
Tuple::One(1),
event_name:
"UNC_C_RING_BOUNCES.AD",
brief_description:
"Number of LLC responses that bounced on the Ring.; AD",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_R2_RING_AK_USED.CCW",
IntelPerformanceCounterDescription{event_code:
Tuple::One(8),
umask:
Tuple::One(12),
event_name:
"UNC_R2_RING_AK_USED.CCW",
brief_description:
"R2 AK Ring in Use; Counterclockwise",
public_description:
Some("Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK5.BANK4",
IntelPerformanceCounterDescription{event_code:
Tuple::One(189),
umask:
Tuple::One(4),
event_name:
"UNC_M_WR_CAS_RANK5.BANK4",
brief_description:
"WR_CAS Access to Rank 5; Bank 4",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_S_RING_AD_USED.UP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(27),
umask:
Tuple::One(3),
event_name:
"UNC_S_RING_AD_USED.UP",
brief_description:
"AD Ring In Use; Up",
public_description:
Some("Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the \'UP\' direction is on the clockwise ring and \'DN\' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_P_PKG_RESIDENCY_C0_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(42),
umask:
Tuple::One(0),
event_name:
"UNC_P_PKG_RESIDENCY_C0_CYCLES",
brief_description:
"Package C State Residency - C0",
public_description:
Some("Counts the number of cycles when the package was in C0. This event can be used in conjunction with edge detect to count C0 entrances (or exits using invert). Residency events do not include transition times."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_P_CORE10_TRANSITION_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(106),
umask:
Tuple::One(0),
event_name:
"UNC_P_CORE10_TRANSITION_CYCLES",
brief_description:
"Core C State Transition Cycles",
public_description:
Some("Number of cycles spent performing core C state transitions. There is one event per core."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_H_RING_AK_USED.CCW_ODD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(63),
umask:
Tuple::One(8),
event_name:
"UNC_H_RING_AK_USED.CCW_ODD",
brief_description:
"HA AK Ring in Use; Counterclockwise and Odd",
public_description:
Some("Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_IMC_READS.NORMAL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(23),
umask:
Tuple::One(1),
event_name:
"UNC_H_IMC_READS.NORMAL",
brief_description:
"HA to iMC Normal Priority Reads Issued; Normal Priority",
public_description:
Some("Count of the number of reads issued to any of the memory controller channels. This can be filtered by the priority of the reads."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_BYP_CMDS.PRE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(161),
umask:
Tuple::One(4),
event_name:
"UNC_M_BYP_CMDS.PRE",
brief_description:
"PRE command issued by 2 cycle bypass",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_H_BT_TO_HT_NOT_ISSUED.RSPACKCFLT_HAZARD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(81),
umask:
Tuple::One(8),
event_name:
"UNC_H_BT_TO_HT_NOT_ISSUED.RSPACKCFLT_HAZARD",
brief_description:
"BT to HT Not Issued; Incoming Data Hazard",
public_description:
Some("Counts the number of cycles when the HA does not issue transaction from BT to HT.; Cycles unable to issue from BT due to incoming BL data hazard"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_S_RxR_OCCUPANCY.IV",
IntelPerformanceCounterDescription{event_code:
Tuple::One(17),
umask:
Tuple::One(32),
event_name:
"UNC_S_RxR_OCCUPANCY.IV",
brief_description:
"Ingress Occupancy; IV",
public_description:
Some("Occupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_H_REQUESTS.INVITOE_REMOTE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(1),
umask:
Tuple::One(32),
event_name:
"UNC_H_REQUESTS.INVITOE_REMOTE",
brief_description:
"Read and Write Requests; Remote InvItoEs",
public_description:
Some("Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only InvItoEs coming from remote sockets."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK5.BANKG3",
IntelPerformanceCounterDescription{event_code:
Tuple::One(189),
umask:
Tuple::One(20),
event_name:
"UNC_M_WR_CAS_RANK5.BANKG3",
brief_description:
"WR_CAS Access to Rank 5; Bank Group 3 (Banks 12-15)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK7.BANK0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(191),
umask:
Tuple::One(0),
event_name:
"UNC_M_WR_CAS_RANK7.BANK0",
brief_description:
"WR_CAS Access to Rank 7; Bank 0",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_P_PKG_RESIDENCY_C6_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(45),
umask:
Tuple::One(0),
event_name:
"UNC_P_PKG_RESIDENCY_C6_CYCLES",
brief_description:
"Package C State Residency - C6",
public_description:
Some("Counts the number of cycles when the package was in C6. This event can be used in conjunction with edge detect to count C6 entrances (or exits using invert). Residency events do not include transition times."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_P_CORE9_TRANSITION_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(105),
umask:
Tuple::One(0),
event_name:
"UNC_P_CORE9_TRANSITION_CYCLES",
brief_description:
"Core C State Transition Cycles",
public_description:
Some("Number of cycles spent performing core C state transitions. There is one event per core."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_R2_STALL_NO_SBO_CREDIT.SBO0_BL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(44),
umask:
Tuple::One(4),
event_name:
"UNC_R2_STALL_NO_SBO_CREDIT.SBO0_BL",
brief_description:
"Stall on No Sbo Credits; For SBo0, BL Ring",
public_description:
Some("Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_C_RxR_INSERTS.PRQ_REJ",
IntelPerformanceCounterDescription{event_code:
Tuple::One(19),
umask:
Tuple::One(32),
event_name:
"UNC_C_RxR_INSERTS.PRQ_REJ",
brief_description:
"Ingress Allocations; PRQ",
public_description:
Some("Counts number of allocations per cycle into the specified Ingress queue."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_C_RxR_EXT_STARVED.IPQ",
IntelPerformanceCounterDescription{event_code:
Tuple::One(18),
umask:
Tuple::One(2),
event_name:
"UNC_C_RxR_EXT_STARVED.IPQ",
brief_description:
"Ingress Arbiter Blocking Cycles; IRQ",
public_description:
Some("Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues.; IPQ is externally startved and therefore we are blocking the IRQ."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_R3_IOT_BACKPRESSURE.HUB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(11),
umask:
Tuple::One(2),
event_name:
"UNC_R3_IOT_BACKPRESSURE.HUB",
brief_description:
"IOT Backpressure",
public_description:
None,
counter:
Counter::Programmable(7),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxR_AK_NDR_CREDIT_OCCUPANCY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(37),
umask:
Tuple::One(0),
event_name:
"UNC_Q_TxR_AK_NDR_CREDIT_OCCUPANCY",
brief_description:
"R3QPI Egress Credit Occupancy - AK NDR",
public_description:
Some("Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. Local NDR message class to AK Egress."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_R2_SBO0_CREDITS_ACQUIRED.AD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(40),
umask:
Tuple::One(1),
event_name:
"UNC_R2_SBO0_CREDITS_ACQUIRED.AD",
brief_description:
"SBo0 Credits Acquired; For AD Ring",
public_description:
Some("Number of Sbo 0 credits acquired in a given cycle, per ring."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_S_RING_AK_USED.UP_ODD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(28),
umask:
Tuple::One(2),
event_name:
"UNC_S_RING_AK_USED.UP_ODD",
brief_description:
"AK Ring In Use; Up and Odd",
public_description:
Some("Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the \'UP\' direction is on the clockwise ring and \'DN\' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_H_STALL_NO_SBO_CREDIT.SBO1_BL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(108),
umask:
Tuple::One(8),
event_name:
"UNC_H_STALL_NO_SBO_CREDIT.SBO1_BL",
brief_description:
"Stall on No Sbo Credits; For SBo1, BL Ring",
public_description:
Some("Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_TRACKER_CYCLES_NE.ALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(3),
umask:
Tuple::One(3),
event_name:
"UNC_H_TRACKER_CYCLES_NE.ALL",
brief_description:
"Tracker Cycles Not Empty; All Requests",
public_description:
Some("Counts the number of cycles when the local HA tracker pool is not empty. This can be used with edge detect to identify the number of situations when the pool became empty. This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure. In other words, this buffer could be completely empty, but there may still be credits in use by the CBos. This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occpancy. HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; Requests coming from both local and remote sockets."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_INSERTS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(8),
umask:
Tuple::One(0),
event_name:
"UNC_Q_RxL_INSERTS",
brief_description:
"Rx Flit Buffer Allocations",
public_description:
Some("Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_C_RING_BL_USED.UP_ODD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(29),
umask:
Tuple::One(2),
event_name:
"UNC_C_RING_BL_USED.UP_ODD",
brief_description:
"BL Ring in Use; Up and Odd",
public_description:
Some("Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the \'UP\' direction is on the clockwise ring and \'DN\' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_M_WMM_TO_RMM.LOW_THRESH",
IntelPerformanceCounterDescription{event_code:
Tuple::One(192),
umask:
Tuple::One(1),
event_name:
"UNC_M_WMM_TO_RMM.LOW_THRESH",
brief_description:
"Transition from WMM to RMM because of low threshold; Transition from WMM to RMM because of starve counter",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(30),
umask:
Tuple::One(2),
event_name:
"UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCB",
brief_description:
"VN0 Credit Consumed; NCB",
public_description:
Some("Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the NCB message class."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_C_RxR_OCCUPANCY.PRQ_REJ",
IntelPerformanceCounterDescription{event_code:
Tuple::One(17),
umask:
Tuple::One(32),
event_name:
"UNC_C_RxR_OCCUPANCY.PRQ_REJ",
brief_description:
"Ingress Occupancy; PRQ Rejects",
public_description:
Some("Counts number of entries in the specified Ingress queue in each cycle."),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_H_HITME_HIT.RSPFWDS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(113),
umask:
Tuple::One(64),
event_name:
"UNC_H_HITME_HIT.RSPFWDS",
brief_description:
"Counts Number of Hits in HitMe Cache; op is RsSFwd or RspSFwdWb",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_S_TxR_INSERTS.BL_BNC",
IntelPerformanceCounterDescription{event_code:
Tuple::One(2),
umask:
Tuple::One(8),
event_name:
"UNC_S_TxR_INSERTS.BL_BNC",
brief_description:
"Egress Allocations; BL - Bounces",
public_description:
Some("Number of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_S_RING_AK_USED.DOWN_ODD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(28),
umask:
Tuple::One(8),
event_name:
"UNC_S_RING_AK_USED.DOWN_ODD",
brief_description:
"AK Ring In Use; Down and Odd",
public_description:
Some("Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the \'UP\' direction is on the clockwise ring and \'DN\' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN3",
IntelPerformanceCounterDescription{event_code:
Tuple::One(21),
umask:
Tuple::One(8),
event_name:
"UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN3",
brief_description:
"iMC RPQ Credits Empty - Regular; Channel 3",
public_description:
Some("Counts the number of cycles when there are no \'regular\' credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC\'s RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and \'special\' requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_S_RxR_BYPASS.AD_BNC",
IntelPerformanceCounterDescription{event_code:
Tuple::One(18),
umask:
Tuple::One(2),
event_name:
"UNC_S_RxR_BYPASS.AD_BNC",
brief_description:
"Bypass; AD - Bounces",
public_description:
Some("Bypass the Sbo Ingress."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxR_BL_NCS_CREDIT_ACQUIRED.VN1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(44),
umask:
Tuple::One(2),
event_name:
"UNC_Q_TxR_BL_NCS_CREDIT_ACQUIRED.VN1",
brief_description:
"R3QPI Egress Credit Occupancy - NCS; for VN1",
public_description:
Some("Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCS message class to BL Egress."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_R3_RxR_CYCLES_NE_VN1.HOM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(20),
umask:
Tuple::One(1),
event_name:
"UNC_R3_RxR_CYCLES_NE_VN1.HOM",
brief_description:
"VN1 Ingress Cycles Not Empty; HOM",
public_description:
Some("Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_I_MISC1.SLOW_M",
IntelPerformanceCounterDescription{event_code:
Tuple::One(21),
umask:
Tuple::One(8),
event_name:
"UNC_I_MISC1.SLOW_M",
brief_description:
"Misc Events - Set 1; Slow Transfer of M Line",
public_description:
Some("Snoop took cacheline ownership before write from data was committed."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_H_RING_AK_USED.CW_ODD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(63),
umask:
Tuple::One(2),
event_name:
"UNC_H_RING_AK_USED.CW_ODD",
brief_description:
"HA AK Ring in Use; Clockwise and Odd",
public_description:
Some("Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_BL.DRS_CACHE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(16),
umask:
Tuple::One(1),
event_name:
"UNC_H_TxR_BL.DRS_CACHE",
brief_description:
"Outbound DRS Ring Transactions to Cache; Data to Cache",
public_description:
Some("Counts the number of DRS messages sent out on the BL ring. This can be filtered by the destination.; Filter for data being sent to the cache."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_TAD_REQUESTS_G1.REGION10",
IntelPerformanceCounterDescription{event_code:
Tuple::One(28),
umask:
Tuple::One(4),
event_name:
"UNC_H_TAD_REQUESTS_G1.REGION10",
brief_description:
"HA Requests to a TAD Region - Group 1; TAD Region 10",
public_description:
Some("Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 8 to 10. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for \'Monroe\' systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 10"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxL_CRC_NO_CREDITS.ALMOST_FULL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(2),
umask:
Tuple::One(2),
event_name:
"UNC_Q_TxL_CRC_NO_CREDITS.ALMOST_FULL",
brief_description:
"Cycles Stalled with no LLR Credits; LLR is almost full",
public_description:
Some("Number of cycles when the Tx side ran out of Link Layer Retry credits, causing the Tx to stall.; When LLR is almost full, we block some but not all packets."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK7.BANKG3",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(20),
event_name:
"UNC_M_RD_CAS_RANK7.BANKG3",
brief_description:
"RD_CAS Access to Rank 7; Bank Group 3 (Banks 12-15)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_P_DEMOTIONS_CORE6",
IntelPerformanceCounterDescription{event_code:
Tuple::One(54),
umask:
Tuple::One(0),
event_name:
"UNC_P_DEMOTIONS_CORE6",
brief_description:
"Core C State Demotions",
public_description:
Some("Counts the number of times when a configurable cores had a C-state demotion"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_P_POWER_STATE_OCCUPANCY.CORES_C3",
IntelPerformanceCounterDescription{event_code:
Tuple::One(128),
umask:
Tuple::One(128),
event_name:
"UNC_P_POWER_STATE_OCCUPANCY.CORES_C3",
brief_description:
"Number of cores in C-State; C3",
public_description:
Some("This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_FLITS_G1.DRS_NONDATA",
IntelPerformanceCounterDescription{event_code:
Tuple::One(2),
umask:
Tuple::One(16),
event_name:
"UNC_Q_RxL_FLITS_G1.DRS_NONDATA",
brief_description:
"Flits Received - Group 1; DRS Header Flits",
public_description:
Some("Counts the number of flits received from the QPI Link. This is one of three \'groups\' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each \'flit\' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four \'fits\', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI \'speed\' (for example, 8.0 GT/s), the \'transfers\' here refer to \'fits\'. Therefore, in L0, the system will transfer 1 \'flit\' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as \'data\' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual \'data\' and an additional 16 bits of other information. To calculate \'data\' bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of protocol flits received over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits received over the NCB channel which transmits non-coherent data. This includes only the header flits (not the data). This includes extended headers."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_Q_TxL_FLITS_G2.NCS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(1),
umask:
Tuple::One(16),
event_name:
"UNC_Q_TxL_FLITS_G2.NCS",
brief_description:
"Flits Transferred - Group 2; Non-Coherent standard Tx Flits",
public_description:
Some("Counts the number of flits trasmitted across the QPI Link. This is one of three \'groups\' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each \'flit\' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four \'fits\', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI \'speed\' (for example, 8.0 GT/s), the \'transfers\' here refer to \'fits\'. Therefore, in L0, the system will transfer 1 \'flit\' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as \'data\' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual \'data\' and an additional 16 bits of other information. To calculate \'data\' bandwidth, one should therefore do: data flits * 8B / time.; Number of NCS (non-coherent standard) flits transmitted over QPI. This includes extended headers."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_S_RING_AD_USED.UP_ODD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(27),
umask:
Tuple::One(2),
event_name:
"UNC_S_RING_AD_USED.UP_ODD",
brief_description:
"AD Ring In Use; Up and Odd",
public_description:
Some("Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the \'UP\' direction is on the clockwise ring and \'DN\' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_HOM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(47),
umask:
Tuple::One(16),
event_name:
"UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_HOM",
brief_description:
"QPI1 BL Credits Empty",
public_description:
Some("No credits available to send to QPI1 on the BL Ring; VN1 HOM Messages"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_C_TOR_OCCUPANCY.LOCAL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(54),
umask:
Tuple::One(40),
event_name:
"UNC_C_TOR_OCCUPANCY.LOCAL",
brief_description:
"TOR Occupancy",
public_description:
Some("For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent \'filters\' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select \'MISS_OPC_MATCH\' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)"),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK5.BANK8",
IntelPerformanceCounterDescription{event_code:
Tuple::One(189),
umask:
Tuple::One(8),
event_name:
"UNC_M_WR_CAS_RANK5.BANK8",
brief_description:
"WR_CAS Access to Rank 5; Bank 8",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK6.BANK11",
IntelPerformanceCounterDescription{event_code:
Tuple::One(190),
umask:
Tuple::One(11),
event_name:
"UNC_M_WR_CAS_RANK6.BANK11",
brief_description:
"WR_CAS Access to Rank 6; Bank 11",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI2",
IntelPerformanceCounterDescription{event_code:
Tuple::One(34),
umask:
Tuple::One(16),
event_name:
"UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI2",
brief_description:
"Cycles without QPI Ingress Credits; BL to QPI Link 0",
public_description:
Some("Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent. This can be filtered by the different credit pools and the different links."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_IOT_CTS_HI.CTS3",
IntelPerformanceCounterDescription{event_code:
Tuple::One(101),
umask:
Tuple::One(2),
event_name:
"UNC_H_IOT_CTS_HI.CTS3",
brief_description:
"IOT Common Trigger Sequencer - Hi",
public_description:
Some("Debug Mask/Match Tie-Ins"),
counter:
Counter::Programmable(7),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_R2_RING_AD_USED.CCW_ODD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(7),
umask:
Tuple::One(8),
event_name:
"UNC_R2_RING_AD_USED.CCW_ODD",
brief_description:
"R2 AD Ring in Use; Counterclockwise and Odd",
public_description:
Some("Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_M_CAS_COUNT.RD_REG",
IntelPerformanceCounterDescription{event_code:
Tuple::One(4),
umask:
Tuple::One(1),
event_name:
"UNC_M_CAS_COUNT.RD_REG",
brief_description:
"DRAM RD_CAS and WR_CAS Commands.; All DRAM RD_CAS (w/ and w/out auto-pre)",
public_description:
Some("DRAM RD_CAS and WR_CAS Commands; Counts the total number or DRAM Read CAS commands issued on this channel. This includes both regular RD CAS commands as well as those with implicit Precharge. AutoPre is only used in systems that are using closed page policy. We do not filter based on major mode, as RD_CAS is not issued during WMM (with the exception of underfills)."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK5.BANK5",
IntelPerformanceCounterDescription{event_code:
Tuple::One(189),
umask:
Tuple::One(5),
event_name:
"UNC_M_WR_CAS_RANK5.BANK5",
brief_description:
"WR_CAS Access to Rank 5; Bank 5",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_R3_VN0_CREDITS_USED.SNP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(54),
umask:
Tuple::One(2),
event_name:
"UNC_R3_VN0_CREDITS_USED.SNP",
brief_description:
"VN0 Credit Used; SNP Message Class",
public_description:
Some("Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_C_TxR_STARVED.AD_CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(3),
umask:
Tuple::One(16),
event_name:
"UNC_C_TxR_STARVED.AD_CORE",
brief_description:
"Injection Starvation; Onto AD Ring (to core)",
public_description:
Some("Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that the core AD egress spent in starvation"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_R2_TxR_NACK_CW.DN_AK",
IntelPerformanceCounterDescription{event_code:
Tuple::One(38),
umask:
Tuple::One(4),
event_name:
"UNC_R2_TxR_NACK_CW.DN_AK",
brief_description:
"Egress CCW NACK; AK CCW",
public_description:
Some("AK CounterClockwise Egress Queue"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK6.BANKG0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(190),
umask:
Tuple::One(17),
event_name:
"UNC_M_WR_CAS_RANK6.BANKG0",
brief_description:
"WR_CAS Access to Rank 6; Bank Group 0 (Banks 0-3)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK0.BANK5",
IntelPerformanceCounterDescription{event_code:
Tuple::One(176),
umask:
Tuple::One(5),
event_name:
"UNC_M_RD_CAS_RANK0.BANK5",
brief_description:
"RD_CAS Access to Rank 0; Bank 5",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_C_RxR_IPQ_RETRY.FULL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(49),
umask:
Tuple::One(2),
event_name:
"UNC_C_RxR_IPQ_RETRY.FULL",
brief_description:
"Probe Queue Retries; No Egress Credits",
public_description:
Some("Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.; Counts the number of times that a request form the IPQ was retried because of a TOR reject from the Egress being full. IPQ requests make use of the AD Egress for regular responses, the BL egress to forward data, and the AK egress to return credits."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_R3_RING_AK_USED.CW_EVEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(8),
umask:
Tuple::One(1),
event_name:
"UNC_R3_RING_AK_USED.CW_EVEN",
brief_description:
"R3 AK Ring in Use; Clockwise and Even",
public_description:
Some("Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity."),
counter:
Counter::Programmable(7),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(34),
umask:
Tuple::One(4),
event_name:
"UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI0",
brief_description:
"Cycles without QPI Ingress Credits; BL to QPI Link 0",
public_description:
Some("Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent. This can be filtered by the different credit pools and the different links."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_C_TOR_OCCUPANCY.NID_MISS_ALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(54),
umask:
Tuple::One(74),
event_name:
"UNC_C_TOR_OCCUPANCY.NID_MISS_ALL",
brief_description:
"TOR Occupancy; NID Matched",
public_description:
Some("For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent \'filters\' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select \'MISS_OPC_MATCH\' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss requests in the TOR that match a NID."),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
Some("CBoFilter1[15:0]"),
extsel:
false,}),
("UNC_M_WR_CAS_RANK7.BANK7",
IntelPerformanceCounterDescription{event_code:
Tuple::One(191),
umask:
Tuple::One(7),
event_name:
"UNC_M_WR_CAS_RANK7.BANK7",
brief_description:
"WR_CAS Access to Rank 7; Bank 7",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_S_TxR_INSERTS.AD_BNC",
IntelPerformanceCounterDescription{event_code:
Tuple::One(2),
umask:
Tuple::One(2),
event_name:
"UNC_S_TxR_INSERTS.AD_BNC",
brief_description:
"Egress Allocations; AD - Bounces",
public_description:
Some("Number of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_R2_RING_BL_USED.CCW_ODD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(9),
umask:
Tuple::One(8),
event_name:
"UNC_R2_RING_BL_USED.CCW_ODD",
brief_description:
"R2 BL Ring in Use; Counterclockwise and Odd",
public_description:
Some("Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_H_OSB.READS_LOCAL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(83),
umask:
Tuple::One(2),
event_name:
"UNC_H_OSB.READS_LOCAL",
brief_description:
"OSB Snoop Broadcast; Local Reads",
public_description:
Some("Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxL_FLITS_G2.NDR_AD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(1),
umask:
Tuple::One(1),
event_name:
"UNC_Q_TxL_FLITS_G2.NDR_AD",
brief_description:
"Flits Transferred - Group 2; Non-Data Response Tx Flits - AD",
public_description:
Some("Counts the number of flits trasmitted across the QPI Link. This is one of three \'groups\' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each \'flit\' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four \'fits\', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI \'speed\' (for example, 8.0 GT/s), the \'transfers\' here refer to \'fits\'. Therefore, in L0, the system will transfer 1 \'flit\' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as \'data\' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual \'data\' and an additional 16 bits of other information. To calculate \'data\' bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets to the local socket which use the AK ring."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_H_TxR_BL_INSERTS.SCHED1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(51),
umask:
Tuple::One(2),
event_name:
"UNC_H_TxR_BL_INSERTS.SCHED1",
brief_description:
"BL Egress Allocations; Scheduler 1",
public_description:
Some("BL Egress Allocations; Filter for allocations from scheduler bank 1"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_R2_RING_BL_USED.CCW",
IntelPerformanceCounterDescription{event_code:
Tuple::One(9),
umask:
Tuple::One(12),
event_name:
"UNC_R2_RING_BL_USED.CCW",
brief_description:
"R2 BL Ring in Use; Counterclockwise",
public_description:
Some("Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_C_TOR_OCCUPANCY.NID_EVICTION",
IntelPerformanceCounterDescription{event_code:
Tuple::One(54),
umask:
Tuple::One(68),
event_name:
"UNC_C_TOR_OCCUPANCY.NID_EVICTION",
brief_description:
"TOR Occupancy; NID Matched Evictions",
public_description:
Some("For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent \'filters\' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select \'MISS_OPC_MATCH\' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding NID matched eviction transactions in the TOR ."),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
Some("CBoFilter1[15:0]"),
extsel:
false,}),
("UNC_M_WR_CAS_RANK5.BANK6",
IntelPerformanceCounterDescription{event_code:
Tuple::One(189),
umask:
Tuple::One(6),
event_name:
"UNC_M_WR_CAS_RANK5.BANK6",
brief_description:
"WR_CAS Access to Rank 5; Bank 6",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_CYCLES_NE_HOM.VN0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(18),
umask:
Tuple::One(1),
event_name:
"UNC_Q_RxL_CYCLES_NE_HOM.VN0",
brief_description:
"RxQ Cycles Not Empty - HOM; for VN0",
public_description:
Some("Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors HOM flits only."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_M_WR_CAS_RANK7.BANK14",
IntelPerformanceCounterDescription{event_code:
Tuple::One(191),
umask:
Tuple::One(14),
event_name:
"UNC_M_WR_CAS_RANK7.BANK14",
brief_description:
"WR_CAS Access to Rank 7; Bank 14",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_H_IMC_WRITES.ALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(26),
umask:
Tuple::One(15),
event_name:
"UNC_H_IMC_WRITES.ALL",
brief_description:
"HA to iMC Full Line Writes Issued; All Writes",
public_description:
Some("Counts the total number of full line writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_R3_RxR_INSERTS.NCS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(17),
umask:
Tuple::One(32),
event_name:
"UNC_R3_RxR_INSERTS.NCS",
brief_description:
"Ingress Allocations; NCS",
public_description:
Some("Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_C_RxR_EXT_STARVED.ISMQ_BIDS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(18),
umask:
Tuple::One(8),
event_name:
"UNC_C_RxR_EXT_STARVED.ISMQ_BIDS",
brief_description:
"Ingress Arbiter Blocking Cycles; ISMQ_BID",
public_description:
Some("Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues.; Number of times that the ISMQ Bid."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_BL_CYCLES_FULL.ALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(54),
umask:
Tuple::One(3),
event_name:
"UNC_H_TxR_BL_CYCLES_FULL.ALL",
brief_description:
"BL Egress Full; All",
public_description:
Some("BL Egress Full; Cycles full from both schedulers"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK7.BANKG1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(18),
event_name:
"UNC_M_RD_CAS_RANK7.BANKG1",
brief_description:
"RD_CAS Access to Rank 7; Bank Group 1 (Banks 4-7)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_S_RING_BL_USED.UP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(29),
umask:
Tuple::One(3),
event_name:
"UNC_S_RING_BL_USED.UP",
brief_description:
"BL Ring in Use; Up",
public_description:
Some("Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the \'UP\' direction is on the clockwise ring and \'DN\' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_R3_VNA_CREDITS_REJECT.NDR",
IntelPerformanceCounterDescription{event_code:
Tuple::One(52),
umask:
Tuple::One(4),
event_name:
"UNC_R3_VNA_CREDITS_REJECT.NDR",
brief_description:
"VNA Credit Reject; NDR Message Class",
public_description:
Some("Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP)."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK5.BANK1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(181),
umask:
Tuple::One(1),
event_name:
"UNC_M_RD_CAS_RANK5.BANK1",
brief_description:
"RD_CAS Access to Rank 5; Bank 1",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_R3_VN1_CREDITS_USED.NDR",
IntelPerformanceCounterDescription{event_code:
Tuple::One(56),
umask:
Tuple::One(4),
event_name:
"UNC_R3_VN1_CREDITS_USED.NDR",
brief_description:
"VN1 Credit Used; NDR Message Class",
public_description:
Some("Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP)."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_C_TxR_STARVED.BL_BOTH",
IntelPerformanceCounterDescription{event_code:
Tuple::One(3),
umask:
Tuple::One(4),
event_name:
"UNC_C_TxR_STARVED.BL_BOTH",
brief_description:
"Injection Starvation; Onto BL Ring",
public_description:
Some("Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that both BL egresses spent in starvation"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_H_HITME_HIT_PV_BITS_SET.WBMTOE_OR_S",
IntelPerformanceCounterDescription{event_code:
Tuple::One(114),
umask:
Tuple::One(8),
event_name:
"UNC_H_HITME_HIT_PV_BITS_SET.WBMTOE_OR_S",
brief_description:
"Accumulates Number of PV bits set on HitMe Cache Hits; op is WbMtoE or WbMtoS",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_R3_RxR_INSERTS_VN1.NDR",
IntelPerformanceCounterDescription{event_code:
Tuple::One(21),
umask:
Tuple::One(4),
event_name:
"UNC_R3_RxR_INSERTS_VN1.NDR",
brief_description:
"VN1 Ingress Allocations; NDR",
public_description:
Some("Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_H_HITME_HIT_PV_BITS_SET.RSP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(114),
umask:
Tuple::One(128),
event_name:
"UNC_H_HITME_HIT_PV_BITS_SET.RSP",
brief_description:
"Accumulates Number of PV bits set on HitMe Cache Hits; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_I_MISC1.SEC_RCVD_INVLD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(21),
umask:
Tuple::One(32),
event_name:
"UNC_I_MISC1.SEC_RCVD_INVLD",
brief_description:
"Misc Events - Set 1; Received Invalid",
public_description:
Some("Secondary received a transfer that did not have sufficient MESI state"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK0.BANKG0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(184),
umask:
Tuple::One(17),
event_name:
"UNC_M_WR_CAS_RANK0.BANKG0",
brief_description:
"WR_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_H_HITME_LOOKUP.INVALS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(112),
umask:
Tuple::One(38),
event_name:
"UNC_H_HITME_LOOKUP.INVALS",
brief_description:
"Counts Number of times HitMe Cache is accessed; Invalidations",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO6",
IntelPerformanceCounterDescription{event_code:
Tuple::One(34),
umask:
Tuple::One(64),
event_name:
"UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO6",
brief_description:
"CBox AD Credits Empty",
public_description:
Some("No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 6"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_H_DIRECT2CORE_TXN_OVERRIDE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(19),
umask:
Tuple::One(0),
event_name:
"UNC_H_DIRECT2CORE_TXN_OVERRIDE",
brief_description:
"Number of Reads that had Direct2Core Overridden",
public_description:
Some("Number of Reads where Direct2Core overridden"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_VMSE_MXB_WR_OCCUPANCY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(145),
umask:
Tuple::One(0),
event_name:
"UNC_M_VMSE_MXB_WR_OCCUPANCY",
brief_description:
"VMSE MXB write buffer occupancy",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK6.BANK5",
IntelPerformanceCounterDescription{event_code:
Tuple::One(190),
umask:
Tuple::One(5),
event_name:
"UNC_M_WR_CAS_RANK6.BANK5",
brief_description:
"WR_CAS Access to Rank 6; Bank 5",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_R3_RxR_CYCLES_NE.SNP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(16),
umask:
Tuple::One(2),
event_name:
"UNC_R3_RxR_CYCLES_NE.SNP",
brief_description:
"Ingress Cycles Not Empty; SNP",
public_description:
Some("Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK1.BANK2",
IntelPerformanceCounterDescription{event_code:
Tuple::One(177),
umask:
Tuple::One(2),
event_name:
"UNC_M_RD_CAS_RANK1.BANK2",
brief_description:
"RD_CAS Access to Rank 1; Bank 2",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK0.BANK11",
IntelPerformanceCounterDescription{event_code:
Tuple::One(176),
umask:
Tuple::One(11),
event_name:
"UNC_M_RD_CAS_RANK0.BANK11",
brief_description:
"RD_CAS Access to Rank 0; Bank 11",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK0.BANK10",
IntelPerformanceCounterDescription{event_code:
Tuple::One(176),
umask:
Tuple::One(10),
event_name:
"UNC_M_RD_CAS_RANK0.BANK10",
brief_description:
"RD_CAS Access to Rank 0; Bank 10",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_I_COHERENT_OPS.WBMTOI",
IntelPerformanceCounterDescription{event_code:
Tuple::One(19),
umask:
Tuple::One(64),
event_name:
"UNC_I_COHERENT_OPS.WBMTOI",
brief_description:
"Coherent Ops; WbMtoI",
public_description:
Some("Counts the number of coherency related operations servied by the IRP"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_H_SBO0_CREDIT_OCCUPANCY.BL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(106),
umask:
Tuple::One(2),
event_name:
"UNC_H_SBO0_CREDIT_OCCUPANCY.BL",
brief_description:
"SBo0 Credits Occupancy; For BL Ring",
public_description:
Some("Number of Sbo 0 credits in use in a given cycle, per ring."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_OSB_EDR.READS_LOCAL_I",
IntelPerformanceCounterDescription{event_code:
Tuple::One(84),
umask:
Tuple::One(2),
event_name:
"UNC_H_OSB_EDR.READS_LOCAL_I",
brief_description:
"OSB Early Data Return; Reads to Local I",
public_description:
Some("Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_FLITS_G2.NCS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(3),
umask:
Tuple::One(16),
event_name:
"UNC_Q_RxL_FLITS_G2.NCS",
brief_description:
"Flits Received - Group 2; Non-Coherent standard Rx Flits",
public_description:
Some("Counts the number of flits received from the QPI Link. This is one of three \'groups\' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each \'flit\' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four \'fits\', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI \'speed\' (for example, 8.0 GT/s), the \'transfers\' here refer to \'fits\'. Therefore, in L0, the system will transfer 1 \'flit\' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as \'data\' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual \'data\' and an additional 16 bits of other information. To calculate \'data\' bandwidth, one should therefore do: data flits * 8B / time.; Number of NCS (non-coherent standard) flits received over QPI. This includes extended headers."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_R2_STALL_NO_SBO_CREDIT.SBO1_BL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(44),
umask:
Tuple::One(8),
event_name:
"UNC_R2_STALL_NO_SBO_CREDIT.SBO1_BL",
brief_description:
"Stall on No Sbo Credits; For SBo1, BL Ring",
public_description:
Some("Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxR_AD_NDR_CREDIT_ACQUIRED.VN1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(40),
umask:
Tuple::One(2),
event_name:
"UNC_Q_TxR_AD_NDR_CREDIT_ACQUIRED.VN1",
brief_description:
"R3QPI Egress Credit Occupancy - AD NDR; for VN1",
public_description:
Some("Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for NDR messages on AD."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_R3_VNA_CREDITS_ACQUIRED.BL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(51),
umask:
Tuple::One(4),
event_name:
"UNC_R3_VNA_CREDITS_ACQUIRED.BL",
brief_description:
"VNA credit Acquisitions; HOM Message Class",
public_description:
Some("Number of QPI VNA Credit acquisitions. This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder. VNA credits are used by all message classes in order to communicate across QPI. If a packet is unable to acquire credits, it will then attempt to use credts from the VN0 pool. Note that a single packet may require multiple flit buffers (i.e. when data is being transfered). Therefore, this event will increment by the number of credits acquired in each cycle. Filtering based on message class is not provided. One can count the number of packets transfered in a given message class using an qfclk event.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_H_RING_AD_USED.CW_ODD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(62),
umask:
Tuple::One(2),
event_name:
"UNC_H_RING_AD_USED.CW_ODD",
brief_description:
"HA AD Ring in Use; Clockwise and Odd",
public_description:
Some("Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_I_SNOOP_RESP.SNPDATA",
IntelPerformanceCounterDescription{event_code:
Tuple::One(23),
umask:
Tuple::One(32),
event_name:
"UNC_I_SNOOP_RESP.SNPDATA",
brief_description:
"Snoop Responses; SnpData",
public_description:
None,
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_S_RING_AK_USED.DOWN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(28),
umask:
Tuple::One(12),
event_name:
"UNC_S_RING_AK_USED.DOWN",
brief_description:
"AK Ring In Use; Down",
public_description:
Some("Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the \'UP\' direction is on the clockwise ring and \'DN\' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_P_DEMOTIONS_CORE14",
IntelPerformanceCounterDescription{event_code:
Tuple::One(62),
umask:
Tuple::One(0),
event_name:
"UNC_P_DEMOTIONS_CORE14",
brief_description:
"Core C State Demotions",
public_description:
Some("Counts the number of times when a configurable cores had a C-state demotion"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(22),
umask:
Tuple::One(1),
event_name:
"UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN0",
brief_description:
"iMC RPQ Credits Empty - Special; Channel 0",
public_description:
Some("Counts the number of cycles when there are no \'special\' credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC\'s RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and \'special\' requests such as ISOCH reads. This count only tracks the \'special\' credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_IOT_BACKPRESSURE.HUB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(97),
umask:
Tuple::One(2),
event_name:
"UNC_H_IOT_BACKPRESSURE.HUB",
brief_description:
"IOT Backpressure",
public_description:
None,
counter:
Counter::Programmable(7),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_DIRECTORY_UPDATE.SET",
IntelPerformanceCounterDescription{event_code:
Tuple::One(13),
umask:
Tuple::One(1),
event_name:
"UNC_H_DIRECTORY_UPDATE.SET",
brief_description:
"Directory Updates; Directory Set",
public_description:
Some("Counts the number of directory updates that were required. These result in writes to the memory controller. This can be filtered by directory sets and directory clears.; Filter for directory sets. This occurs when a remote read transaction requests memory, bringing it to a remote cache."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_ADDR_OPC_MATCH.ADDR",
IntelPerformanceCounterDescription{event_code:
Tuple::One(32),
umask:
Tuple::One(1),
event_name:
"UNC_H_ADDR_OPC_MATCH.ADDR",
brief_description:
"QPI Address/Opcode Match; Address",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
Some("HA_AddrMatch0[31:6], HA_AddrMatch1[13:0]"),
extsel:
false,}),
("UNC_C_QLRU.AGE3",
IntelPerformanceCounterDescription{event_code:
Tuple::One(60),
umask:
Tuple::One(8),
event_name:
"UNC_C_QLRU.AGE3",
brief_description:
"LRU Queue; LRU Age 3",
public_description:
Some("How often age was set to 3"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_H_RING_BL_USED.CCW",
IntelPerformanceCounterDescription{event_code:
Tuple::One(64),
umask:
Tuple::One(12),
event_name:
"UNC_H_RING_BL_USED.CCW",
brief_description:
"HA BL Ring in Use; Counterclockwise",
public_description:
Some("Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_C_TOR_INSERTS.ALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(53),
umask:
Tuple::One(8),
event_name:
"UNC_C_TOR_INSERTS.ALL",
brief_description:
"TOR Inserts; All",
public_description:
Some("Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent \'filters\' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select \'MISS_OPC_MATCH\' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted into the TOR. This includes requests that reside in the TOR for a short time, such as LLC Hits that do not need to snoop cores or requests that get rejected and have to be retried through one of the ingress queues. The TOR is more commonly a bottleneck in skews with smaller core counts, where the ratio of RTIDs to TOR entries is larger. Note that there are reserved TOR entries for various request types, so it is possible that a given request type be blocked with an occupancy that is less than 20. Also note that generally requests will not be able to arbitrate into the TOR pipeline if there are no available TOR slots."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK5.BANKG3",
IntelPerformanceCounterDescription{event_code:
Tuple::One(181),
umask:
Tuple::One(20),
event_name:
"UNC_M_RD_CAS_RANK5.BANKG3",
brief_description:
"RD_CAS Access to Rank 5; Bank Group 3 (Banks 12-15)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_S_RxR_CRD_STARVED.BL_CRD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(20),
umask:
Tuple::One(4),
event_name:
"UNC_S_RxR_CRD_STARVED.BL_CRD",
brief_description:
"Injection Starvation; BL - Credits",
public_description:
Some("Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK5.BANK2",
IntelPerformanceCounterDescription{event_code:
Tuple::One(189),
umask:
Tuple::One(2),
event_name:
"UNC_M_WR_CAS_RANK5.BANK2",
brief_description:
"WR_CAS Access to Rank 5; Bank 2",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_H_HITME_HIT.ACKCNFLTWBI",
IntelPerformanceCounterDescription{event_code:
Tuple::One(113),
umask:
Tuple::One(4),
event_name:
"UNC_H_HITME_HIT.ACKCNFLTWBI",
brief_description:
"Counts Number of Hits in HitMe Cache; op is AckCnfltWbI",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_S_RxR_INSERTS.IV",
IntelPerformanceCounterDescription{event_code:
Tuple::One(19),
umask:
Tuple::One(32),
event_name:
"UNC_S_RxR_INSERTS.IV",
brief_description:
"Ingress Allocations; IV",
public_description:
Some("Number of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_AK_CYCLES_NE.SCHED1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(49),
umask:
Tuple::One(2),
event_name:
"UNC_H_TxR_AK_CYCLES_NE.SCHED1",
brief_description:
"AK Egress Not Empty; Scheduler 1",
public_description:
Some("AK Egress Not Empty; Filter for cycles not empty from scheduler bank 1"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK7.BANKG3",
IntelPerformanceCounterDescription{event_code:
Tuple::One(191),
umask:
Tuple::One(20),
event_name:
"UNC_M_WR_CAS_RANK7.BANKG3",
brief_description:
"WR_CAS Access to Rank 7; Bank Group 3 (Banks 12-15)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_R2_RxR_INSERTS.NCS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(17),
umask:
Tuple::One(32),
event_name:
"UNC_R2_RxR_INSERTS.NCS",
brief_description:
"Ingress Allocations; NCS",
public_description:
Some("Counts the number of allocations into the R2PCIe Ingress. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN3",
IntelPerformanceCounterDescription{event_code:
Tuple::One(25),
umask:
Tuple::One(8),
event_name:
"UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN3",
brief_description:
"HA iMC CHN0 WPQ Credits Empty - Special; Channel 3",
public_description:
Some("Counts the number of cycles when there are no \'special\' credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC\'s WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and \'special\' requests such as ISOCH writes. This count only tracks the \'special\' credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK",
IntelPerformanceCounterDescription{event_code:
Tuple::One(69),
umask:
Tuple::One(1),
event_name:
"UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK",
brief_description:
"Cycles PHOLD Assert to Ack; Assert to ACK",
public_description:
Some("PHOLD cycles. Filter from source CoreID."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("UBOX"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_CYCLES_NE_NDR.VN0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(20),
umask:
Tuple::One(1),
event_name:
"UNC_Q_RxL_CYCLES_NE_NDR.VN0",
brief_description:
"RxQ Cycles Not Empty - NDR; for VN0",
public_description:
Some("Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NDR flits only."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_Q_RxL_STALLS_VN0.BGF_NCS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(53),
umask:
Tuple::One(4),
event_name:
"UNC_Q_RxL_STALLS_VN0.BGF_NCS",
brief_description:
"Stalls Sending to R3QPI on VN0; BGF Stall - NDR",
public_description:
Some("Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the NDR message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_R3_RxR_CYCLES_NE_VN1.NDR",
IntelPerformanceCounterDescription{event_code:
Tuple::One(20),
umask:
Tuple::One(4),
event_name:
"UNC_R3_RxR_CYCLES_NE_VN1.NDR",
brief_description:
"VN1 Ingress Cycles Not Empty; NDR",
public_description:
Some("Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_C_RxR_ISMQ_RETRY.FULL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(51),
umask:
Tuple::One(2),
event_name:
"UNC_C_RxR_ISMQ_RETRY.FULL",
brief_description:
"ISMQ Retries; No Egress Credits",
public_description:
Some("Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Counts the number of times that a request from the ISMQ retried because of a TOR reject caused by a lack of Egress credits. The egress is the buffer that queues up for allocating onto the ring. If any of the Egress queues that a given request needs to make use of are full, the request will be retried."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_R3_VN0_CREDITS_USED.NDR",
IntelPerformanceCounterDescription{event_code:
Tuple::One(54),
umask:
Tuple::One(4),
event_name:
"UNC_R3_VN0_CREDITS_USED.NDR",
brief_description:
"VN0 Credit Used; NDR Message Class",
public_description:
Some("Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP)."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_OCCUPANCY_DRS.VN1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(21),
umask:
Tuple::One(2),
event_name:
"UNC_Q_RxL_OCCUPANCY_DRS.VN1",
brief_description:
"RxQ Occupancy - DRS; for VN1",
public_description:
Some("Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors DRS flits only."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_M_WR_CAS_RANK6.BANK15",
IntelPerformanceCounterDescription{event_code:
Tuple::One(190),
umask:
Tuple::One(15),
event_name:
"UNC_M_WR_CAS_RANK6.BANK15",
brief_description:
"WR_CAS Access to Rank 6; Bank 15",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_I_MISC1.DATA_THROTTLE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(21),
umask:
Tuple::One(128),
event_name:
"UNC_I_MISC1.DATA_THROTTLE",
brief_description:
"Misc Events - Set 1; Data Throttled",
public_description:
Some("IRP throttled switch data"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_H_HITME_HIT_PV_BITS_SET.READ_OR_INVITOE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(114),
umask:
Tuple::One(1),
event_name:
"UNC_H_HITME_HIT_PV_BITS_SET.READ_OR_INVITOE",
brief_description:
"Accumulates Number of PV bits set on HitMe Cache Hits; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_R3_SBO1_CREDIT_OCCUPANCY.AD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(43),
umask:
Tuple::One(1),
event_name:
"UNC_R3_SBO1_CREDIT_OCCUPANCY.AD",
brief_description:
"SBo1 Credits Occupancy; For AD Ring",
public_description:
Some("Number of Sbo 1 credits in use in a given cycle, per ring."),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_C_TOR_OCCUPANCY.MISS_OPCODE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(54),
umask:
Tuple::One(3),
event_name:
"UNC_C_TOR_OCCUPANCY.MISS_OPCODE",
brief_description:
"TOR Occupancy; Miss Opcode Match",
public_description:
Some("For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent \'filters\' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select \'MISS_OPC_MATCH\' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries for miss transactions that match an opcode. This generally means that the request was sent to memory or MMIO."),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
Some("CBoFilter1[28:20]"),
extsel:
false,}),
("UNC_M_VMSE_WR_PUSH.RMM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(144),
umask:
Tuple::One(2),
event_name:
"UNC_M_VMSE_WR_PUSH.RMM",
brief_description:
"VMSE WR PUSH issued; VMSE write PUSH issued in RMM",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_H_OSB.REMOTE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(83),
umask:
Tuple::One(8),
event_name:
"UNC_H_OSB.REMOTE",
brief_description:
"OSB Snoop Broadcast; Remote",
public_description:
Some("Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_C_RxR_IPQ_RETRY.ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(49),
umask:
Tuple::One(1),
event_name:
"UNC_C_RxR_IPQ_RETRY.ANY",
brief_description:
"Probe Queue Retries; Any Reject",
public_description:
Some("Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.; Counts the number of times that a request form the IPQ was retried because of a TOR reject. TOR rejects from the IPQ can be caused by the Egress being full or Address Conflicts."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_M_PRE_COUNT.BYP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(2),
umask:
Tuple::One(16),
event_name:
"UNC_M_PRE_COUNT.BYP",
brief_description:
"DRAM Precharge commands.; Precharge due to bypass",
public_description:
Some("Counts the number of DRAM Precharge commands sent on this channel."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxR_BL_NCS_CREDIT_OCCUPANCY.VN0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(33),
umask:
Tuple::One(1),
event_name:
"UNC_Q_TxR_BL_NCS_CREDIT_OCCUPANCY.VN0",
brief_description:
"R3QPI Egress Credit Occupancy - BL NCS; for VN0",
public_description:
Some("Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. NCS message class to BL Egress."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_H_BT_CYCLES_NE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(66),
umask:
Tuple::One(0),
event_name:
"UNC_H_BT_CYCLES_NE",
brief_description:
"BT Cycles Not Empty",
public_description:
Some("Cycles the Backup Tracker (BT) is not empty. The BT is the actual HOM tracker in IVT."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_SBO0_CREDIT_OCCUPANCY.AD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(106),
umask:
Tuple::One(1),
event_name:
"UNC_H_SBO0_CREDIT_OCCUPANCY.AD",
brief_description:
"SBo0 Credits Occupancy; For AD Ring",
public_description:
Some("Number of Sbo 0 credits in use in a given cycle, per ring."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK4.BANK10",
IntelPerformanceCounterDescription{event_code:
Tuple::One(180),
umask:
Tuple::One(10),
event_name:
"UNC_M_RD_CAS_RANK4.BANK10",
brief_description:
"RD_CAS Access to Rank 4; Bank 10",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK1.BANK13",
IntelPerformanceCounterDescription{event_code:
Tuple::One(177),
umask:
Tuple::One(13),
event_name:
"UNC_M_RD_CAS_RANK1.BANK13",
brief_description:
"RD_CAS Access to Rank 1; Bank 13",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_P_UFS_TRANSITIONS_RING_GV",
IntelPerformanceCounterDescription{event_code:
Tuple::One(121),
umask:
Tuple::One(0),
event_name:
"UNC_P_UFS_TRANSITIONS_RING_GV",
brief_description:
"tbd",
public_description:
Some("Ring GV with same final and initial frequency"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_H_TAD_REQUESTS_G0.REGION7",
IntelPerformanceCounterDescription{event_code:
Tuple::One(27),
umask:
Tuple::One(128),
event_name:
"UNC_H_TAD_REQUESTS_G0.REGION7",
brief_description:
"HA Requests to a TAD Region - Group 0; TAD Region 7",
public_description:
Some("Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for \'Monroe\' systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 7"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_P_VR_HOT_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(66),
umask:
Tuple::One(0),
event_name:
"UNC_P_VR_HOT_CYCLES",
brief_description:
"VR Hot",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_CYCLES_NE_NCS.VN0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(17),
umask:
Tuple::One(1),
event_name:
"UNC_Q_RxL_CYCLES_NE_NCS.VN0",
brief_description:
"RxQ Cycles Not Empty - NCS; for VN0",
public_description:
Some("Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NCS flits only."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_H_HITME_HIT.INVALS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(113),
umask:
Tuple::One(38),
event_name:
"UNC_H_HITME_HIT.INVALS",
brief_description:
"Counts Number of Hits in HitMe Cache; Invalidations",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_C_LLC_LOOKUP.NID",
IntelPerformanceCounterDescription{event_code:
Tuple::One(52),
umask:
Tuple::One(65),
event_name:
"UNC_C_LLC_LOOKUP.NID",
brief_description:
"Cache Lookups; Lookups that Match NID",
public_description:
Some("Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Qualify one of the other subevents by the Target NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid. In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
Some("CBoFilter0[23:17]"),
extsel:
false,}),
("UNC_Q_RxL_INSERTS_SNP.VN0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(13),
umask:
Tuple::One(1),
event_name:
"UNC_Q_RxL_INSERTS_SNP.VN0",
brief_description:
"Rx Flit Buffer Allocations - SNP; for VN0",
public_description:
Some("Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only SNP flits."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_M_RD_CAS_RANK6.BANK8",
IntelPerformanceCounterDescription{event_code:
Tuple::One(182),
umask:
Tuple::One(8),
event_name:
"UNC_M_RD_CAS_RANK6.BANK8",
brief_description:
"RD_CAS Access to Rank 6; Bank 8",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_R2_SBO0_CREDIT_OCCUPANCY.AD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(42),
umask:
Tuple::One(1),
event_name:
"UNC_R2_SBO0_CREDIT_OCCUPANCY.AD",
brief_description:
"SBo0 Credits Occupancy; For AD Ring",
public_description:
Some("Number of Sbo 0 credits in use in a given cycle, per ring."),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_R3_VN0_CREDITS_REJECT.NDR",
IntelPerformanceCounterDescription{event_code:
Tuple::One(55),
umask:
Tuple::One(4),
event_name:
"UNC_R3_VN0_CREDITS_REJECT.NDR",
brief_description:
"VN0 Credit Acquisition Failed on DRS; NDR Message Class",
public_description:
Some("Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP)."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_H_RING_AD_USED.CCW",
IntelPerformanceCounterDescription{event_code:
Tuple::One(62),
umask:
Tuple::One(12),
event_name:
"UNC_H_RING_AD_USED.CCW",
brief_description:
"HA AD Ring in Use; Counterclockwise",
public_description:
Some("Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK4.BANK9",
IntelPerformanceCounterDescription{event_code:
Tuple::One(180),
umask:
Tuple::One(9),
event_name:
"UNC_M_RD_CAS_RANK4.BANK9",
brief_description:
"RD_CAS Access to Rank 4; Bank 9",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_H_DIRECTORY_LOOKUP.SNP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(12),
umask:
Tuple::One(1),
event_name:
"UNC_H_DIRECTORY_LOOKUP.SNP",
brief_description:
"Directory Lookups; Snoop Needed",
public_description:
Some("Counts the number of transactions that looked up the directory. Can be filtered by requests that had to snoop and those that did not have to.; Filters for transactions that had to send one or more snoops because the directory bit was set."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI2",
IntelPerformanceCounterDescription{event_code:
Tuple::One(34),
umask:
Tuple::One(32),
event_name:
"UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI2",
brief_description:
"Cycles without QPI Ingress Credits; BL to QPI Link 1",
public_description:
Some("Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent. This can be filtered by the different credit pools and the different links."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_TAD_REQUESTS_G0.REGION0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(27),
umask:
Tuple::One(1),
event_name:
"UNC_H_TAD_REQUESTS_G0.REGION0",
brief_description:
"HA Requests to a TAD Region - Group 0; TAD Region 0",
public_description:
Some("Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for \'Monroe\' systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 0"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_R3_RING_AK_USED.CW_ODD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(8),
umask:
Tuple::One(2),
event_name:
"UNC_R3_RING_AK_USED.CW_ODD",
brief_description:
"R3 AK Ring in Use; Clockwise and Odd",
public_description:
Some("Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity."),
counter:
Counter::Programmable(7),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_P_CLOCKTICKS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(0),
umask:
Tuple::One(0),
event_name:
"UNC_P_CLOCKTICKS",
brief_description:
"pclk Cycles",
public_description:
Some("The PCU runs off a fixed 800 MHz clock. This event counts the number of pclk cycles measured while the counter was enabled. The pclk, like the Memory Controller\'s dclk, counts at a constant rate making it a good measure of actual wall time."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK6.BANKG2",
IntelPerformanceCounterDescription{event_code:
Tuple::One(190),
umask:
Tuple::One(19),
event_name:
"UNC_M_WR_CAS_RANK6.BANKG2",
brief_description:
"WR_CAS Access to Rank 6; Bank Group 2 (Banks 8-11)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_NDR",
IntelPerformanceCounterDescription{event_code:
Tuple::One(32),
umask:
Tuple::One(8),
event_name:
"UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_NDR",
brief_description:
"QPI0 AD Credits Empty",
public_description:
Some("No credits available to send to QPI0 on the AD Ring; VN0 NDR Messages"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_S_TxR_INSERTS.AD_CRD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(2),
umask:
Tuple::One(1),
event_name:
"UNC_S_TxR_INSERTS.AD_CRD",
brief_description:
"Egress Allocations; AD - Credits",
public_description:
Some("Number of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_M_POWER_THROTTLE_CYCLES.RANK3",
IntelPerformanceCounterDescription{event_code:
Tuple::One(65),
umask:
Tuple::One(8),
event_name:
"UNC_M_POWER_THROTTLE_CYCLES.RANK3",
brief_description:
"Throttle Cycles for Rank 0; DIMM ID",
public_description:
Some("Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_FLITS_G1.HOM_NONREQ",
IntelPerformanceCounterDescription{event_code:
Tuple::One(2),
umask:
Tuple::One(4),
event_name:
"UNC_Q_RxL_FLITS_G1.HOM_NONREQ",
brief_description:
"Flits Received - Group 1; HOM Non-Request Flits",
public_description:
Some("Counts the number of flits received from the QPI Link. This is one of three \'groups\' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each \'flit\' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four \'fits\', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI \'speed\' (for example, 8.0 GT/s), the \'transfers\' here refer to \'fits\'. Therefore, in L0, the system will transfer 1 \'flit\' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as \'data\' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual \'data\' and an additional 16 bits of other information. To calculate \'data\' bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of non-request flits received over QPI on the home channel. These are most commonly snoop responses, and this event can be used as a proxy for that."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_Q_RxL_INSERTS_DRS.VN0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(9),
umask:
Tuple::One(1),
event_name:
"UNC_Q_RxL_INSERTS_DRS.VN0",
brief_description:
"Rx Flit Buffer Allocations - DRS; for VN0",
public_description:
Some("Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only DRS flits."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_I_RxR_BL_DRS_INSERTS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(1),
umask:
Tuple::One(0),
event_name:
"UNC_I_RxR_BL_DRS_INSERTS",
brief_description:
"BL Ingress Occupancy - DRS",
public_description:
Some("Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_R3_RxR_CYCLES_NE.HOM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(16),
umask:
Tuple::One(1),
event_name:
"UNC_R3_RxR_CYCLES_NE.HOM",
brief_description:
"Ingress Cycles Not Empty; HOM",
public_description:
Some("Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_I_TRANSACTIONS.WRITES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(22),
umask:
Tuple::One(2),
event_name:
"UNC_I_TRANSACTIONS.WRITES",
brief_description:
"Inbound Transaction Count; Writes",
public_description:
Some("Counts the number of \'Inbound\' transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Trackes only write requests. Each write request should have a prefetch, so there is no need to explicitly track these requests. For writes that are tickled and have to retry, the counter will be incremented for each retry."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_C_RxR_OCCUPANCY.IRQ_REJ",
IntelPerformanceCounterDescription{event_code:
Tuple::One(17),
umask:
Tuple::One(2),
event_name:
"UNC_C_RxR_OCCUPANCY.IRQ_REJ",
brief_description:
"Ingress Occupancy; IRQ Rejected",
public_description:
Some("Counts number of entries in the specified Ingress queue in each cycle."),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_S_RxR_BUSY_STARVED.BL_BNC",
IntelPerformanceCounterDescription{event_code:
Tuple::One(21),
umask:
Tuple::One(8),
event_name:
"UNC_S_RxR_BUSY_STARVED.BL_BNC",
brief_description:
"Injection Starvation; BL - Bounces",
public_description:
Some("Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress because a message (credited/bounceable) is being sent."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK1.ALLBANKS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(177),
umask:
Tuple::One(16),
event_name:
"UNC_M_RD_CAS_RANK1.ALLBANKS",
brief_description:
"RD_CAS Access to Rank 1; All Banks",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK1.BANK0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(177),
umask:
Tuple::One(0),
event_name:
"UNC_M_RD_CAS_RANK1.BANK0",
brief_description:
"RD_CAS Access to Rank 1; Bank 0",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK6.BANKG0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(182),
umask:
Tuple::One(17),
event_name:
"UNC_M_RD_CAS_RANK6.BANKG0",
brief_description:
"RD_CAS Access to Rank 6; Bank Group 0 (Banks 0-3)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK5.BANK14",
IntelPerformanceCounterDescription{event_code:
Tuple::One(189),
umask:
Tuple::One(14),
event_name:
"UNC_M_WR_CAS_RANK5.BANK14",
brief_description:
"WR_CAS Access to Rank 5; Bank 14",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_POWER_CKE_CYCLES.RANK7",
IntelPerformanceCounterDescription{event_code:
Tuple::One(131),
umask:
Tuple::One(128),
event_name:
"UNC_M_POWER_CKE_CYCLES.RANK7",
brief_description:
"CKE_ON_CYCLES by Rank; DIMM ID",
public_description:
Some("Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary)."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_S_TxR_STARVED.AK",
IntelPerformanceCounterDescription{event_code:
Tuple::One(3),
umask:
Tuple::One(2),
event_name:
"UNC_S_TxR_STARVED.AK",
brief_description:
"Injection Starvation; Onto AK Ring",
public_description:
Some("Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxL_FLITS_G2.NCB_DATA",
IntelPerformanceCounterDescription{event_code:
Tuple::One(1),
umask:
Tuple::One(4),
event_name:
"UNC_Q_TxL_FLITS_G2.NCB_DATA",
brief_description:
"Flits Transferred - Group 2; Non-Coherent data Tx Flits",
public_description:
Some("Counts the number of flits trasmitted across the QPI Link. This is one of three \'groups\' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each \'flit\' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four \'fits\', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI \'speed\' (for example, 8.0 GT/s), the \'transfers\' here refer to \'fits\'. Therefore, in L0, the system will transfer 1 \'flit\' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as \'data\' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual \'data\' and an additional 16 bits of other information. To calculate \'data\' bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass data flits. These flits are generally used to transmit non-coherent data across QPI. This does not include a count of the DRS (coherent) data flits. This only counts the data flits, not te NCB headers."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_R3_RxR_OCCUPANCY_VN1.HOM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(19),
umask:
Tuple::One(1),
event_name:
"UNC_R3_RxR_OCCUPANCY_VN1.HOM",
brief_description:
"VN1 Ingress Occupancy Accumulator; HOM",
public_description:
Some("Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.; HOM Ingress Queue"),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_CREDITS_CONSUMED_VN0.NDR",
IntelPerformanceCounterDescription{event_code:
Tuple::One(30),
umask:
Tuple::One(32),
event_name:
"UNC_Q_RxL_CREDITS_CONSUMED_VN0.NDR",
brief_description:
"VN0 Credit Consumed; NDR",
public_description:
Some("Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the NDR message class."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_M_WR_CAS_RANK4.BANK15",
IntelPerformanceCounterDescription{event_code:
Tuple::One(188),
umask:
Tuple::One(15),
event_name:
"UNC_M_WR_CAS_RANK4.BANK15",
brief_description:
"WR_CAS Access to Rank 4; Bank 15",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(24),
umask:
Tuple::One(1),
event_name:
"UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN0",
brief_description:
"HA iMC CHN0 WPQ Credits Empty - Regular; Channel 0",
public_description:
Some("Counts the number of cycles when there are no \'regular\' credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC\'s WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and \'special\' requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_R2_IIO_CREDITS_ACQUIRED.DRS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(51),
umask:
Tuple::One(8),
event_name:
"UNC_R2_IIO_CREDITS_ACQUIRED.DRS",
brief_description:
"R2PCIe IIO Credit Acquired; DRS",
public_description:
Some("Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the DRS message class."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_C_TxR_INSERTS.BL_CACHE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(2),
umask:
Tuple::One(4),
event_name:
"UNC_C_TxR_INSERTS.BL_CACHE",
brief_description:
"Egress Allocations; BL - Cacheno",
public_description:
Some("Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the BL ring. This is commonly used to send data from the cache to various destinations."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_S_RING_SINK_STARVED.AK_CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(6),
umask:
Tuple::One(2),
event_name:
"UNC_S_RING_SINK_STARVED.AK_CORE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_H_HITME_LOOKUP.RSPFWDI_LOCAL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(112),
umask:
Tuple::One(32),
event_name:
"UNC_H_HITME_LOOKUP.RSPFWDI_LOCAL",
brief_description:
"Counts Number of times HitMe Cache is accessed; op is RspIFwd or RspIFwdWb for a local request",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_S_TxR_INSERTS.BL_CRD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(2),
umask:
Tuple::One(4),
event_name:
"UNC_S_TxR_INSERTS.BL_CRD",
brief_description:
"Egress Allocations; BL - Credits",
public_description:
Some("Number of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK1.BANK8",
IntelPerformanceCounterDescription{event_code:
Tuple::One(185),
umask:
Tuple::One(8),
event_name:
"UNC_M_WR_CAS_RANK1.BANK8",
brief_description:
"WR_CAS Access to Rank 1; Bank 8",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK4.BANK15",
IntelPerformanceCounterDescription{event_code:
Tuple::One(180),
umask:
Tuple::One(15),
event_name:
"UNC_M_RD_CAS_RANK4.BANK15",
brief_description:
"RD_CAS Access to Rank 4; Bank 15",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_P_DEMOTIONS_CORE8",
IntelPerformanceCounterDescription{event_code:
Tuple::One(56),
umask:
Tuple::One(0),
event_name:
"UNC_P_DEMOTIONS_CORE8",
brief_description:
"Core C State Demotions",
public_description:
Some("Counts the number of times when a configurable cores had a C-state demotion"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_C_RING_AD_USED.UP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(27),
umask:
Tuple::One(3),
event_name:
"UNC_C_RING_AD_USED.UP",
brief_description:
"AD Ring In Use; Up",
public_description:
Some("Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the \'UP\' direction is on the clockwise ring and \'DN\' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK7.BANK1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(1),
event_name:
"UNC_M_RD_CAS_RANK7.BANK1",
brief_description:
"RD_CAS Access to Rank 7; Bank 1",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_BYPASSED",
IntelPerformanceCounterDescription{event_code:
Tuple::One(9),
umask:
Tuple::One(0),
event_name:
"UNC_Q_RxL_BYPASSED",
brief_description:
"Rx Flit Buffer Bypassed",
public_description:
Some("Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of flits transfered, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_H_HITME_LOOKUP.READ_OR_INVITOE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(112),
umask:
Tuple::One(1),
event_name:
"UNC_H_HITME_LOOKUP.READ_OR_INVITOE",
brief_description:
"Counts Number of times HitMe Cache is accessed; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_OSB_EDR.READS_LOCAL_S",
IntelPerformanceCounterDescription{event_code:
Tuple::One(84),
umask:
Tuple::One(8),
event_name:
"UNC_H_OSB_EDR.READS_LOCAL_S",
brief_description:
"OSB Early Data Return; Reads to Local S",
public_description:
Some("Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_SNOOP_RESP.RSPIFWD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(33),
umask:
Tuple::One(4),
event_name:
"UNC_H_SNOOP_RESP.RSPIFWD",
brief_description:
"Snoop Responses Received; RspIFwd",
public_description:
Some("Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoop responses of RspIFwd. This is returned when a remote caching agent forwards data and the requesting agent is able to acquire the data in E or M states. This is commonly returned with RFO transactions. It can be either a HitM or a HitFE."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_C_RING_AD_USED.UP_ODD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(27),
umask:
Tuple::One(2),
event_name:
"UNC_C_RING_AD_USED.UP_ODD",
brief_description:
"AD Ring In Use; Up and Odd",
public_description:
Some("Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the \'UP\' direction is on the clockwise ring and \'DN\' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_M_MAJOR_MODES.READ",
IntelPerformanceCounterDescription{event_code:
Tuple::One(7),
umask:
Tuple::One(1),
event_name:
"UNC_M_MAJOR_MODES.READ",
brief_description:
"Cycles in a Major Mode; Read Major Mode",
public_description:
Some("Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; Read Major Mode is the default mode for the iMC, as reads are generally more critical to forward progress than writes."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_DRAM_PRE_ALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(6),
umask:
Tuple::One(0),
event_name:
"UNC_M_DRAM_PRE_ALL",
brief_description:
"DRAM Precharge All Commands",
public_description:
Some("Counts the number of times that the precharge all command was sent."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_C_RxR_EXT_STARVED.PRQ",
IntelPerformanceCounterDescription{event_code:
Tuple::One(18),
umask:
Tuple::One(4),
event_name:
"UNC_C_RxR_EXT_STARVED.PRQ",
brief_description:
"Ingress Arbiter Blocking Cycles; PRQ",
public_description:
Some("Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_S_TxR_STARVED.IV",
IntelPerformanceCounterDescription{event_code:
Tuple::One(3),
umask:
Tuple::One(8),
event_name:
"UNC_S_TxR_STARVED.IV",
brief_description:
"Injection Starvation; Onto IV Ring",
public_description:
Some("Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_S_RING_AK_USED.UP_EVEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(28),
umask:
Tuple::One(1),
event_name:
"UNC_S_RING_AK_USED.UP_EVEN",
brief_description:
"AK Ring In Use; Up and Even",
public_description:
Some("Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the \'UP\' direction is on the clockwise ring and \'DN\' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_R2_IIO_CREDITS_ACQUIRED.NCB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(51),
umask:
Tuple::One(16),
event_name:
"UNC_R2_IIO_CREDITS_ACQUIRED.NCB",
brief_description:
"R2PCIe IIO Credit Acquired; NCB",
public_description:
Some("Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCB message class."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK1.BANK5",
IntelPerformanceCounterDescription{event_code:
Tuple::One(185),
umask:
Tuple::One(5),
event_name:
"UNC_M_WR_CAS_RANK1.BANK5",
brief_description:
"WR_CAS Access to Rank 1; Bank 5",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK7.BANK12",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(12),
event_name:
"UNC_M_RD_CAS_RANK7.BANK12",
brief_description:
"RD_CAS Access to Rank 7; Bank 12",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK6.BANK10",
IntelPerformanceCounterDescription{event_code:
Tuple::One(190),
umask:
Tuple::One(10),
event_name:
"UNC_M_WR_CAS_RANK6.BANK10",
brief_description:
"WR_CAS Access to Rank 6; Bank 10",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_H_HITME_HIT.RSPFWDI_REMOTE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(113),
umask:
Tuple::One(16),
event_name:
"UNC_H_HITME_HIT.RSPFWDI_REMOTE",
brief_description:
"Counts Number of Hits in HitMe Cache; op is RspIFwd or RspIFwdWb for a remote request",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_C_TOR_OCCUPANCY.MISS_REMOTE_OPCODE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(54),
umask:
Tuple::One(131),
event_name:
"UNC_C_TOR_OCCUPANCY.MISS_REMOTE_OPCODE",
brief_description:
"TOR Occupancy; Misses to Remote Memory - Opcode Matched",
public_description:
Some("For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent \'filters\' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select \'MISS_OPC_MATCH\' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss transactions, satisifed by an opcode, in the TOR that are satisifed by remote caches or remote memory."),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
Some("CBoFilter1[28:20]"),
extsel:
false,}),
("UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO8",
IntelPerformanceCounterDescription{event_code:
Tuple::One(31),
umask:
Tuple::One(1),
event_name:
"UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO8",
brief_description:
"CBox AD Credits Empty",
public_description:
Some("No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 8"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_M_POWER_CKE_CYCLES.RANK5",
IntelPerformanceCounterDescription{event_code:
Tuple::One(131),
umask:
Tuple::One(32),
event_name:
"UNC_M_POWER_CKE_CYCLES.RANK5",
brief_description:
"CKE_ON_CYCLES by Rank; DIMM ID",
public_description:
Some("Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary)."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_AK_CYCLES_FULL.SCHED0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(50),
umask:
Tuple::One(1),
event_name:
"UNC_H_TxR_AK_CYCLES_FULL.SCHED0",
brief_description:
"AK Egress Full; Scheduler 0",
public_description:
Some("AK Egress Full; Filter for cycles full from scheduler bank 0"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_SNP_RESP_RECV_LOCAL.RSPS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(96),
umask:
Tuple::One(2),
event_name:
"UNC_H_SNP_RESP_RECV_LOCAL.RSPS",
brief_description:
"Snoop Responses Received Local; RspS",
public_description:
Some("Number of snoop responses received for a Local request; Filters for snoop responses of RspS. RspS is returned when a remote cache has data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E state. No data is sent with S RspS."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_AD_CYCLES_NE.ALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(41),
umask:
Tuple::One(3),
event_name:
"UNC_H_TxR_AD_CYCLES_NE.ALL",
brief_description:
"AD Egress Not Empty; All",
public_description:
Some("AD Egress Not Empty; Cycles full from both schedulers"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_STALLS_VN1.BGF_NDR",
IntelPerformanceCounterDescription{event_code:
Tuple::One(58),
umask:
Tuple::One(32),
event_name:
"UNC_Q_RxL_STALLS_VN1.BGF_NDR",
brief_description:
"Stalls Sending to R3QPI on VN1; BGF Stall - NCS",
public_description:
Some("Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the NCS message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_R2_RING_BL_USED.CCW_EVEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(9),
umask:
Tuple::One(4),
event_name:
"UNC_R2_RING_BL_USED.CCW_EVEN",
brief_description:
"R2 BL Ring in Use; Counterclockwise and Even",
public_description:
Some("Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_C_RxR_ISMQ_RETRY2.AD_SBO",
IntelPerformanceCounterDescription{event_code:
Tuple::One(42),
umask:
Tuple::One(1),
event_name:
"UNC_C_RxR_ISMQ_RETRY2.AD_SBO",
brief_description:
"ISMQ Request Queue Rejects; No AD Sbo Credits",
public_description:
Some("Counts the number of times that a request from the ISMQ was retried because of it lacked credits to send an AD packet to the Sbo."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_R2_TxR_NACK_CW.UP_AD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(38),
umask:
Tuple::One(8),
event_name:
"UNC_R2_TxR_NACK_CW.UP_AD",
brief_description:
"Egress CCW NACK; AK CCW",
public_description:
Some("BL CounterClockwise Egress Queue"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_C_TOR_OCCUPANCY.NID_WB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(54),
umask:
Tuple::One(80),
event_name:
"UNC_C_TOR_OCCUPANCY.NID_WB",
brief_description:
"TOR Occupancy; NID Matched Writebacks",
public_description:
Some("For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent \'filters\' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select \'MISS_OPC_MATCH\' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); NID matched write transactions int the TOR."),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
Some("CBoFilter1[15:0]"),
extsel:
false,}),
("UNC_R3_VN0_CREDITS_USED.DRS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(54),
umask:
Tuple::One(8),
event_name:
"UNC_R3_VN0_CREDITS_USED.DRS",
brief_description:
"VN0 Credit Used; DRS Message Class",
public_description:
Some("Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_C_TxR_INSERTS.AD_CACHE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(2),
umask:
Tuple::One(1),
event_name:
"UNC_C_TxR_INSERTS.AD_CACHE",
brief_description:
"Egress Allocations; AD - Cachebo",
public_description:
Some("Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_R3_HA_R2_BL_CREDITS_EMPTY.R2_NCB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(45),
umask:
Tuple::One(4),
event_name:
"UNC_R3_HA_R2_BL_CREDITS_EMPTY.R2_NCB",
brief_description:
"HA/R2 AD Credits Empty",
public_description:
Some("No credits available to send to either HA or R2 on the BL Ring; R2 NCB Messages"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_R3_RING_AD_USED.CCW_EVEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(7),
umask:
Tuple::One(4),
event_name:
"UNC_R3_RING_AD_USED.CCW_EVEN",
brief_description:
"R3 AD Ring in Use; Counterclockwise and Even",
public_description:
Some("Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity."),
counter:
Counter::Programmable(7),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_P_CORE6_TRANSITION_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(102),
umask:
Tuple::One(0),
event_name:
"UNC_P_CORE6_TRANSITION_CYCLES",
brief_description:
"Core C State Transition Cycles",
public_description:
Some("Number of cycles spent performing core C state transitions. There is one event per core."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK5.BANK8",
IntelPerformanceCounterDescription{event_code:
Tuple::One(181),
umask:
Tuple::One(8),
event_name:
"UNC_M_RD_CAS_RANK5.BANK8",
brief_description:
"RD_CAS Access to Rank 5; Bank 8",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK1.BANK11",
IntelPerformanceCounterDescription{event_code:
Tuple::One(185),
umask:
Tuple::One(11),
event_name:
"UNC_M_WR_CAS_RANK1.BANK11",
brief_description:
"WR_CAS Access to Rank 1; Bank 11",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_BL.DRS_CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(16),
umask:
Tuple::One(2),
event_name:
"UNC_H_TxR_BL.DRS_CORE",
brief_description:
"Outbound DRS Ring Transactions to Cache; Data to Core",
public_description:
Some("Counts the number of DRS messages sent out on the BL ring. This can be filtered by the destination.; Filter for data being sent directly to the requesting core."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK6.BANK14",
IntelPerformanceCounterDescription{event_code:
Tuple::One(182),
umask:
Tuple::One(14),
event_name:
"UNC_M_RD_CAS_RANK6.BANK14",
brief_description:
"RD_CAS Access to Rank 6; Bank 14",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK0.BANK3",
IntelPerformanceCounterDescription{event_code:
Tuple::One(184),
umask:
Tuple::One(3),
event_name:
"UNC_M_WR_CAS_RANK0.BANK3",
brief_description:
"WR_CAS Access to Rank 0; Bank 3",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_H_CLOCKTICKS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(0),
umask:
Tuple::One(0),
event_name:
"UNC_H_CLOCKTICKS",
brief_description:
"uclks",
public_description:
Some("Counts the number of uclks in the HA. This will be slightly different than the count in the Ubox because of enable/freeze delays. The HA is on the other side of the die from the fixed Ubox uclk counter, so the drift could be somewhat larger than in units that are closer like the QPI Agent."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_TAD_REQUESTS_G1.REGION8",
IntelPerformanceCounterDescription{event_code:
Tuple::One(28),
umask:
Tuple::One(1),
event_name:
"UNC_H_TAD_REQUESTS_G1.REGION8",
brief_description:
"HA Requests to a TAD Region - Group 1; TAD Region 8",
public_description:
Some("Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 8 to 10. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for \'Monroe\' systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 8"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_TAD_REQUESTS_G0.REGION6",
IntelPerformanceCounterDescription{event_code:
Tuple::One(27),
umask:
Tuple::One(64),
event_name:
"UNC_H_TAD_REQUESTS_G0.REGION6",
brief_description:
"HA Requests to a TAD Region - Group 0; TAD Region 6",
public_description:
Some("Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for \'Monroe\' systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 6"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO13",
IntelPerformanceCounterDescription{event_code:
Tuple::One(31),
umask:
Tuple::One(32),
event_name:
"UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO13",
brief_description:
"CBox AD Credits Empty",
public_description:
Some("No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 13"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK6.ALLBANKS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(190),
umask:
Tuple::One(16),
event_name:
"UNC_M_WR_CAS_RANK6.ALLBANKS",
brief_description:
"WR_CAS Access to Rank 6; All Banks",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_C_RxR_IRQ_RETRY.FULL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(50),
umask:
Tuple::One(2),
event_name:
"UNC_C_RxR_IRQ_RETRY.FULL",
brief_description:
"Ingress Request Queue Rejects; No Egress Credits",
public_description:
Some("Counts the number of times that a request from the IRQ was retried because it failed to acquire an entry in the Egress. The egress is the buffer that queues up for allocating onto the ring. IRQ requests can make use of all four rings and all four Egresses. If any of the queues that a given request needs to make use of are full, the request will be retried."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(114),
umask:
Tuple::One(64),
event_name:
"UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDS",
brief_description:
"Accumulates Number of PV bits set on HitMe Cache Hits; op is RsSFwd or RspSFwdWb",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK1.BANK9",
IntelPerformanceCounterDescription{event_code:
Tuple::One(185),
umask:
Tuple::One(9),
event_name:
"UNC_M_WR_CAS_RANK1.BANK9",
brief_description:
"WR_CAS Access to Rank 1; Bank 9",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_MAJOR_MODES.WRITE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(7),
umask:
Tuple::One(2),
event_name:
"UNC_M_MAJOR_MODES.WRITE",
brief_description:
"Cycles in a Major Mode; Write Major Mode",
public_description:
Some("Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This mode is triggered when the WPQ hits high occupancy and causes writes to be higher priority than reads. This can cause blips in the available read bandwidth in the system and temporarily increase read latencies in order to achieve better bus utilizations and higher bandwidth."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK0.BANK12",
IntelPerformanceCounterDescription{event_code:
Tuple::One(176),
umask:
Tuple::One(12),
event_name:
"UNC_M_RD_CAS_RANK0.BANK12",
brief_description:
"RD_CAS Access to Rank 0; Bank 12",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_P_DEMOTIONS_CORE12",
IntelPerformanceCounterDescription{event_code:
Tuple::One(60),
umask:
Tuple::One(0),
event_name:
"UNC_P_DEMOTIONS_CORE12",
brief_description:
"Core C State Demotions",
public_description:
Some("Counts the number of times when a configurable cores had a C-state demotion"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_C_RxR_ISMQ_RETRY.ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(51),
umask:
Tuple::One(1),
event_name:
"UNC_C_RxR_ISMQ_RETRY.ANY",
brief_description:
"ISMQ Retries; Any Reject",
public_description:
Some("Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Counts the total number of times that a request from the ISMQ retried because of a TOR reject. ISMQ requests generally will not need to retry (or at least ISMQ retries are less common than IRQ retries). ISMQ requests will retry if they are not able to acquire a needed Egress credit to get onto the ring, or for cache evictions that need to acquire an RTID. Most ISMQ requests already have an RTID, so eviction retries will be less common here."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO12",
IntelPerformanceCounterDescription{event_code:
Tuple::One(31),
umask:
Tuple::One(16),
event_name:
"UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO12",
brief_description:
"CBox AD Credits Empty",
public_description:
Some("No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 12"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK0.BANK14",
IntelPerformanceCounterDescription{event_code:
Tuple::One(184),
umask:
Tuple::One(14),
event_name:
"UNC_M_WR_CAS_RANK0.BANK14",
brief_description:
"WR_CAS Access to Rank 0; Bank 14",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK4.BANK13",
IntelPerformanceCounterDescription{event_code:
Tuple::One(180),
umask:
Tuple::One(13),
event_name:
"UNC_M_RD_CAS_RANK4.BANK13",
brief_description:
"RD_CAS Access to Rank 4; Bank 13",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK0.BANKG3",
IntelPerformanceCounterDescription{event_code:
Tuple::One(176),
umask:
Tuple::One(20),
event_name:
"UNC_M_RD_CAS_RANK0.BANKG3",
brief_description:
"RD_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_I_SNOOP_RESP.SNPCODE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(23),
umask:
Tuple::One(16),
event_name:
"UNC_I_SNOOP_RESP.SNPCODE",
brief_description:
"Snoop Responses; SnpCode",
public_description:
None,
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_C_RING_IV_USED.DN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(30),
umask:
Tuple::One(12),
event_name:
"UNC_C_RING_IV_USED.DN",
brief_description:
"BL Ring in Use; Any",
public_description:
Some("Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring in HSX Therefore, if one wants to monitor the \'Even\' ring, they should select both UP_EVEN and DN_EVEN. To monitor the \'Odd\' ring, they should select both UP_ODD and DN_ODD.; Filters any polarity"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_HOM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(46),
umask:
Tuple::One(16),
event_name:
"UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_HOM",
brief_description:
"QPI1 AD Credits Empty",
public_description:
Some("No credits available to send to QPI1 on the AD Ring; VN1 HOM Messages"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_P_CORE8_TRANSITION_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(104),
umask:
Tuple::One(0),
event_name:
"UNC_P_CORE8_TRANSITION_CYCLES",
brief_description:
"Core C State Transition Cycles",
public_description:
Some("Number of cycles spent performing core C state transitions. There is one event per core."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_P_FREQ_TRANS_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(116),
umask:
Tuple::One(0),
event_name:
"UNC_P_FREQ_TRANS_CYCLES",
brief_description:
"Cycles spent changing Frequency",
public_description:
Some("Counts the number of cycles when the system is changing frequency. This can not be filtered by thread ID. One can also use it with the occupancy counter that monitors number of threads in C0 to estimate the performance impact that frequency transitions had on the system."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_C_MISC.RFO_HIT_S",
IntelPerformanceCounterDescription{event_code:
Tuple::One(57),
umask:
Tuple::One(8),
event_name:
"UNC_C_MISC.RFO_HIT_S",
brief_description:
"Cbo Misc; RFO HitS",
public_description:
Some("Miscellaneous events in the Cbo.; Number of times that an RFO hit in S state. This is useful for determining if it might be good for a workload to use RspIWB instead of RspSWB."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_HOM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(47),
umask:
Tuple::One(2),
event_name:
"UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_HOM",
brief_description:
"QPI1 BL Credits Empty",
public_description:
Some("No credits available to send to QPI1 on the BL Ring; VN0 HOM Messages"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxL_FLITS_G2.NCB_NONDATA",
IntelPerformanceCounterDescription{event_code:
Tuple::One(1),
umask:
Tuple::One(8),
event_name:
"UNC_Q_TxL_FLITS_G2.NCB_NONDATA",
brief_description:
"Flits Transferred - Group 2; Non-Coherent non-data Tx Flits",
public_description:
Some("Counts the number of flits trasmitted across the QPI Link. This is one of three \'groups\' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each \'flit\' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four \'fits\', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI \'speed\' (for example, 8.0 GT/s), the \'transfers\' here refer to \'fits\'. Therefore, in L0, the system will transfer 1 \'flit\' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as \'data\' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual \'data\' and an additional 16 bits of other information. To calculate \'data\' bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass non-data flits. These packets are generally used to transmit non-coherent data across QPI, and the flits counted here are for headers and other non-data flits. This includes extended headers."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_H_HITME_LOOKUP.WBMTOE_OR_S",
IntelPerformanceCounterDescription{event_code:
Tuple::One(112),
umask:
Tuple::One(8),
event_name:
"UNC_H_HITME_LOOKUP.WBMTOE_OR_S",
brief_description:
"Counts Number of times HitMe Cache is accessed; op is WbMtoE or WbMtoS",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_R3_RxR_INSERTS.DRS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(17),
umask:
Tuple::One(8),
event_name:
"UNC_R3_RxR_INSERTS.DRS",
brief_description:
"Ingress Allocations; DRS",
public_description:
Some("Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; DRS Ingress Queue"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_S_RxR_CRD_STARVED.AD_BNC",
IntelPerformanceCounterDescription{event_code:
Tuple::One(20),
umask:
Tuple::One(2),
event_name:
"UNC_S_RxR_CRD_STARVED.AD_BNC",
brief_description:
"Injection Starvation; AD - Bounces",
public_description:
Some("Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_C_RxR_OCCUPANCY.IRQ",
IntelPerformanceCounterDescription{event_code:
Tuple::One(17),
umask:
Tuple::One(1),
event_name:
"UNC_C_RxR_OCCUPANCY.IRQ",
brief_description:
"Ingress Occupancy; IRQ",
public_description:
Some("Counts number of entries in the specified Ingress queue in each cycle."),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_P_DEMOTIONS_CORE7",
IntelPerformanceCounterDescription{event_code:
Tuple::One(55),
umask:
Tuple::One(0),
event_name:
"UNC_P_DEMOTIONS_CORE7",
brief_description:
"Core C State Demotions",
public_description:
Some("Counts the number of times when a configurable cores had a C-state demotion"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_U_RACU_REQUESTS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(70),
umask:
Tuple::One(0),
event_name:
"UNC_U_RACU_REQUESTS",
brief_description:
"RACU Request",
public_description:
Some("Number outstanding register requests within message channel tracker"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("UBOX"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_FLITS_G1.HOM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(2),
umask:
Tuple::One(6),
event_name:
"UNC_Q_RxL_FLITS_G1.HOM",
brief_description:
"Flits Received - Group 1; HOM Flits",
public_description:
Some("Counts the number of flits received from the QPI Link. This is one of three \'groups\' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each \'flit\' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four \'fits\', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI \'speed\' (for example, 8.0 GT/s), the \'transfers\' here refer to \'fits\'. Therefore, in L0, the system will transfer 1 \'flit\' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as \'data\' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual \'data\' and an additional 16 bits of other information. To calculate \'data\' bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of flits received over QPI on the home channel."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_Q_RxL_CREDITS_CONSUMED_VN1.HOM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(57),
umask:
Tuple::One(8),
event_name:
"UNC_Q_RxL_CREDITS_CONSUMED_VN1.HOM",
brief_description:
"VN1 Credit Consumed; HOM",
public_description:
Some("Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the HOM message class."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_R2_RING_AK_USED.CCW_ODD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(8),
umask:
Tuple::One(8),
event_name:
"UNC_R2_RING_AK_USED.CCW_ODD",
brief_description:
"R2 AK Ring in Use; Counterclockwise and Odd",
public_description:
Some("Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN2",
IntelPerformanceCounterDescription{event_code:
Tuple::One(25),
umask:
Tuple::One(4),
event_name:
"UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN2",
brief_description:
"HA iMC CHN0 WPQ Credits Empty - Special; Channel 2",
public_description:
Some("Counts the number of cycles when there are no \'special\' credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC\'s WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and \'special\' requests such as ISOCH writes. This count only tracks the \'special\' credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_R2_TxR_NACK_CW.DN_AD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(38),
umask:
Tuple::One(1),
event_name:
"UNC_R2_TxR_NACK_CW.DN_AD",
brief_description:
"Egress CCW NACK; AD CCW",
public_description:
Some("AD CounterClockwise Egress Queue"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_CREDITS_CONSUMED_VN1.NCB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(57),
umask:
Tuple::One(2),
event_name:
"UNC_Q_RxL_CREDITS_CONSUMED_VN1.NCB",
brief_description:
"VN1 Credit Consumed; NCB",
public_description:
Some("Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the NCB message class."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_R3_VNA_CREDITS_REJECT.NCB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(52),
umask:
Tuple::One(16),
event_name:
"UNC_R3_VNA_CREDITS_REJECT.NCB",
brief_description:
"VNA Credit Reject; NCB Message Class",
public_description:
Some("Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_C_TOR_INSERTS.LOCAL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(53),
umask:
Tuple::One(40),
event_name:
"UNC_C_TOR_INSERTS.LOCAL",
brief_description:
"TOR Inserts; Local Memory",
public_description:
Some("Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent \'filters\' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select \'MISS_OPC_MATCH\' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted into the TOR that are satisifed by locally HOMed memory."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_H_SNP_RESP_RECV_LOCAL.OTHER",
IntelPerformanceCounterDescription{event_code:
Tuple::One(96),
umask:
Tuple::One(128),
event_name:
"UNC_H_SNP_RESP_RECV_LOCAL.OTHER",
brief_description:
"Snoop Responses Received Local; Other",
public_description:
Some("Number of snoop responses received for a Local request; Filters for all other snoop responses."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_STALLS_VN0.BGF_NDR",
IntelPerformanceCounterDescription{event_code:
Tuple::One(53),
umask:
Tuple::One(32),
event_name:
"UNC_Q_RxL_STALLS_VN0.BGF_NDR",
brief_description:
"Stalls Sending to R3QPI on VN0; BGF Stall - NCS",
public_description:
Some("Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the NCS message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_H_BYPASS_IMC.TAKEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(20),
umask:
Tuple::One(1),
event_name:
"UNC_H_BYPASS_IMC.TAKEN",
brief_description:
"HA to iMC Bypass; Taken",
public_description:
Some("Counts the number of times when the HA was able to bypass was attempted. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filted by when the bypass was taken and when it was not.; Filter for transactions that succeeded in taking the bypass."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_CAS_COUNT.WR_RMM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(4),
umask:
Tuple::One(8),
event_name:
"UNC_M_CAS_COUNT.WR_RMM",
brief_description:
"DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode",
public_description:
Some("DRAM RD_CAS and WR_CAS Commands; Counts the total number of Opportunistic\' DRAM Write CAS commands issued on this channel while in Read-Major-Mode."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_C_RING_BL_USED.UP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(29),
umask:
Tuple::One(3),
event_name:
"UNC_C_RING_BL_USED.UP",
brief_description:
"BL Ring in Use; Up",
public_description:
Some("Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the \'UP\' direction is on the clockwise ring and \'DN\' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_S_RING_BL_USED.UP_ODD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(29),
umask:
Tuple::One(2),
event_name:
"UNC_S_RING_BL_USED.UP_ODD",
brief_description:
"BL Ring in Use; Up and Odd",
public_description:
Some("Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the \'UP\' direction is on the clockwise ring and \'DN\' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_AD_CYCLES_FULL.SCHED0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(42),
umask:
Tuple::One(1),
event_name:
"UNC_H_TxR_AD_CYCLES_FULL.SCHED0",
brief_description:
"AD Egress Full; Scheduler 0",
public_description:
Some("AD Egress Full; Filter for cycles full from scheduler bank 0"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_LOCAL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(114),
umask:
Tuple::One(32),
event_name:
"UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_LOCAL",
brief_description:
"Accumulates Number of PV bits set on HitMe Cache Hits; op is RspIFwd or RspIFwdWb for a local request",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_CAS_COUNT.RD_WMM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(4),
umask:
Tuple::One(16),
event_name:
"UNC_M_CAS_COUNT.RD_WMM",
brief_description:
"DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in WMM",
public_description:
Some("DRAM RD_CAS and WR_CAS Commands"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK0.BANK8",
IntelPerformanceCounterDescription{event_code:
Tuple::One(176),
umask:
Tuple::One(8),
event_name:
"UNC_M_RD_CAS_RANK0.BANK8",
brief_description:
"RD_CAS Access to Rank 0; Bank 8",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_MAJOR_MODES.PARTIAL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(7),
umask:
Tuple::One(4),
event_name:
"UNC_M_MAJOR_MODES.PARTIAL",
brief_description:
"Cycles in a Major Mode; Partial Major Mode",
public_description:
Some("Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This major mode is used to drain starved underfill reads. Regular reads and writes are blocked and only underfill reads will be processed."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_CREDITS_CONSUMED_VN1.SNP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(57),
umask:
Tuple::One(16),
event_name:
"UNC_Q_RxL_CREDITS_CONSUMED_VN1.SNP",
brief_description:
"VN1 Credit Consumed; SNP",
public_description:
Some("Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the SNP message class."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_Q_VNA_CREDIT_RETURNS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(28),
umask:
Tuple::One(0),
event_name:
"UNC_Q_VNA_CREDIT_RETURNS",
brief_description:
"VNA Credits Returned",
public_description:
Some("Number of VNA credits returned."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_M_RD_CAS_RANK7.BANK11",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(11),
event_name:
"UNC_M_RD_CAS_RANK7.BANK11",
brief_description:
"RD_CAS Access to Rank 7; Bank 11",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK0.BANKG2",
IntelPerformanceCounterDescription{event_code:
Tuple::One(176),
umask:
Tuple::One(19),
event_name:
"UNC_M_RD_CAS_RANK0.BANKG2",
brief_description:
"RD_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK4.BANK3",
IntelPerformanceCounterDescription{event_code:
Tuple::One(188),
umask:
Tuple::One(3),
event_name:
"UNC_M_WR_CAS_RANK4.BANK3",
brief_description:
"WR_CAS Access to Rank 4; Bank 3",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_R3_RING_IV_USED.CW",
IntelPerformanceCounterDescription{event_code:
Tuple::One(10),
umask:
Tuple::One(3),
event_name:
"UNC_R3_RING_IV_USED.CW",
brief_description:
"R3 IV Ring in Use; Clockwise",
public_description:
Some("Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop."),
counter:
Counter::Programmable(7),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_R3_STALL_NO_SBO_CREDIT.SBO0_AD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(44),
umask:
Tuple::One(1),
event_name:
"UNC_R3_STALL_NO_SBO_CREDIT.SBO0_AD",
brief_description:
"Stall on No Sbo Credits; For SBo0, AD Ring",
public_description:
Some("Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_C_RxR_OCCUPANCY.IPQ",
IntelPerformanceCounterDescription{event_code:
Tuple::One(17),
umask:
Tuple::One(4),
event_name:
"UNC_C_RxR_OCCUPANCY.IPQ",
brief_description:
"Ingress Occupancy; IPQ",
public_description:
Some("Counts number of entries in the specified Ingress queue in each cycle."),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_H_IOT_CTS_HI.CTS2",
IntelPerformanceCounterDescription{event_code:
Tuple::One(101),
umask:
Tuple::One(1),
event_name:
"UNC_H_IOT_CTS_HI.CTS2",
brief_description:
"IOT Common Trigger Sequencer - Hi",
public_description:
Some("Debug Mask/Match Tie-Ins"),
counter:
Counter::Programmable(7),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK1.BANK14",
IntelPerformanceCounterDescription{event_code:
Tuple::One(177),
umask:
Tuple::One(14),
event_name:
"UNC_M_RD_CAS_RANK1.BANK14",
brief_description:
"RD_CAS Access to Rank 1; Bank 14",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_S_RING_AK_USED.DOWN_EVEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(28),
umask:
Tuple::One(4),
event_name:
"UNC_S_RING_AK_USED.DOWN_EVEN",
brief_description:
"AK Ring In Use; Down and Event",
public_description:
Some("Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the \'UP\' direction is on the clockwise ring and \'DN\' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Event ring polarity."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK7.BANK11",
IntelPerformanceCounterDescription{event_code:
Tuple::One(191),
umask:
Tuple::One(11),
event_name:
"UNC_M_WR_CAS_RANK7.BANK11",
brief_description:
"WR_CAS Access to Rank 7; Bank 11",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_R2_RING_IV_USED.CCW",
IntelPerformanceCounterDescription{event_code:
Tuple::One(10),
umask:
Tuple::One(12),
event_name:
"UNC_R2_RING_IV_USED.CCW",
brief_description:
"R2 IV Ring in Use; Counterclockwise",
public_description:
Some("Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_S_RxR_CRD_STARVED.AK",
IntelPerformanceCounterDescription{event_code:
Tuple::One(20),
umask:
Tuple::One(16),
event_name:
"UNC_S_RxR_CRD_STARVED.AK",
brief_description:
"Injection Starvation; AK",
public_description:
Some("Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_Q_DIRECT2CORE.SUCCESS_RBT_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(19),
umask:
Tuple::One(1),
event_name:
"UNC_Q_DIRECT2CORE.SUCCESS_RBT_HIT",
brief_description:
"Direct 2 Core Spawning; Spawn Success",
public_description:
Some("Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exlusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn was successful. There were sufficient credits, the RBT valid bit was set and there was an RBT tag match. The message was marked to spawn direct2core."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_AK_INSERTS.ALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(47),
umask:
Tuple::One(3),
event_name:
"UNC_H_TxR_AK_INSERTS.ALL",
brief_description:
"AK Egress Allocations; All",
public_description:
Some("AK Egress Allocations; Allocations from both schedulers"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK7.BANKG0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(17),
event_name:
"UNC_M_RD_CAS_RANK7.BANKG0",
brief_description:
"RD_CAS Access to Rank 7; Bank Group 0 (Banks 0-3)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK5.BANK7",
IntelPerformanceCounterDescription{event_code:
Tuple::One(189),
umask:
Tuple::One(7),
event_name:
"UNC_M_WR_CAS_RANK5.BANK7",
brief_description:
"WR_CAS Access to Rank 5; Bank 7",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_P_UFS_TRANSITIONS_NO_CHANGE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(121),
umask:
Tuple::One(0),
event_name:
"UNC_P_UFS_TRANSITIONS_NO_CHANGE",
brief_description:
"tbd",
public_description:
Some("Ring GV with same final and initial frequency"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK4.BANKG3",
IntelPerformanceCounterDescription{event_code:
Tuple::One(188),
umask:
Tuple::One(20),
event_name:
"UNC_M_WR_CAS_RANK4.BANKG3",
brief_description:
"WR_CAS Access to Rank 4; Bank Group 3 (Banks 12-15)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_H_REQUESTS.WRITES_LOCAL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(1),
umask:
Tuple::One(4),
event_name:
"UNC_H_REQUESTS.WRITES_LOCAL",
brief_description:
"Read and Write Requests; Local Writes",
public_description:
Some("Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only writes coming from the local socket."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_P_CORE14_TRANSITION_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(110),
umask:
Tuple::One(0),
event_name:
"UNC_P_CORE14_TRANSITION_CYCLES",
brief_description:
"Core C State Transition Cycles",
public_description:
Some("Number of cycles spent performing core C state transitions. There is one event per core."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_P_DEMOTIONS_CORE9",
IntelPerformanceCounterDescription{event_code:
Tuple::One(57),
umask:
Tuple::One(0),
event_name:
"UNC_P_DEMOTIONS_CORE9",
brief_description:
"Core C State Demotions",
public_description:
Some("Counts the number of times when a configurable cores had a C-state demotion"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(21),
umask:
Tuple::One(2),
event_name:
"UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN1",
brief_description:
"iMC RPQ Credits Empty - Regular; Channel 1",
public_description:
Some("Counts the number of cycles when there are no \'regular\' credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC\'s RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and \'special\' requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_AD_CYCLES_FULL.ALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(42),
umask:
Tuple::One(3),
event_name:
"UNC_H_TxR_AD_CYCLES_FULL.ALL",
brief_description:
"AD Egress Full; All",
public_description:
Some("AD Egress Full; Cycles full from both schedulers"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_S_RxR_INSERTS.AD_BNC",
IntelPerformanceCounterDescription{event_code:
Tuple::One(19),
umask:
Tuple::One(2),
event_name:
"UNC_S_RxR_INSERTS.AD_BNC",
brief_description:
"Ingress Allocations; AD - Bounces",
public_description:
Some("Number of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_I_TxR_REQUEST_OCCUPANCY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(13),
umask:
Tuple::One(0),
event_name:
"UNC_I_TxR_REQUEST_OCCUPANCY",
brief_description:
"Outbound Request Queue Occupancy",
public_description:
Some("Accumultes the number of outstanding outbound requests from the IRP to the switch (towards the devices). This can be used in conjuection with the allocations event in order to calculate average latency of outbound requests."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_M_MAJOR_MODES.ISOCH",
IntelPerformanceCounterDescription{event_code:
Tuple::One(7),
umask:
Tuple::One(8),
event_name:
"UNC_M_MAJOR_MODES.ISOCH",
brief_description:
"Cycles in a Major Mode; Isoch Major Mode",
public_description:
Some("Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; We group these two modes together so that we can use four counters to track each of the major modes at one time. These major modes are used whenever there is an ISOCH txn in the memory controller. In these mode, only ISOCH transactions are processed."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_S_TxR_OCCUPANCY.AD_CRD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(1),
umask:
Tuple::One(1),
event_name:
"UNC_S_TxR_OCCUPANCY.AD_CRD",
brief_description:
"Egress Occupancy; AD - Credits",
public_description:
Some("Occupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK1.BANK1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(177),
umask:
Tuple::One(1),
event_name:
"UNC_M_RD_CAS_RANK1.BANK1",
brief_description:
"RD_CAS Access to Rank 1; Bank 1",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_I_COHERENT_OPS.RFO",
IntelPerformanceCounterDescription{event_code:
Tuple::One(19),
umask:
Tuple::One(8),
event_name:
"UNC_I_COHERENT_OPS.RFO",
brief_description:
"Coherent Ops; RFO",
public_description:
Some("Counts the number of coherency related operations servied by the IRP"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK6.BANK13",
IntelPerformanceCounterDescription{event_code:
Tuple::One(190),
umask:
Tuple::One(13),
event_name:
"UNC_M_WR_CAS_RANK6.BANK13",
brief_description:
"WR_CAS Access to Rank 6; Bank 13",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_PRE_COUNT.WR",
IntelPerformanceCounterDescription{event_code:
Tuple::One(2),
umask:
Tuple::One(8),
event_name:
"UNC_M_PRE_COUNT.WR",
brief_description:
"DRAM Precharge commands.; Precharge due to write",
public_description:
Some("Counts the number of DRAM Precharge commands sent on this channel."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK4.BANK8",
IntelPerformanceCounterDescription{event_code:
Tuple::One(180),
umask:
Tuple::One(8),
event_name:
"UNC_M_RD_CAS_RANK4.BANK8",
brief_description:
"RD_CAS Access to Rank 4; Bank 8",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK5.BANK10",
IntelPerformanceCounterDescription{event_code:
Tuple::One(181),
umask:
Tuple::One(10),
event_name:
"UNC_M_RD_CAS_RANK5.BANK10",
brief_description:
"RD_CAS Access to Rank 5; Bank 10",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_H_IOT_CTS_WEST_LO.CTS1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(98),
umask:
Tuple::One(2),
event_name:
"UNC_H_IOT_CTS_WEST_LO.CTS1",
brief_description:
"IOT Common Trigger Sequencer - Lo",
public_description:
Some("Debug Mask/Match Tie-Ins"),
counter:
Counter::Programmable(7),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_I_MISC0.UNKNOWN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(20),
umask:
Tuple::One(128),
event_name:
"UNC_I_MISC0.UNKNOWN",
brief_description:
"Misc Events - Set 0",
public_description:
Some("RTLSignal: iirpc2irppm_misc0_events0[7] + iirpc2irppm_misc0_events1[7];RTLSignal2: .iirpc2irppm_misc0_events0[6]+.iirpc2irppm_misc0_events1[6]"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_I_TxR_AD_STALL_CREDIT_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(24),
umask:
Tuple::One(0),
event_name:
"UNC_I_TxR_AD_STALL_CREDIT_CYCLES",
brief_description:
"No AD Egress Credit Stalls",
public_description:
Some("Counts the number times when it is not possible to issue a request to the R2PCIe because there are no AD Egress Credits available."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_SNP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(47),
umask:
Tuple::One(32),
event_name:
"UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_SNP",
brief_description:
"QPI1 BL Credits Empty",
public_description:
Some("No credits available to send to QPI1 on the BL Ring; VN1 SNP Messages"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_S_RING_BOUNCES.BL_CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(5),
umask:
Tuple::One(4),
event_name:
"UNC_S_RING_BOUNCES.BL_CORE",
brief_description:
"Number of LLC responses that bounced on the Ring.; Data Responses to core",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_I_RxR_BL_NCS_OCCUPANCY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(9),
umask:
Tuple::One(0),
event_name:
"UNC_I_RxR_BL_NCS_OCCUPANCY",
brief_description:
"tbd",
public_description:
Some("Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_M_POWER_THROTTLE_CYCLES.RANK4",
IntelPerformanceCounterDescription{event_code:
Tuple::One(65),
umask:
Tuple::One(16),
event_name:
"UNC_M_POWER_THROTTLE_CYCLES.RANK4",
brief_description:
"Throttle Cycles for Rank 0; DIMM ID",
public_description:
Some("Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK7.BANK5",
IntelPerformanceCounterDescription{event_code:
Tuple::One(191),
umask:
Tuple::One(5),
event_name:
"UNC_M_WR_CAS_RANK7.BANK5",
brief_description:
"WR_CAS Access to Rank 7; Bank 5",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(21),
umask:
Tuple::One(1),
event_name:
"UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN0",
brief_description:
"iMC RPQ Credits Empty - Regular; Channel 0",
public_description:
Some("Counts the number of cycles when there are no \'regular\' credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC\'s RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and \'special\' requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK6.BANK1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(182),
umask:
Tuple::One(1),
event_name:
"UNC_M_RD_CAS_RANK6.BANK1",
brief_description:
"RD_CAS Access to Rank 6; Bank 1",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_U_U2C_EVENTS.OTHER",
IntelPerformanceCounterDescription{event_code:
Tuple::One(67),
umask:
Tuple::One(128),
event_name:
"UNC_U_U2C_EVENTS.OTHER",
brief_description:
"Monitor Sent to T0; Other",
public_description:
Some("Events coming from Uncore can be sent to one or all cores; PREQ, PSMI, P2U, Thermal, PCUSMI, PMI"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("UBOX"),
filter:
None,
extsel:
false,}),
("UNC_R2_IIO_CREDIT.PRQ_QPI0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(45),
umask:
Tuple::One(1),
event_name:
"UNC_R2_IIO_CREDIT.PRQ_QPI0",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_R3_VN0_CREDITS_REJECT.NCS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(55),
umask:
Tuple::One(32),
event_name:
"UNC_R3_VN0_CREDITS_REJECT.NCS",
brief_description:
"VN0 Credit Acquisition Failed on DRS; NCS Message Class",
public_description:
Some("Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for Non-Coherent Standard (NCS). NCS is commonly used for ?"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK6.BANK7",
IntelPerformanceCounterDescription{event_code:
Tuple::One(182),
umask:
Tuple::One(7),
event_name:
"UNC_M_RD_CAS_RANK6.BANK7",
brief_description:
"RD_CAS Access to Rank 6; Bank 7",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_I_TRANSACTIONS.RD_PREF",
IntelPerformanceCounterDescription{event_code:
Tuple::One(22),
umask:
Tuple::One(4),
event_name:
"UNC_I_TRANSACTIONS.RD_PREF",
brief_description:
"Inbound Transaction Count; Read Prefetches",
public_description:
Some("Counts the number of \'Inbound\' transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of read prefetches."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_R3_RxR_CYCLES_NE_VN1.SNP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(20),
umask:
Tuple::One(2),
event_name:
"UNC_R3_RxR_CYCLES_NE_VN1.SNP",
brief_description:
"VN1 Ingress Cycles Not Empty; SNP",
public_description:
Some("Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK4.BANK0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(180),
umask:
Tuple::One(0),
event_name:
"UNC_M_RD_CAS_RANK4.BANK0",
brief_description:
"RD_CAS Access to Rank 4; Bank 0",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_H_SNOOP_RESP.RSPCNFLCT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(33),
umask:
Tuple::One(64),
event_name:
"UNC_H_SNOOP_RESP.RSPCNFLCT",
brief_description:
"Snoop Responses Received; RSPCNFLCT*",
public_description:
Some("Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoops responses of RspConflict. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent. This triggers conflict resolution hardware. This covers both RspCnflct and RspCnflctWbI."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_R3_RING_AD_USED.CW_EVEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(7),
umask:
Tuple::One(1),
event_name:
"UNC_R3_RING_AD_USED.CW_EVEN",
brief_description:
"R3 AD Ring in Use; Clockwise and Even",
public_description:
Some("Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity."),
counter:
Counter::Programmable(7),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_P_FREQ_BAND0_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(11),
umask:
Tuple::One(0),
event_name:
"UNC_P_FREQ_BAND0_CYCLES",
brief_description:
"Frequency Residency",
public_description:
Some("Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter. One can use all four counters with this event, so it is possible to track up to 4 configurable bands. One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
Some("PCUFilter[7:0]"),
extsel:
false,}),
("UNC_H_OSB_EDR.READS_REMOTE_I",
IntelPerformanceCounterDescription{event_code:
Tuple::One(84),
umask:
Tuple::One(4),
event_name:
"UNC_H_OSB_EDR.READS_REMOTE_I",
brief_description:
"OSB Early Data Return; Reads to Remote I",
public_description:
Some("Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxL_FLITS_G2.NCB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(1),
umask:
Tuple::One(12),
event_name:
"UNC_Q_TxL_FLITS_G2.NCB",
brief_description:
"Flits Transferred - Group 2; Non-Coherent Bypass Tx Flits",
public_description:
Some("Counts the number of flits trasmitted across the QPI Link. This is one of three \'groups\' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each \'flit\' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four \'fits\', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI \'speed\' (for example, 8.0 GT/s), the \'transfers\' here refer to \'fits\'. Therefore, in L0, the system will transfer 1 \'flit\' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as \'data\' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual \'data\' and an additional 16 bits of other information. To calculate \'data\' bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass flits. These packets are generally used to transmit non-coherent data across QPI."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_M_RD_CAS_RANK0.BANKG0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(176),
umask:
Tuple::One(17),
event_name:
"UNC_M_RD_CAS_RANK0.BANKG0",
brief_description:
"RD_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_I_MISC1.SLOW_E",
IntelPerformanceCounterDescription{event_code:
Tuple::One(21),
umask:
Tuple::One(4),
event_name:
"UNC_I_MISC1.SLOW_E",
brief_description:
"Misc Events - Set 1; Slow Transfer of E Line",
public_description:
Some("Secondary received a transfer that did have sufficient MESI state"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_H_REQUESTS.READS_LOCAL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(1),
umask:
Tuple::One(1),
event_name:
"UNC_H_REQUESTS.READS_LOCAL",
brief_description:
"Read and Write Requests; Local Reads",
public_description:
Some("Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only read requests coming from the local socket. This is a good proxy for LLC Read Misses (including RFOs) from the local socket."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_SBO1_CREDITS_ACQUIRED.AD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(105),
umask:
Tuple::One(1),
event_name:
"UNC_H_SBO1_CREDITS_ACQUIRED.AD",
brief_description:
"SBo1 Credits Acquired; For AD Ring",
public_description:
Some("Number of Sbo 1 credits acquired in a given cycle, per ring."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK0.BANK0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(176),
umask:
Tuple::One(0),
event_name:
"UNC_M_RD_CAS_RANK0.BANK0",
brief_description:
"RD_CAS Access to Rank 0; Bank 0",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_C_TxR_STARVED.IV",
IntelPerformanceCounterDescription{event_code:
Tuple::One(3),
umask:
Tuple::One(8),
event_name:
"UNC_C_TxR_STARVED.IV",
brief_description:
"Injection Starvation; Onto IV Ring",
public_description:
Some("Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that the cachebo IV egress spent in starvation"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_S_TxR_ADS_USED.BL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(4),
umask:
Tuple::One(4),
event_name:
"UNC_S_TxR_ADS_USED.BL",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_CYCLES_NE_NCB.VN1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(16),
umask:
Tuple::One(2),
event_name:
"UNC_Q_RxL_CYCLES_NE_NCB.VN1",
brief_description:
"RxQ Cycles Not Empty - NCB; for VN1",
public_description:
Some("Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NCB flits only."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_R3_RxR_CYCLES_NE.NDR",
IntelPerformanceCounterDescription{event_code:
Tuple::One(16),
umask:
Tuple::One(4),
event_name:
"UNC_R3_RxR_CYCLES_NE.NDR",
brief_description:
"Ingress Cycles Not Empty; NDR",
public_description:
Some("Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_C_TOR_OCCUPANCY.OPCODE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(54),
umask:
Tuple::One(1),
event_name:
"UNC_C_TOR_OCCUPANCY.OPCODE",
brief_description:
"TOR Occupancy; Opcode Match",
public_description:
Some("For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent \'filters\' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select \'MISS_OPC_MATCH\' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)."),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
Some("CBoFilter1[28:20]"),
extsel:
false,}),
("UNC_Q_RxL_STALLS_VN1.BGF_DRS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(58),
umask:
Tuple::One(1),
event_name:
"UNC_Q_RxL_STALLS_VN1.BGF_DRS",
brief_description:
"Stalls Sending to R3QPI on VN1; BGF Stall - HOM",
public_description:
Some("Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the HOM message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_P_PKG_RESIDENCY_C3_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(44),
umask:
Tuple::One(0),
event_name:
"UNC_P_PKG_RESIDENCY_C3_CYCLES",
brief_description:
"Package C State Residency - C3",
public_description:
Some("Counts the number of cycles when the package was in C3. This event can be used in conjunction with edge detect to count C3 entrances (or exits using invert). Residency events do not include transition times."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_H_TRACKER_CYCLES_NE.REMOTE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(3),
umask:
Tuple::One(2),
event_name:
"UNC_H_TRACKER_CYCLES_NE.REMOTE",
brief_description:
"Tracker Cycles Not Empty; Remote Requests",
public_description:
Some("Counts the number of cycles when the local HA tracker pool is not empty. This can be used with edge detect to identify the number of situations when the pool became empty. This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure. In other words, this buffer could be completely empty, but there may still be credits in use by the CBos. This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occpancy. HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; This filter includes only requests coming from remote sockets."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_C_RxR_ISMQ_RETRY.QPI_CREDITS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(51),
umask:
Tuple::One(16),
event_name:
"UNC_C_RxR_ISMQ_RETRY.QPI_CREDITS",
brief_description:
"ISMQ Retries; No QPI Credits",
public_description:
Some("Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_H_TRACKER_PENDING_OCCUPANCY.LOCAL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(5),
umask:
Tuple::One(1),
event_name:
"UNC_H_TRACKER_PENDING_OCCUPANCY.LOCAL",
brief_description:
"Data Pending Occupancy Accumultor; Local Requests",
public_description:
Some("Accumulates the number of transactions that have data from the memory controller until they get scheduled to the Egress. This can be used to calculate the queuing latency for two things. (1) If the system is waiting for snoops, this will increase. (2) If the system can\'t schedule to the Egress because of either (a) Egress Credits or (b) QPI BL IGR credits for remote requests.; This filter includes only requests coming from the local socket."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_S_RING_SINK_STARVED.BL_CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(6),
umask:
Tuple::One(4),
event_name:
"UNC_S_RING_SINK_STARVED.BL_CORE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO_15_17",
IntelPerformanceCounterDescription{event_code:
Tuple::One(31),
umask:
Tuple::One(128),
event_name:
"UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO_15_17",
brief_description:
"CBox AD Credits Empty",
public_description:
Some("No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 15&17"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_C_TOR_INSERTS.NID_ALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(53),
umask:
Tuple::One(72),
event_name:
"UNC_C_TOR_INSERTS.NID_ALL",
brief_description:
"TOR Inserts; NID Matched",
public_description:
Some("Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent \'filters\' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select \'MISS_OPC_MATCH\' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All NID matched (matches an RTID destination) transactions inserted into the TOR. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid. In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
Some("CBoFilter1[15:0]"),
extsel:
false,}),
("UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(19),
umask:
Tuple::One(128),
event_name:
"UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT_MISS",
brief_description:
"Direct 2 Core Spawning; Spawn Failure - Egress and RBT Miss, Invalid",
public_description:
Some("Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exlusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match, the valid bit was not set and there weren\'t enough Egress credits."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_H_RING_AD_USED.CW_EVEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(62),
umask:
Tuple::One(1),
event_name:
"UNC_H_RING_AD_USED.CW_EVEN",
brief_description:
"HA AD Ring in Use; Clockwise and Even",
public_description:
Some("Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(31),
umask:
Tuple::One(2),
event_name:
"UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN1",
brief_description:
"R3QPI Egress Credit Occupancy - BL DRS; for VN1",
public_description:
Some("Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. DRS message class to BL Egress."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_M_RD_CAS_RANK4.BANK14",
IntelPerformanceCounterDescription{event_code:
Tuple::One(180),
umask:
Tuple::One(14),
event_name:
"UNC_M_RD_CAS_RANK4.BANK14",
brief_description:
"RD_CAS Access to Rank 4; Bank 14",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_POWER_SELF_REFRESH",
IntelPerformanceCounterDescription{event_code:
Tuple::One(67),
umask:
Tuple::One(0),
event_name:
"UNC_M_POWER_SELF_REFRESH",
brief_description:
"Clock-Enabled Self-Refresh",
public_description:
Some("Counts the number of cycles when the iMC is in self-refresh and the iMC still has a clock. This happens in some package C-states. For example, the PCU may ask the iMC to enter self-refresh even though some of the cores are still processing. One use of this is for Monroe technology. Self-refresh is required during package C3 and C6, but there is no clock in the iMC at this time, so it is not possible to count these cases."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK7.BANK13",
IntelPerformanceCounterDescription{event_code:
Tuple::One(191),
umask:
Tuple::One(13),
event_name:
"UNC_M_WR_CAS_RANK7.BANK13",
brief_description:
"WR_CAS Access to Rank 7; Bank 13",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK1.BANK15",
IntelPerformanceCounterDescription{event_code:
Tuple::One(185),
umask:
Tuple::One(15),
event_name:
"UNC_M_WR_CAS_RANK1.BANK15",
brief_description:
"WR_CAS Access to Rank 1; Bank 15",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_STALLS_VN1.BGF_NCB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(58),
umask:
Tuple::One(2),
event_name:
"UNC_Q_RxL_STALLS_VN1.BGF_NCB",
brief_description:
"Stalls Sending to R3QPI on VN1; BGF Stall - SNP",
public_description:
Some("Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the SNP message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_H_DIRECTORY_UPDATE.CLEAR",
IntelPerformanceCounterDescription{event_code:
Tuple::One(13),
umask:
Tuple::One(2),
event_name:
"UNC_H_DIRECTORY_UPDATE.CLEAR",
brief_description:
"Directory Updates; Directory Clear",
public_description:
Some("Counts the number of directory updates that were required. These result in writes to the memory controller. This can be filtered by directory sets and directory clears.; Filter for directory clears. This occurs when snoops were sent and all returned with RspI."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_TAD_REQUESTS_G0.REGION2",
IntelPerformanceCounterDescription{event_code:
Tuple::One(27),
umask:
Tuple::One(4),
event_name:
"UNC_H_TAD_REQUESTS_G0.REGION2",
brief_description:
"HA Requests to a TAD Region - Group 0; TAD Region 2",
public_description:
Some("Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for \'Monroe\' systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 2"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_STALLS_VN0.BGF_SNP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(53),
umask:
Tuple::One(16),
event_name:
"UNC_Q_RxL_STALLS_VN0.BGF_SNP",
brief_description:
"Stalls Sending to R3QPI on VN0; BGF Stall - NCB",
public_description:
Some("Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the NCB message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_C_RxR_INSERTS.IRQ",
IntelPerformanceCounterDescription{event_code:
Tuple::One(19),
umask:
Tuple::One(1),
event_name:
"UNC_C_RxR_INSERTS.IRQ",
brief_description:
"Ingress Allocations; IRQ",
public_description:
Some("Counts number of allocations per cycle into the specified Ingress queue."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxL_FLITS_G2.NDR_AK",
IntelPerformanceCounterDescription{event_code:
Tuple::One(1),
umask:
Tuple::One(2),
event_name:
"UNC_Q_TxL_FLITS_G2.NDR_AK",
brief_description:
"Flits Transferred - Group 2; Non-Data Response Tx Flits - AK",
public_description:
Some("Counts the number of flits trasmitted across the QPI Link. This is one of three \'groups\' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each \'flit\' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four \'fits\', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI \'speed\' (for example, 8.0 GT/s), the \'transfers\' here refer to \'fits\'. Therefore, in L0, the system will transfer 1 \'flit\' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as \'data\' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual \'data\' and an additional 16 bits of other information. To calculate \'data\' bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets destined for Route-thru to a remote socket."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_M_RD_CAS_RANK7.BANK9",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(9),
event_name:
"UNC_M_RD_CAS_RANK7.BANK9",
brief_description:
"RD_CAS Access to Rank 7; Bank 9",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_AK_CYCLES_FULL.ALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(50),
umask:
Tuple::One(3),
event_name:
"UNC_H_TxR_AK_CYCLES_FULL.ALL",
brief_description:
"AK Egress Full; All",
public_description:
Some("AK Egress Full; Cycles full from both schedulers"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK1.BANK10",
IntelPerformanceCounterDescription{event_code:
Tuple::One(185),
umask:
Tuple::One(10),
event_name:
"UNC_M_WR_CAS_RANK1.BANK10",
brief_description:
"WR_CAS Access to Rank 1; Bank 10",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_R2_IIO_CREDITS_ACQUIRED.NCS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(51),
umask:
Tuple::One(32),
event_name:
"UNC_R2_IIO_CREDITS_ACQUIRED.NCS",
brief_description:
"R2PCIe IIO Credit Acquired; NCS",
public_description:
Some("Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCS message class."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_P_CORE11_TRANSITION_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(107),
umask:
Tuple::One(0),
event_name:
"UNC_P_CORE11_TRANSITION_CYCLES",
brief_description:
"Core C State Transition Cycles",
public_description:
Some("Number of cycles spent performing core C state transitions. There is one event per core."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_R3_VN1_CREDITS_USED.NCS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(56),
umask:
Tuple::One(32),
event_name:
"UNC_R3_VN1_CREDITS_USED.NCS",
brief_description:
"VN1 Credit Used; NCS Message Class",
public_description:
Some("Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Standard (NCS). NCS is commonly used for ?"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK6.BANK6",
IntelPerformanceCounterDescription{event_code:
Tuple::One(190),
umask:
Tuple::One(6),
event_name:
"UNC_M_WR_CAS_RANK6.BANK6",
brief_description:
"WR_CAS Access to Rank 6; Bank 6",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_S_RxR_INSERTS.BL_CRD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(19),
umask:
Tuple::One(4),
event_name:
"UNC_S_RxR_INSERTS.BL_CRD",
brief_description:
"Ingress Allocations; BL - Credits",
public_description:
Some("Number of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_M_VMSE_WR_PUSH.WMM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(144),
umask:
Tuple::One(1),
event_name:
"UNC_M_VMSE_WR_PUSH.WMM",
brief_description:
"VMSE WR PUSH issued; VMSE write PUSH issued in WMM",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_R3_VN1_CREDITS_USED.NCB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(56),
umask:
Tuple::One(16),
event_name:
"UNC_R3_VN1_CREDITS_USED.NCB",
brief_description:
"VN1 Credit Used; NCB Message Class",
public_description:
Some("Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_C_LLC_LOOKUP.DATA_READ",
IntelPerformanceCounterDescription{event_code:
Tuple::One(52),
umask:
Tuple::One(3),
event_name:
"UNC_C_LLC_LOOKUP.DATA_READ",
brief_description:
"Cache Lookups; Data Read Request",
public_description:
Some("Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Read transactions"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
Some("CBoFilter0[23:17]"),
extsel:
false,}),
("UNC_Q_RxL_OCCUPANCY_NCS.VN1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(23),
umask:
Tuple::One(2),
event_name:
"UNC_Q_RxL_OCCUPANCY_NCS.VN1",
brief_description:
"RxQ Occupancy - NCS; for VN1",
public_description:
Some("Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCS flits only."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_C_RxR_ISMQ_RETRY.RTID",
IntelPerformanceCounterDescription{event_code:
Tuple::One(51),
umask:
Tuple::One(8),
event_name:
"UNC_C_RxR_ISMQ_RETRY.RTID",
brief_description:
"ISMQ Retries; No RTIDs",
public_description:
Some("Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Counts the number of times that a request from the ISMQ retried because of a TOR reject caused by no RTIDs. M-state cache evictions are serviced through the ISMQ, and must acquire an RTID in order to write back to memory. If no RTIDs are available, they will be retried."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_R3_VN0_CREDITS_REJECT.DRS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(55),
umask:
Tuple::One(8),
event_name:
"UNC_R3_VN0_CREDITS_REJECT.DRS",
brief_description:
"VN0 Credit Acquisition Failed on DRS; DRS Message Class",
public_description:
Some("Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxL_FLITS_G1.HOM_REQ",
IntelPerformanceCounterDescription{event_code:
Tuple::One(0),
umask:
Tuple::One(2),
event_name:
"UNC_Q_TxL_FLITS_G1.HOM_REQ",
brief_description:
"Flits Transferred - Group 1; HOM Request Flits",
public_description:
Some("Counts the number of flits trasmitted across the QPI Link. This is one of three \'groups\' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each \'flit\' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four \'fits\', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI \'speed\' (for example, 8.0 GT/s), the \'transfers\' here refer to \'fits\'. Therefore, in L0, the system will transfer 1 \'flit\' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as \'data\' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual \'data\' and an additional 16 bits of other information. To calculate \'data\' bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of data request transmitted over QPI on the home channel. This basically counts the number of remote memory requests transmitted over QPI. In conjunction with the local read count in the Home Agent, one can calculate the number of LLC Misses."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_M_POWER_CHANNEL_PPD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(133),
umask:
Tuple::One(0),
event_name:
"UNC_M_POWER_CHANNEL_PPD",
brief_description:
"Channel PPD Cycles",
public_description:
Some("Number of cycles when all the ranks in the channel are in PPD mode. If IBT=off is enabled, then this can be used to count those cycles. If it is not enabled, then this can count the number of cycles when that could have been taken advantage of."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_Q_CLOCKTICKS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(20),
umask:
Tuple::One(0),
event_name:
"UNC_Q_CLOCKTICKS",
brief_description:
"Number of qfclks",
public_description:
Some("Counts the number of clocks in the QPI LL. This clock runs at 1/4th the \'GT/s\' speed of the QPI link. For example, a 4GT/s link will have qfclk or 1GHz. HSX does not support dynamic link speeds, so this frequency is fixed."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_P_DEMOTIONS_CORE3",
IntelPerformanceCounterDescription{event_code:
Tuple::One(51),
umask:
Tuple::One(0),
event_name:
"UNC_P_DEMOTIONS_CORE3",
brief_description:
"Core C State Demotions",
public_description:
Some("Counts the number of times when a configurable cores had a C-state demotion"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK1.BANK6",
IntelPerformanceCounterDescription{event_code:
Tuple::One(177),
umask:
Tuple::One(6),
event_name:
"UNC_M_RD_CAS_RANK1.BANK6",
brief_description:
"RD_CAS Access to Rank 1; Bank 6",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxR_AD_SNP_CREDIT_ACQUIRED.VN1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(39),
umask:
Tuple::One(2),
event_name:
"UNC_Q_TxR_AD_SNP_CREDIT_ACQUIRED.VN1",
brief_description:
"R3QPI Egress Credit Occupancy - SNP; for VN1",
public_description:
Some("Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Snoop messages on AD."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_U_U2C_EVENTS.LTERROR",
IntelPerformanceCounterDescription{event_code:
Tuple::One(67),
umask:
Tuple::One(8),
event_name:
"UNC_U_U2C_EVENTS.LTERROR",
brief_description:
"Monitor Sent to T0; LTError",
public_description:
Some("Events coming from Uncore can be sent to one or all cores; Filter by core"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("UBOX"),
filter:
None,
extsel:
false,}),
("UNC_S_RING_SINK_STARVED.AD_CACHE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(6),
umask:
Tuple::One(1),
event_name:
"UNC_S_RING_SINK_STARVED.AD_CACHE",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_M_POWER_THROTTLE_CYCLES.RANK7",
IntelPerformanceCounterDescription{event_code:
Tuple::One(65),
umask:
Tuple::One(128),
event_name:
"UNC_M_POWER_THROTTLE_CYCLES.RANK7",
brief_description:
"Throttle Cycles for Rank 0; DIMM ID",
public_description:
Some("Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK5.BANK10",
IntelPerformanceCounterDescription{event_code:
Tuple::One(189),
umask:
Tuple::One(10),
event_name:
"UNC_M_WR_CAS_RANK5.BANK10",
brief_description:
"WR_CAS Access to Rank 5; Bank 10",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_R3_RING_AD_USED.CW_ODD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(7),
umask:
Tuple::One(2),
event_name:
"UNC_R3_RING_AD_USED.CW_ODD",
brief_description:
"R3 AD Ring in Use; Clockwise and Odd",
public_description:
Some("Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity."),
counter:
Counter::Programmable(7),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_R3_TxR_NACK.UP_BL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(38),
umask:
Tuple::One(16),
event_name:
"UNC_R3_TxR_NACK.UP_BL",
brief_description:
"Egress CCW NACK; BL CCW",
public_description:
Some("AD CounterClockwise Egress Queue"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_H_HITME_HIT.WBMTOE_OR_S",
IntelPerformanceCounterDescription{event_code:
Tuple::One(113),
umask:
Tuple::One(8),
event_name:
"UNC_H_HITME_HIT.WBMTOE_OR_S",
brief_description:
"Counts Number of Hits in HitMe Cache; op is WbMtoE or WbMtoS",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_R3_IOT_BACKPRESSURE.SAT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(11),
umask:
Tuple::One(1),
event_name:
"UNC_R3_IOT_BACKPRESSURE.SAT",
brief_description:
"IOT Backpressure",
public_description:
None,
counter:
Counter::Programmable(7),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK4.BANK12",
IntelPerformanceCounterDescription{event_code:
Tuple::One(180),
umask:
Tuple::One(12),
event_name:
"UNC_M_RD_CAS_RANK4.BANK12",
brief_description:
"RD_CAS Access to Rank 4; Bank 12",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_OCCUPANCY_HOM.VN1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(24),
umask:
Tuple::One(2),
event_name:
"UNC_Q_RxL_OCCUPANCY_HOM.VN1",
brief_description:
"RxQ Occupancy - HOM; for VN1",
public_description:
Some("Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors HOM flits only."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_R2_SBO0_CREDIT_OCCUPANCY.BL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(42),
umask:
Tuple::One(2),
event_name:
"UNC_R2_SBO0_CREDIT_OCCUPANCY.BL",
brief_description:
"SBo0 Credits Occupancy; For BL Ring",
public_description:
Some("Number of Sbo 0 credits in use in a given cycle, per ring."),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK0.BANK1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(184),
umask:
Tuple::One(1),
event_name:
"UNC_M_WR_CAS_RANK0.BANK1",
brief_description:
"WR_CAS Access to Rank 0; Bank 1",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_STALLS_VN0.BGF_HOM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(53),
umask:
Tuple::One(8),
event_name:
"UNC_Q_RxL_STALLS_VN0.BGF_HOM",
brief_description:
"Stalls Sending to R3QPI on VN0; BGF Stall - DRS",
public_description:
Some("Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the DRS message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_R2_RING_AK_USED.CW",
IntelPerformanceCounterDescription{event_code:
Tuple::One(8),
umask:
Tuple::One(3),
event_name:
"UNC_R2_RING_AK_USED.CW",
brief_description:
"R2 AK Ring in Use; Clockwise",
public_description:
Some("Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_C_TOR_OCCUPANCY.MISS_ALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(54),
umask:
Tuple::One(10),
event_name:
"UNC_C_TOR_OCCUPANCY.MISS_ALL",
brief_description:
"TOR Occupancy; Miss All",
public_description:
Some("For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent \'filters\' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select \'MISS_OPC_MATCH\' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding miss requests in the TOR. \'Miss\' means the allocation requires an RTID. This generally means that the request was sent to memory or MMIO."),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_H_HITME_HIT_PV_BITS_SET.ACKCNFLTWBI",
IntelPerformanceCounterDescription{event_code:
Tuple::One(114),
umask:
Tuple::One(4),
event_name:
"UNC_H_HITME_HIT_PV_BITS_SET.ACKCNFLTWBI",
brief_description:
"Accumulates Number of PV bits set on HitMe Cache Hits; op is AckCnfltWbI",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_R2_STALL_NO_SBO_CREDIT.SBO1_AD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(44),
umask:
Tuple::One(2),
event_name:
"UNC_R2_STALL_NO_SBO_CREDIT.SBO1_AD",
brief_description:
"Stall on No Sbo Credits; For SBo1, AD Ring",
public_description:
Some("Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK1.BANK11",
IntelPerformanceCounterDescription{event_code:
Tuple::One(177),
umask:
Tuple::One(11),
event_name:
"UNC_M_RD_CAS_RANK1.BANK11",
brief_description:
"RD_CAS Access to Rank 1; Bank 11",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_AD_CYCLES_FULL.SCHED1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(42),
umask:
Tuple::One(2),
event_name:
"UNC_H_TxR_AD_CYCLES_FULL.SCHED1",
brief_description:
"AD Egress Full; Scheduler 1",
public_description:
Some("AD Egress Full; Filter for cycles full from scheduler bank 1"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_S_RING_IV_USED.UP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(30),
umask:
Tuple::One(3),
event_name:
"UNC_S_RING_IV_USED.UP",
brief_description:
"BL Ring in Use; Any",
public_description:
Some("Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. There is only 1 IV ring in HSX. Therefore, if one wants to monitor the \'Even\' ring, they should select both UP_EVEN and DN_EVEN. To monitor the \'Odd\' ring, they should select both UP_ODD and DN_ODD.; Filters any polarity"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_H_ADDR_OPC_MATCH.BL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(32),
umask:
Tuple::One(8),
event_name:
"UNC_H_ADDR_OPC_MATCH.BL",
brief_description:
"QPI Address/Opcode Match; BL Opcodes",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
Some("HA_OpcodeMatch[5:0]"),
extsel:
false,}),
("UNC_M_RD_CAS_RANK5.BANK2",
IntelPerformanceCounterDescription{event_code:
Tuple::One(181),
umask:
Tuple::One(2),
event_name:
"UNC_M_RD_CAS_RANK5.BANK2",
brief_description:
"RD_CAS Access to Rank 5; Bank 2",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_R2_TxR_CYCLES_FULL.AD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(37),
umask:
Tuple::One(1),
event_name:
"UNC_R2_TxR_CYCLES_FULL.AD",
brief_description:
"Egress Cycles Full; AD",
public_description:
Some("Counts the number of cycles when the R2PCIe Egress buffer is full.; AD Egress Queue"),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_INSERTS_HOM.VN0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(12),
umask:
Tuple::One(1),
event_name:
"UNC_Q_RxL_INSERTS_HOM.VN0",
brief_description:
"Rx Flit Buffer Allocations - HOM; for VN0",
public_description:
Some("Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only HOM flits."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_M_WR_CAS_RANK4.BANKG2",
IntelPerformanceCounterDescription{event_code:
Tuple::One(188),
umask:
Tuple::One(19),
event_name:
"UNC_M_WR_CAS_RANK4.BANKG2",
brief_description:
"WR_CAS Access to Rank 4; Bank Group 2 (Banks 8-11)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK5.BANKG1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(189),
umask:
Tuple::One(18),
event_name:
"UNC_M_WR_CAS_RANK5.BANKG1",
brief_description:
"WR_CAS Access to Rank 5; Bank Group 1 (Banks 4-7)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK6.BANK3",
IntelPerformanceCounterDescription{event_code:
Tuple::One(182),
umask:
Tuple::One(3),
event_name:
"UNC_M_RD_CAS_RANK6.BANK3",
brief_description:
"RD_CAS Access to Rank 6; Bank 3",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_R3_QPI0_AD_CREDITS_EMPTY.VNA",
IntelPerformanceCounterDescription{event_code:
Tuple::One(32),
umask:
Tuple::One(1),
event_name:
"UNC_R3_QPI0_AD_CREDITS_EMPTY.VNA",
brief_description:
"QPI0 AD Credits Empty",
public_description:
Some("No credits available to send to QPI0 on the AD Ring; VNA"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_H_SNP_RESP_RECV_LOCAL.RSPxFWDxWB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(96),
umask:
Tuple::One(32),
event_name:
"UNC_H_SNP_RESP_RECV_LOCAL.RSPxFWDxWB",
brief_description:
"Snoop Responses Received Local; Rsp*FWD*WB",
public_description:
Some("Number of snoop responses received for a Local request; Filters for a snoop response of Rsp*Fwd*WB. This snoop response is only used in 4s systems. It is used when a snoop HITM\'s in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_POWER_THROTTLE_CYCLES.RANK2",
IntelPerformanceCounterDescription{event_code:
Tuple::One(65),
umask:
Tuple::One(4),
event_name:
"UNC_M_POWER_THROTTLE_CYCLES.RANK2",
brief_description:
"Throttle Cycles for Rank 0; DIMM ID",
public_description:
Some("Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_POWER_THROTTLE_CYCLES.RANK1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(65),
umask:
Tuple::One(2),
event_name:
"UNC_M_POWER_THROTTLE_CYCLES.RANK1",
brief_description:
"Throttle Cycles for Rank 0; DIMM ID",
public_description:
Some("Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_I_MISC0.FAST_REQ",
IntelPerformanceCounterDescription{event_code:
Tuple::One(20),
umask:
Tuple::One(1),
event_name:
"UNC_I_MISC0.FAST_REQ",
brief_description:
"Misc Events - Set 0; Fastpath Requests",
public_description:
None,
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK0.BANKG2",
IntelPerformanceCounterDescription{event_code:
Tuple::One(184),
umask:
Tuple::One(19),
event_name:
"UNC_M_WR_CAS_RANK0.BANKG2",
brief_description:
"WR_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK5.BANK0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(181),
umask:
Tuple::One(0),
event_name:
"UNC_M_RD_CAS_RANK5.BANK0",
brief_description:
"RD_CAS Access to Rank 5; Bank 0",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_R3_RxR_OCCUPANCY_VN1.NCB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(19),
umask:
Tuple::One(16),
event_name:
"UNC_R3_RxR_OCCUPANCY_VN1.NCB",
brief_description:
"VN1 Ingress Occupancy Accumulator; NCB",
public_description:
Some("Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.; NCB Ingress Queue"),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO2",
IntelPerformanceCounterDescription{event_code:
Tuple::One(34),
umask:
Tuple::One(4),
event_name:
"UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO2",
brief_description:
"CBox AD Credits Empty",
public_description:
Some("No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 2"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_C_RxR_IRQ_RETRY2.AD_SBO",
IntelPerformanceCounterDescription{event_code:
Tuple::One(41),
umask:
Tuple::One(1),
event_name:
"UNC_C_RxR_IRQ_RETRY2.AD_SBO",
brief_description:
"Ingress Request Queue Rejects; No AD Sbo Credits",
public_description:
Some("Counts the number of times that a request from the IPQ was retried because of it lacked credits to send an AD packet to the Sbo."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK5.BANK0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(189),
umask:
Tuple::One(0),
event_name:
"UNC_M_WR_CAS_RANK5.BANK0",
brief_description:
"WR_CAS Access to Rank 5; Bank 0",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK6.BANK0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(182),
umask:
Tuple::One(0),
event_name:
"UNC_M_RD_CAS_RANK6.BANK0",
brief_description:
"RD_CAS Access to Rank 6; Bank 0",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_INSERTS_NDR.VN1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(14),
umask:
Tuple::One(2),
event_name:
"UNC_Q_RxL_INSERTS_NDR.VN1",
brief_description:
"Rx Flit Buffer Allocations - NDR; for VN1",
public_description:
Some("Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NDR flits."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_P_PKG_RESIDENCY_C2E_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(43),
umask:
Tuple::One(0),
event_name:
"UNC_P_PKG_RESIDENCY_C2E_CYCLES",
brief_description:
"Package C State Residency - C2E",
public_description:
Some("Counts the number of cycles when the package was in C2E. This event can be used in conjunction with edge detect to count C2E entrances (or exits using invert). Residency events do not include transition times."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_U_U2C_EVENTS.TRAP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(67),
umask:
Tuple::One(64),
event_name:
"UNC_U_U2C_EVENTS.TRAP",
brief_description:
"Monitor Sent to T0; Trap",
public_description:
Some("Events coming from Uncore can be sent to one or all cores"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("UBOX"),
filter:
None,
extsel:
false,}),
("UNC_I_COHERENT_OPS.CLFLUSH",
IntelPerformanceCounterDescription{event_code:
Tuple::One(19),
umask:
Tuple::One(128),
event_name:
"UNC_I_COHERENT_OPS.CLFLUSH",
brief_description:
"Coherent Ops; CLFlush",
public_description:
Some("Counts the number of coherency related operations servied by the IRP"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_CYCLES_NE_NCS.VN1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(17),
umask:
Tuple::One(2),
event_name:
"UNC_Q_RxL_CYCLES_NE_NCS.VN1",
brief_description:
"RxQ Cycles Not Empty - NCS; for VN1",
public_description:
Some("Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NCS flits only."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_Q_CTO_COUNT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(56),
umask:
Tuple::One(0),
event_name:
"UNC_Q_CTO_COUNT",
brief_description:
"Count of CTO Events",
public_description:
Some("Counts the number of CTO (cluster trigger outs) events that were asserted across the two slots. If both slots trigger in a given cycle, the event will increment by 2. You can use edge detect to count the number of cases when both events triggered."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
Some("QPIMask0[17:0],QPIMatch0[17:0],QPIMask1[19:16],QPIMatch1[19:16]"),
extsel:
true,}),
("UNC_M_WR_CAS_RANK1.BANK13",
IntelPerformanceCounterDescription{event_code:
Tuple::One(185),
umask:
Tuple::One(13),
event_name:
"UNC_M_WR_CAS_RANK1.BANK13",
brief_description:
"WR_CAS Access to Rank 1; Bank 13",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_I_RxR_AK_INSERTS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(10),
umask:
Tuple::One(0),
event_name:
"UNC_I_RxR_AK_INSERTS",
brief_description:
"AK Ingress Occupancy",
public_description:
Some("Counts the number of allocations into the AK Ingress. This queue is where the IRP receives responses from R2PCIe (the ring)."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK1.ALLBANKS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(185),
umask:
Tuple::One(16),
event_name:
"UNC_M_WR_CAS_RANK1.ALLBANKS",
brief_description:
"WR_CAS Access to Rank 1; All Banks",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_C_RxR_INT_STARVED.PRQ",
IntelPerformanceCounterDescription{event_code:
Tuple::One(20),
umask:
Tuple::One(16),
event_name:
"UNC_C_RxR_INT_STARVED.PRQ",
brief_description:
"Ingress Internal Starvation Cycles; PRQ",
public_description:
Some("Counts cycles in internal starvation. This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_R3_RxR_INSERTS.NDR",
IntelPerformanceCounterDescription{event_code:
Tuple::One(17),
umask:
Tuple::One(4),
event_name:
"UNC_R3_RxR_INSERTS.NDR",
brief_description:
"Ingress Allocations; NDR",
public_description:
Some("Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_R3_RxR_INSERTS_VN1.NCB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(21),
umask:
Tuple::One(16),
event_name:
"UNC_R3_RxR_INSERTS_VN1.NCB",
brief_description:
"VN1 Ingress Allocations; NCB",
public_description:
Some("Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_R2_RxR_CYCLES_NE.NCS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(16),
umask:
Tuple::One(32),
event_name:
"UNC_R2_RxR_CYCLES_NE.NCS",
brief_description:
"Ingress Cycles Not Empty; NCS",
public_description:
Some("Counts the number of cycles when the R2PCIe Ingress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_U_EVENT_MSG.DOORBELL_RCVD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(66),
umask:
Tuple::One(8),
event_name:
"UNC_U_EVENT_MSG.DOORBELL_RCVD",
brief_description:
"VLW Received",
public_description:
Some("Virtual Logical Wire (legacy) message were received from Uncore. Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("UBOX"),
filter:
None,
extsel:
false,}),
("UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_SNP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(47),
umask:
Tuple::One(4),
event_name:
"UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_SNP",
brief_description:
"QPI1 BL Credits Empty",
public_description:
Some("No credits available to send to QPI1 on the BL Ring; VN0 SNP Messages"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK7.BANK8",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(8),
event_name:
"UNC_M_RD_CAS_RANK7.BANK8",
brief_description:
"RD_CAS Access to Rank 7; Bank 8",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_R2_TxR_CYCLES_FULL.AK",
IntelPerformanceCounterDescription{event_code:
Tuple::One(37),
umask:
Tuple::One(2),
event_name:
"UNC_R2_TxR_CYCLES_FULL.AK",
brief_description:
"Egress Cycles Full; AK",
public_description:
Some("Counts the number of cycles when the R2PCIe Egress buffer is full.; AK Egress Queue"),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_S_RING_BOUNCES.AK_CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(5),
umask:
Tuple::One(2),
event_name:
"UNC_S_RING_BOUNCES.AK_CORE",
brief_description:
"Number of LLC responses that bounced on the Ring.; Acknowledgements to core",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO9",
IntelPerformanceCounterDescription{event_code:
Tuple::One(31),
umask:
Tuple::One(2),
event_name:
"UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO9",
brief_description:
"CBox AD Credits Empty",
public_description:
Some("No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 9"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_I_TRANSACTIONS.ORDERINGQ",
IntelPerformanceCounterDescription{event_code:
Tuple::One(22),
umask:
Tuple::One(64),
event_name:
"UNC_I_TRANSACTIONS.ORDERINGQ",
brief_description:
"Inbound Transaction Count; Select Source",
public_description:
Some("Counts the number of \'Inbound\' transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register. This register allows one to select one specific queue. It is not possible to monitor multiple queues at a time. If this bit is not set, then requests from all sources will be counted."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
Some("IRPFilter[4:0]"),
extsel:
false,}),
("UNC_R3_RING_BL_USED.CW_EVEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(9),
umask:
Tuple::One(1),
event_name:
"UNC_R3_RING_BL_USED.CW_EVEN",
brief_description:
"R3 BL Ring in Use; Clockwise and Even",
public_description:
Some("Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity."),
counter:
Counter::Programmable(7),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK0.BANK6",
IntelPerformanceCounterDescription{event_code:
Tuple::One(176),
umask:
Tuple::One(6),
event_name:
"UNC_M_RD_CAS_RANK0.BANK6",
brief_description:
"RD_CAS Access to Rank 0; Bank 6",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_Q_DIRECT2CORE.FAILURE_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(19),
umask:
Tuple::One(16),
event_name:
"UNC_Q_DIRECT2CORE.FAILURE_MISS",
brief_description:
"Direct 2 Core Spawning; Spawn Failure - RBT Miss",
public_description:
Some("Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exlusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match although the valid bit was set and there were enough Egress credits."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxL_INSERTS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(4),
umask:
Tuple::One(0),
event_name:
"UNC_Q_TxL_INSERTS",
brief_description:
"Tx Flit Buffer Allocations",
public_description:
Some("Number of allocations into the QPI Tx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_SNP_HAZARD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(81),
umask:
Tuple::One(2),
event_name:
"UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_SNP_HAZARD",
brief_description:
"BT to HT Not Issued; Incoming Snoop Hazard",
public_description:
Some("Counts the number of cycles when the HA does not issue transaction from BT to HT.; Cycles unable to issue from BT due to incoming snoop hazard"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_U_U2C_EVENTS.LIVELOCK",
IntelPerformanceCounterDescription{event_code:
Tuple::One(67),
umask:
Tuple::One(4),
event_name:
"UNC_U_U2C_EVENTS.LIVELOCK",
brief_description:
"Monitor Sent to T0; Livelock",
public_description:
Some("Events coming from Uncore can be sent to one or all cores; Filter by core"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("UBOX"),
filter:
None,
extsel:
false,}),
("UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_SNP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(33),
umask:
Tuple::One(32),
event_name:
"UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_SNP",
brief_description:
"QPI0 BL Credits Empty",
public_description:
Some("No credits available to send to QPI0 on the BL Ring; VN1 SNP Messages"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_PRIO.LOW",
IntelPerformanceCounterDescription{event_code:
Tuple::One(160),
umask:
Tuple::One(1),
event_name:
"UNC_M_RD_CAS_PRIO.LOW",
brief_description:
"Read CAS issued with LOW priority",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_R2_TxR_NACK_CW.DN_BL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(38),
umask:
Tuple::One(2),
event_name:
"UNC_R2_TxR_NACK_CW.DN_BL",
brief_description:
"Egress CCW NACK; BL CCW",
public_description:
Some("BL CounterClockwise Egress Queue"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_H_TAD_REQUESTS_G1.REGION9",
IntelPerformanceCounterDescription{event_code:
Tuple::One(28),
umask:
Tuple::One(2),
event_name:
"UNC_H_TAD_REQUESTS_G1.REGION9",
brief_description:
"HA Requests to a TAD Region - Group 1; TAD Region 9",
public_description:
Some("Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 8 to 10. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for \'Monroe\' systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 9"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK7.BANK15",
IntelPerformanceCounterDescription{event_code:
Tuple::One(191),
umask:
Tuple::One(15),
event_name:
"UNC_M_WR_CAS_RANK7.BANK15",
brief_description:
"WR_CAS Access to Rank 7; Bank 15",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_P_PKG_RESIDENCY_C1E_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(78),
umask:
Tuple::One(0),
event_name:
"UNC_P_PKG_RESIDENCY_C1E_CYCLES",
brief_description:
"Package C State Residency - C1E",
public_description:
Some("Counts the number of cycles when the package was in C1E. This event can be used in conjunction with edge detect to count C1E entrances (or exits using invert). Residency events do not include transition times."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_C_TxR_ADS_USED.BL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(4),
umask:
Tuple::One(4),
event_name:
"UNC_C_TxR_ADS_USED.BL",
brief_description:
"Onto BL Ring",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_C_TOR_OCCUPANCY.ALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(54),
umask:
Tuple::One(8),
event_name:
"UNC_C_TOR_OCCUPANCY.ALL",
brief_description:
"TOR Occupancy; Any",
public_description:
Some("For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent \'filters\' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select \'MISS_OPC_MATCH\' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); All valid TOR entries. This includes requests that reside in the TOR for a short time, such as LLC Hits that do not need to snoop cores or requests that get rejected and have to be retried through one of the ingress queues. The TOR is more commonly a bottleneck in skews with smaller core counts, where the ratio of RTIDs to TOR entries is larger. Note that there are reserved TOR entries for various request types, so it is possible that a given request type be blocked with an occupancy that is less than 20. Also note that generally requests will not be able to arbitrate into the TOR pipeline if there are no available TOR slots."),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_C_SBO_CREDITS_ACQUIRED.AD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(61),
umask:
Tuple::One(1),
event_name:
"UNC_C_SBO_CREDITS_ACQUIRED.AD",
brief_description:
"SBo Credits Acquired; For AD Ring",
public_description:
Some("Number of Sbo credits acquired in a given cycle, per ring. Each Cbo is assigned an Sbo it can communicate with."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_C_RxR_IRQ_RETRY.ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(50),
umask:
Tuple::One(1),
event_name:
"UNC_C_RxR_IRQ_RETRY.ANY",
brief_description:
"Ingress Request Queue Rejects; Any Reject",
public_description:
Some("Counts the number of IRQ retries that occur. Requests from the IRQ are retried if they are rejected from the TOR pipeline for a variety of reasons. Some of the most common reasons include if the Egress is full, there are no RTIDs, or there is a Physical Address match to another outstanding request."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_H_SBO1_CREDITS_ACQUIRED.BL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(105),
umask:
Tuple::One(2),
event_name:
"UNC_H_SBO1_CREDITS_ACQUIRED.BL",
brief_description:
"SBo1 Credits Acquired; For BL Ring",
public_description:
Some("Number of Sbo 1 credits acquired in a given cycle, per ring."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_C_TOR_INSERTS.OPCODE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(53),
umask:
Tuple::One(1),
event_name:
"UNC_C_TOR_INSERTS.OPCODE",
brief_description:
"TOR Inserts; Opcode Match",
public_description:
Some("Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent \'filters\' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select \'MISS_OPC_MATCH\' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
Some("CBoFilter1[28:20]"),
extsel:
false,}),
("UNC_R3_STALL_NO_SBO_CREDIT.SBO1_AD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(44),
umask:
Tuple::One(2),
event_name:
"UNC_R3_STALL_NO_SBO_CREDIT.SBO1_AD",
brief_description:
"Stall on No Sbo Credits; For SBo1, AD Ring",
public_description:
Some("Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_P_DEMOTIONS_CORE0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(48),
umask:
Tuple::One(0),
event_name:
"UNC_P_DEMOTIONS_CORE0",
brief_description:
"Core C State Demotions",
public_description:
Some("Counts the number of times when a configurable cores had a C-state demotion"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK5.BANK5",
IntelPerformanceCounterDescription{event_code:
Tuple::One(181),
umask:
Tuple::One(5),
event_name:
"UNC_M_RD_CAS_RANK5.BANK5",
brief_description:
"RD_CAS Access to Rank 5; Bank 5",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK6.BANK4",
IntelPerformanceCounterDescription{event_code:
Tuple::One(182),
umask:
Tuple::One(4),
event_name:
"UNC_M_RD_CAS_RANK6.BANK4",
brief_description:
"RD_CAS Access to Rank 6; Bank 4",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_R2_SBO0_CREDITS_ACQUIRED.BL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(40),
umask:
Tuple::One(2),
event_name:
"UNC_R2_SBO0_CREDITS_ACQUIRED.BL",
brief_description:
"SBo0 Credits Acquired; For BL Ring",
public_description:
Some("Number of Sbo 0 credits acquired in a given cycle, per ring."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_H_OSB_EDR.ALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(84),
umask:
Tuple::One(1),
event_name:
"UNC_H_OSB_EDR.ALL",
brief_description:
"OSB Early Data Return; All",
public_description:
Some("Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_SNOOP_CYCLES_NE.LOCAL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(8),
umask:
Tuple::One(1),
event_name:
"UNC_H_SNOOP_CYCLES_NE.LOCAL",
brief_description:
"Cycles with Snoops Outstanding; Local Requests",
public_description:
Some("Counts cycles when one or more snoops are outstanding.; This filter includes only requests coming from the local socket."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK7.BANK3",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(3),
event_name:
"UNC_M_RD_CAS_RANK7.BANK3",
brief_description:
"RD_CAS Access to Rank 7; Bank 3",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxL_CYCLES_NE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(6),
umask:
Tuple::One(0),
event_name:
"UNC_Q_TxL_CYCLES_NE",
brief_description:
"Tx Flit Buffer Cycles not Empty",
public_description:
Some("Counts the number of cycles when the TxQ is not empty. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_H_OSB_EDR.READS_REMOTE_S",
IntelPerformanceCounterDescription{event_code:
Tuple::One(84),
umask:
Tuple::One(16),
event_name:
"UNC_H_OSB_EDR.READS_REMOTE_S",
brief_description:
"OSB Early Data Return; Reads to Remote S",
public_description:
Some("Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_C_RING_AD_USED.DOWN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(27),
umask:
Tuple::One(12),
event_name:
"UNC_C_RING_AD_USED.DOWN",
brief_description:
"AD Ring In Use; Down",
public_description:
Some("Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the \'UP\' direction is on the clockwise ring and \'DN\' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_R3_VN1_CREDITS_USED.HOM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(56),
umask:
Tuple::One(1),
event_name:
"UNC_R3_VN1_CREDITS_USED.HOM",
brief_description:
"VN1 Credit Used; HOM Message Class",
public_description:
Some("Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_AK_INSERTS.SCHED1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(47),
umask:
Tuple::One(2),
event_name:
"UNC_H_TxR_AK_INSERTS.SCHED1",
brief_description:
"AK Egress Allocations; Scheduler 1",
public_description:
Some("AK Egress Allocations; Filter for allocations from scheduler bank 1"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK0.BANK5",
IntelPerformanceCounterDescription{event_code:
Tuple::One(184),
umask:
Tuple::One(5),
event_name:
"UNC_M_WR_CAS_RANK0.BANK5",
brief_description:
"WR_CAS Access to Rank 0; Bank 5",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_S_BOUNCE_CONTROL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(10),
umask:
Tuple::One(0),
event_name:
"UNC_S_BOUNCE_CONTROL",
brief_description:
"Bounce Control",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_C_RxR_IRQ_RETRY.RTID",
IntelPerformanceCounterDescription{event_code:
Tuple::One(50),
umask:
Tuple::One(8),
event_name:
"UNC_C_RxR_IRQ_RETRY.RTID",
brief_description:
"Ingress Request Queue Rejects; No RTIDs",
public_description:
Some("Counts the number of times that requests from the IRQ were retried because there were no RTIDs available. RTIDs are required after a request misses the LLC and needs to send snoops and/or requests to memory. If there are no RTIDs available, requests will queue up in the IRQ and retry until one becomes available. Note that there are multiple RTID pools for the different sockets. There may be cases where the local RTIDs are all used, but requests destined for remote memory can still acquire an RTID because there are remote RTIDs available. This event does not provide any filtering for this case."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK1.BANK3",
IntelPerformanceCounterDescription{event_code:
Tuple::One(177),
umask:
Tuple::One(3),
event_name:
"UNC_M_RD_CAS_RANK1.BANK3",
brief_description:
"RD_CAS Access to Rank 1; Bank 3",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK5.ALLBANKS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(189),
umask:
Tuple::One(16),
event_name:
"UNC_M_WR_CAS_RANK5.ALLBANKS",
brief_description:
"WR_CAS Access to Rank 5; All Banks",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK4.BANK2",
IntelPerformanceCounterDescription{event_code:
Tuple::One(188),
umask:
Tuple::One(2),
event_name:
"UNC_M_WR_CAS_RANK4.BANK2",
brief_description:
"WR_CAS Access to Rank 4; Bank 2",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_C_LLC_VICTIMS.MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(55),
umask:
Tuple::One(16),
event_name:
"UNC_C_LLC_VICTIMS.MISS",
brief_description:
"Lines Victimized",
public_description:
Some("Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(22),
umask:
Tuple::One(2),
event_name:
"UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN1",
brief_description:
"iMC RPQ Credits Empty - Special; Channel 1",
public_description:
Some("Counts the number of cycles when there are no \'special\' credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC\'s RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and \'special\' requests such as ISOCH reads. This count only tracks the \'special\' credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_WMM_TO_RMM.STARVE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(192),
umask:
Tuple::One(2),
event_name:
"UNC_M_WMM_TO_RMM.STARVE",
brief_description:
"Transition from WMM to RMM because of low threshold",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_R2_IIO_CREDIT.PRQ_QPI1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(45),
umask:
Tuple::One(2),
event_name:
"UNC_R2_IIO_CREDIT.PRQ_QPI1",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK1.BANK14",
IntelPerformanceCounterDescription{event_code:
Tuple::One(185),
umask:
Tuple::One(14),
event_name:
"UNC_M_WR_CAS_RANK1.BANK14",
brief_description:
"WR_CAS Access to Rank 1; Bank 14",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_C_RING_AK_USED.ALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(28),
umask:
Tuple::One(15),
event_name:
"UNC_C_RING_AK_USED.ALL",
brief_description:
"AK Ring In Use; All",
public_description:
Some("Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the \'UP\' direction is on the clockwise ring and \'DN\' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_P_MEMORY_PHASE_SHEDDING_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(47),
umask:
Tuple::One(0),
event_name:
"UNC_P_MEMORY_PHASE_SHEDDING_CYCLES",
brief_description:
"Memory Phase Shedding Cycles",
public_description:
Some("Counts the number of cycles that the PCU has triggered memory phase shedding. This is a mode that can be run in the iMC physicals that saves power at the expense of additional latency."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_R3_RING_AK_USED.CCW_EVEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(8),
umask:
Tuple::One(4),
event_name:
"UNC_R3_RING_AK_USED.CCW_EVEN",
brief_description:
"R3 AK Ring in Use; Counterclockwise and Even",
public_description:
Some("Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity."),
counter:
Counter::Programmable(7),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_H_TRACKER_OCCUPANCY.WRITES_REMOTE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(4),
umask:
Tuple::One(32),
event_name:
"UNC_H_TRACKER_OCCUPANCY.WRITES_REMOTE",
brief_description:
"Tracker Occupancy Accumultor; Remote Write Requests",
public_description:
Some("Accumulates the occupancy of the local HA tracker pool in every cycle. This can be used in conjection with the \'not empty\' stat to calculate average queue occupancy or the \'allocations\' stat in order to calculate average queue latency. HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_C_COUNTER0_OCCUPANCY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(31),
umask:
Tuple::One(0),
event_name:
"UNC_C_COUNTER0_OCCUPANCY",
brief_description:
"Counter 0 Occupancy",
public_description:
Some("Since occupancy counts can only be captured in the Cbo\'s 0 counter, this event allows a user to capture occupancy related information by filtering the Cb0 occupancy count captured in Counter 0. The filtering available is found in the control register - threshold, invert and edge detect. E.g. setting threshold to 1 can effectively monitor how many cycles the monitored queue has an entry."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_R2_RING_AK_USED.CCW_EVEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(8),
umask:
Tuple::One(4),
event_name:
"UNC_R2_RING_AK_USED.CCW_EVEN",
brief_description:
"R2 AK Ring in Use; Counterclockwise and Even",
public_description:
Some("Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_R2_RING_IV_USED.CW",
IntelPerformanceCounterDescription{event_code:
Tuple::One(10),
umask:
Tuple::One(3),
event_name:
"UNC_R2_RING_IV_USED.CW",
brief_description:
"R2 IV Ring in Use; Clockwise",
public_description:
Some("Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_R3_VN0_CREDITS_USED.HOM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(54),
umask:
Tuple::One(1),
event_name:
"UNC_R3_VN0_CREDITS_USED.HOM",
brief_description:
"VN0 Credit Used; HOM Message Class",
public_description:
Some("Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_FLITS_G2.NCB_DATA",
IntelPerformanceCounterDescription{event_code:
Tuple::One(3),
umask:
Tuple::One(4),
event_name:
"UNC_Q_RxL_FLITS_G2.NCB_DATA",
brief_description:
"Flits Received - Group 2; Non-Coherent data Rx Flits",
public_description:
Some("Counts the number of flits received from the QPI Link. This is one of three \'groups\' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each \'flit\' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four \'fits\', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI \'speed\' (for example, 8.0 GT/s), the \'transfers\' here refer to \'fits\'. Therefore, in L0, the system will transfer 1 \'flit\' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as \'data\' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual \'data\' and an additional 16 bits of other information. To calculate \'data\' bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass data flits. These flits are generally used to transmit non-coherent data across QPI. This does not include a count of the DRS (coherent) data flits. This only counts the data flits, not the NCB headers."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_R2_TxR_NACK_CW.UP_AK",
IntelPerformanceCounterDescription{event_code:
Tuple::One(38),
umask:
Tuple::One(32),
event_name:
"UNC_R2_TxR_NACK_CW.UP_AK",
brief_description:
"Egress CCW NACK; BL CW",
public_description:
Some("AD Clockwise Egress Queue"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_C_RING_AD_USED.UP_EVEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(27),
umask:
Tuple::One(1),
event_name:
"UNC_C_RING_AD_USED.UP_EVEN",
brief_description:
"AD Ring In Use; Up and Even",
public_description:
Some("Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the \'UP\' direction is on the clockwise ring and \'DN\' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_REMOTE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(114),
umask:
Tuple::One(16),
event_name:
"UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_REMOTE",
brief_description:
"Accumulates Number of PV bits set on HitMe Cache Hits; op is RspIFwd or RspIFwdWb for a remote request",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_R3_RxR_INSERTS_VN1.HOM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(21),
umask:
Tuple::One(1),
event_name:
"UNC_R3_RxR_INSERTS_VN1.HOM",
brief_description:
"VN1 Ingress Allocations; HOM",
public_description:
Some("Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_C_TOR_INSERTS.MISS_REMOTE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(53),
umask:
Tuple::One(138),
event_name:
"UNC_C_TOR_INSERTS.MISS_REMOTE",
brief_description:
"TOR Inserts; Misses to Remote Memory",
public_description:
Some("Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent \'filters\' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select \'MISS_OPC_MATCH\' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that are satisifed by remote caches or remote memory."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_R3_SBO1_CREDITS_ACQUIRED.AD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(41),
umask:
Tuple::One(1),
event_name:
"UNC_R3_SBO1_CREDITS_ACQUIRED.AD",
brief_description:
"SBo1 Credits Acquired; For AD Ring",
public_description:
Some("Number of Sbo 1 credits acquired in a given cycle, per ring."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_H_IOT_CTS_EAST_LO.CTS1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(100),
umask:
Tuple::One(2),
event_name:
"UNC_H_IOT_CTS_EAST_LO.CTS1",
brief_description:
"IOT Common Trigger Sequencer - Lo",
public_description:
Some("Debug Mask/Match Tie-Ins"),
counter:
Counter::Programmable(7),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_P_CORE15_TRANSITION_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(111),
umask:
Tuple::One(0),
event_name:
"UNC_P_CORE15_TRANSITION_CYCLES",
brief_description:
"Core C State Transition Cycles",
public_description:
Some("Number of cycles spent performing core C state transitions. There is one event per core."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_C_RING_SINK_STARVED.BL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(6),
umask:
Tuple::One(4),
event_name:
"UNC_C_RING_SINK_STARVED.BL",
brief_description:
"BL",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_H_SNP_RESP_RECV_LOCAL.RSPxWB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(96),
umask:
Tuple::One(16),
event_name:
"UNC_H_SNP_RESP_RECV_LOCAL.RSPxWB",
brief_description:
"Snoop Responses Received Local; Rsp*WB",
public_description:
Some("Number of snoop responses received for a Local request; Filters for a snoop response of RspIWB or RspSWB. This is returned when a non-RFO request hits in M state. Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured. InvItoE transactions will also return RspIWB because they must acquire ownership."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_C_FAST_ASSERTED",
IntelPerformanceCounterDescription{event_code:
Tuple::One(9),
umask:
Tuple::One(0),
event_name:
"UNC_C_FAST_ASSERTED",
brief_description:
"FaST wire asserted",
public_description:
Some("Counts the number of cycles either the local distress or incoming distress signals are asserted. Incoming distress includes both up and dn."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_R3_RxR_CYCLES_NE_VN1.NCS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(20),
umask:
Tuple::One(32),
event_name:
"UNC_R3_RxR_CYCLES_NE_VN1.NCS",
brief_description:
"VN1 Ingress Cycles Not Empty; NCS",
public_description:
Some("Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_P_PKG_RESIDENCY_C7_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(46),
umask:
Tuple::One(0),
event_name:
"UNC_P_PKG_RESIDENCY_C7_CYCLES",
brief_description:
"Package C7 State Residency",
public_description:
Some("Counts the number of cycles when the package was in C7. This event can be used in conjunction with edge detect to count C7 entrances (or exits using invert). Residency events do not include transition times."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_R3_VN0_CREDITS_USED.NCB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(54),
umask:
Tuple::One(16),
event_name:
"UNC_R3_VN0_CREDITS_USED.NCB",
brief_description:
"VN0 Credit Used; NCB Message Class",
public_description:
Some("Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK4.BANK10",
IntelPerformanceCounterDescription{event_code:
Tuple::One(188),
umask:
Tuple::One(10),
event_name:
"UNC_M_WR_CAS_RANK4.BANK10",
brief_description:
"WR_CAS Access to Rank 4; Bank 10",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK7.BANK13",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(13),
event_name:
"UNC_M_RD_CAS_RANK7.BANK13",
brief_description:
"RD_CAS Access to Rank 7; Bank 13",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_C_QLRU.VICTIM_NON_ZERO",
IntelPerformanceCounterDescription{event_code:
Tuple::One(60),
umask:
Tuple::One(32),
event_name:
"UNC_C_QLRU.VICTIM_NON_ZERO",
brief_description:
"LRU Queue; Non-0 Aged Victim",
public_description:
Some("How often we picked a victim that had a non-zero age"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_P_CORE13_TRANSITION_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(109),
umask:
Tuple::One(0),
event_name:
"UNC_P_CORE13_TRANSITION_CYCLES",
brief_description:
"Core C State Transition Cycles",
public_description:
Some("Number of cycles spent performing core C state transitions. There is one event per core."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_P_CORE0_TRANSITION_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(96),
umask:
Tuple::One(0),
event_name:
"UNC_P_CORE0_TRANSITION_CYCLES",
brief_description:
"Core C State Transition Cycles",
public_description:
Some("Number of cycles spent performing core C state transitions. There is one event per core."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_I_SNOOP_RESP.SNPINV",
IntelPerformanceCounterDescription{event_code:
Tuple::One(23),
umask:
Tuple::One(64),
event_name:
"UNC_I_SNOOP_RESP.SNPINV",
brief_description:
"Snoop Responses; SnpInv",
public_description:
None,
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK6.BANK15",
IntelPerformanceCounterDescription{event_code:
Tuple::One(182),
umask:
Tuple::One(15),
event_name:
"UNC_M_RD_CAS_RANK6.BANK15",
brief_description:
"RD_CAS Access to Rank 6; Bank 15",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_P_DEMOTIONS_CORE11",
IntelPerformanceCounterDescription{event_code:
Tuple::One(59),
umask:
Tuple::One(0),
event_name:
"UNC_P_DEMOTIONS_CORE11",
brief_description:
"Core C State Demotions",
public_description:
Some("Counts the number of times when a configurable cores had a C-state demotion"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_C_RING_AD_USED.DOWN_EVEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(27),
umask:
Tuple::One(4),
event_name:
"UNC_C_RING_AD_USED.DOWN_EVEN",
brief_description:
"AD Ring In Use; Down and Even",
public_description:
Some("Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the \'UP\' direction is on the clockwise ring and \'DN\' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK6.BANK8",
IntelPerformanceCounterDescription{event_code:
Tuple::One(190),
umask:
Tuple::One(8),
event_name:
"UNC_M_WR_CAS_RANK6.BANK8",
brief_description:
"WR_CAS Access to Rank 6; Bank 8",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_R3_STALL_NO_SBO_CREDIT.SBO0_BL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(44),
umask:
Tuple::One(4),
event_name:
"UNC_R3_STALL_NO_SBO_CREDIT.SBO0_BL",
brief_description:
"Stall on No Sbo Credits; For SBo0, BL Ring",
public_description:
Some("Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_S_RING_BOUNCES.IV_CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(5),
umask:
Tuple::One(8),
event_name:
"UNC_S_RING_BOUNCES.IV_CORE",
brief_description:
"Number of LLC responses that bounced on the Ring.; Snoops of processor\'s cache.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_R3_VNA_CREDITS_REJECT.HOM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(52),
umask:
Tuple::One(1),
event_name:
"UNC_R3_VNA_CREDITS_REJECT.HOM",
brief_description:
"VNA Credit Reject; HOM Message Class",
public_description:
Some("Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK1.BANKG3",
IntelPerformanceCounterDescription{event_code:
Tuple::One(177),
umask:
Tuple::One(20),
event_name:
"UNC_M_RD_CAS_RANK1.BANKG3",
brief_description:
"RD_CAS Access to Rank 1; Bank Group 3 (Banks 12-15)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK5.BANK12",
IntelPerformanceCounterDescription{event_code:
Tuple::One(181),
umask:
Tuple::One(12),
event_name:
"UNC_M_RD_CAS_RANK5.BANK12",
brief_description:
"RD_CAS Access to Rank 5; Bank 12",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_H_IMC_WRITES.FULL_ISOCH",
IntelPerformanceCounterDescription{event_code:
Tuple::One(26),
umask:
Tuple::One(4),
event_name:
"UNC_H_IMC_WRITES.FULL_ISOCH",
brief_description:
"HA to iMC Full Line Writes Issued; ISOCH Full Line",
public_description:
Some("Counts the total number of full line writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_R3_VN1_CREDITS_REJECT.DRS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(57),
umask:
Tuple::One(8),
event_name:
"UNC_R3_VN1_CREDITS_REJECT.DRS",
brief_description:
"VN1 Credit Acquisition Failed on DRS; DRS Message Class",
public_description:
Some("Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_C_LLC_VICTIMS.M_STATE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(55),
umask:
Tuple::One(1),
event_name:
"UNC_C_LLC_VICTIMS.M_STATE",
brief_description:
"Lines Victimized; Lines in M state",
public_description:
Some("Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_I_COHERENT_OPS.PCIRDCUR",
IntelPerformanceCounterDescription{event_code:
Tuple::One(19),
umask:
Tuple::One(1),
event_name:
"UNC_I_COHERENT_OPS.PCIRDCUR",
brief_description:
"Coherent Ops; PCIRdCur",
public_description:
Some("Counts the number of coherency related operations servied by the IRP"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(34),
umask:
Tuple::One(2),
event_name:
"UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI1",
brief_description:
"Cycles without QPI Ingress Credits; AD to QPI Link 1",
public_description:
Some("Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent. This can be filtered by the different credit pools and the different links."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_HITME_LOOKUP.RSPFWDI_REMOTE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(112),
umask:
Tuple::One(16),
event_name:
"UNC_H_HITME_LOOKUP.RSPFWDI_REMOTE",
brief_description:
"Counts Number of times HitMe Cache is accessed; op is RspIFwd or RspIFwdWb for a remote request",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK5.BANKG2",
IntelPerformanceCounterDescription{event_code:
Tuple::One(181),
umask:
Tuple::One(19),
event_name:
"UNC_M_RD_CAS_RANK5.BANKG2",
brief_description:
"RD_CAS Access to Rank 5; Bank Group 2 (Banks 8-11)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_C_LLC_LOOKUP.WRITE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(52),
umask:
Tuple::One(5),
event_name:
"UNC_C_LLC_LOOKUP.WRITE",
brief_description:
"Cache Lookups; Write Requests",
public_description:
Some("Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Writeback transactions from L2 to the LLC This includes all write transactions -- both Cachable and UC."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
Some("CBoFilter0[23:17]"),
extsel:
false,}),
("UNC_P_DEMOTIONS_CORE13",
IntelPerformanceCounterDescription{event_code:
Tuple::One(61),
umask:
Tuple::One(0),
event_name:
"UNC_P_DEMOTIONS_CORE13",
brief_description:
"Core C State Demotions",
public_description:
Some("Counts the number of times when a configurable cores had a C-state demotion"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK6.BANKG3",
IntelPerformanceCounterDescription{event_code:
Tuple::One(182),
umask:
Tuple::One(20),
event_name:
"UNC_M_RD_CAS_RANK6.BANKG3",
brief_description:
"RD_CAS Access to Rank 6; Bank Group 3 (Banks 12-15)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_C_LLC_VICTIMS.I_STATE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(55),
umask:
Tuple::One(4),
event_name:
"UNC_C_LLC_VICTIMS.I_STATE",
brief_description:
"Lines Victimized; Lines in S State",
public_description:
Some("Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_H_ADDR_OPC_MATCH.FILT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(32),
umask:
Tuple::One(3),
event_name:
"UNC_H_ADDR_OPC_MATCH.FILT",
brief_description:
"QPI Address/Opcode Match; Address & Opcode Match",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
Some("HA_AddrMatch0[31:6], HA_AddrMatch1[13:0], HA_OpcodeMatch[5:0]"),
extsel:
false,}),
("UNC_S_RING_AD_USED.UP_EVEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(27),
umask:
Tuple::One(1),
event_name:
"UNC_S_RING_AD_USED.UP_EVEN",
brief_description:
"AD Ring In Use; Up and Even",
public_description:
Some("Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the \'UP\' direction is on the clockwise ring and \'DN\' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_S_RxR_BYPASS.AK",
IntelPerformanceCounterDescription{event_code:
Tuple::One(18),
umask:
Tuple::One(16),
event_name:
"UNC_S_RxR_BYPASS.AK",
brief_description:
"Bypass; AK",
public_description:
Some("Bypass the Sbo Ingress."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK1.BANK4",
IntelPerformanceCounterDescription{event_code:
Tuple::One(177),
umask:
Tuple::One(4),
event_name:
"UNC_M_RD_CAS_RANK1.BANK4",
brief_description:
"RD_CAS Access to Rank 1; Bank 4",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_R3_TxR_NACK.UP_AK",
IntelPerformanceCounterDescription{event_code:
Tuple::One(38),
umask:
Tuple::One(32),
event_name:
"UNC_R3_TxR_NACK.UP_AK",
brief_description:
"Egress CCW NACK; BL CW",
public_description:
Some("AD Clockwise Egress Queue"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_BL_CYCLES_FULL.SCHED0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(54),
umask:
Tuple::One(1),
event_name:
"UNC_H_TxR_BL_CYCLES_FULL.SCHED0",
brief_description:
"BL Egress Full; Scheduler 0",
public_description:
Some("BL Egress Full; Filter for cycles full from scheduler bank 0"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_C_TxR_ADS_USED.AD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(4),
umask:
Tuple::One(1),
event_name:
"UNC_C_TxR_ADS_USED.AD",
brief_description:
"Onto AD Ring",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK4.BANK8",
IntelPerformanceCounterDescription{event_code:
Tuple::One(188),
umask:
Tuple::One(8),
event_name:
"UNC_M_WR_CAS_RANK4.BANK8",
brief_description:
"WR_CAS Access to Rank 4; Bank 8",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_CAS_COUNT.RD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(4),
umask:
Tuple::One(3),
event_name:
"UNC_M_CAS_COUNT.RD",
brief_description:
"DRAM RD_CAS and WR_CAS Commands.; All DRAM Reads (RD_CAS + Underfills)",
public_description:
Some("DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Read CAS commands issued on this channel (including underfills)."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_CRC_ERRORS.NORMAL_OP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(3),
umask:
Tuple::One(2),
event_name:
"UNC_Q_RxL_CRC_ERRORS.NORMAL_OP",
brief_description:
"CRC Errors Detected; Normal Operations",
public_description:
Some("Number of CRC errors detected in the QPI Agent. Each QPI flit incorporates 8 bits of CRC for error detection. This counts the number of flits where the CRC was able to detect an error. After an error has been detected, the QPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it).; CRC errors detected during normal operation."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO5",
IntelPerformanceCounterDescription{event_code:
Tuple::One(34),
umask:
Tuple::One(32),
event_name:
"UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO5",
brief_description:
"CBox AD Credits Empty",
public_description:
Some("No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 5"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_CYCLES_NE_NCB.VN0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(16),
umask:
Tuple::One(1),
event_name:
"UNC_Q_RxL_CYCLES_NE_NCB.VN0",
brief_description:
"RxQ Cycles Not Empty - NCB; for VN0",
public_description:
Some("Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NCB flits only."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_Q_VNA_CREDIT_RETURN_OCCUPANCY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(27),
umask:
Tuple::One(0),
event_name:
"UNC_Q_VNA_CREDIT_RETURN_OCCUPANCY",
brief_description:
"VNA Credits Pending Return - Occupancy",
public_description:
Some("Number of VNA credits in the Rx side that are waitng to be returned back across the link."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_U_U2C_EVENTS.MONITOR_T1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(67),
umask:
Tuple::One(2),
event_name:
"UNC_U_U2C_EVENTS.MONITOR_T1",
brief_description:
"Monitor Sent to T0; Monitor T1",
public_description:
Some("Events coming from Uncore can be sent to one or all cores; Filter by core"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("UBOX"),
filter:
None,
extsel:
false,}),
("UNC_S_RxR_BYPASS.IV",
IntelPerformanceCounterDescription{event_code:
Tuple::One(18),
umask:
Tuple::One(32),
event_name:
"UNC_S_RxR_BYPASS.IV",
brief_description:
"Bypass; IV",
public_description:
Some("Bypass the Sbo Ingress."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_Q_L1_POWER_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(18),
umask:
Tuple::One(0),
event_name:
"UNC_Q_L1_POWER_CYCLES",
brief_description:
"Cycles in L1",
public_description:
Some("Number of QPI qfclk cycles spent in L1 power mode. L1 is a mode that totally shuts down a QPI link. Use edge detect to count the number of instances when the QPI link entered L1. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. Because L1 totally shuts down the link, it takes a good amount of time to exit this mode."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_I_RxR_BL_NCB_CYCLES_FULL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(5),
umask:
Tuple::One(0),
event_name:
"UNC_I_RxR_BL_NCB_CYCLES_FULL",
brief_description:
"tbd",
public_description:
Some("Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_I_RxR_BL_NCS_INSERTS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(3),
umask:
Tuple::One(0),
event_name:
"UNC_I_RxR_BL_NCS_INSERTS",
brief_description:
"BL Ingress Occupancy - NCS",
public_description:
Some("Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_S_RxR_OCCUPANCY.BL_BNC",
IntelPerformanceCounterDescription{event_code:
Tuple::One(17),
umask:
Tuple::One(8),
event_name:
"UNC_S_RxR_OCCUPANCY.BL_BNC",
brief_description:
"Ingress Occupancy; BL - Bounces",
public_description:
Some("Occupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_C_RING_AK_USED.DOWN_EVEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(28),
umask:
Tuple::One(4),
event_name:
"UNC_C_RING_AK_USED.DOWN_EVEN",
brief_description:
"AK Ring In Use; Down and Even",
public_description:
Some("Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the \'UP\' direction is on the clockwise ring and \'DN\' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_M_DRAM_REFRESH.PANIC",
IntelPerformanceCounterDescription{event_code:
Tuple::One(5),
umask:
Tuple::One(2),
event_name:
"UNC_M_DRAM_REFRESH.PANIC",
brief_description:
"Number of DRAM Refreshes Issued",
public_description:
Some("Counts the number of refreshes issued."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_H_OSB.INVITOE_LOCAL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(83),
umask:
Tuple::One(4),
event_name:
"UNC_H_OSB.INVITOE_LOCAL",
brief_description:
"OSB Snoop Broadcast; Local InvItoE",
public_description:
Some("Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK1.BANK9",
IntelPerformanceCounterDescription{event_code:
Tuple::One(177),
umask:
Tuple::One(9),
event_name:
"UNC_M_RD_CAS_RANK1.BANK9",
brief_description:
"RD_CAS Access to Rank 1; Bank 9",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_I_CACHE_TOTAL_OCCUPANCY.SOURCE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(18),
umask:
Tuple::One(2),
event_name:
"UNC_I_CACHE_TOTAL_OCCUPANCY.SOURCE",
brief_description:
"Total Write Cache Occupancy; Select Source",
public_description:
Some("Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register. This register allows one to select one specific queue. It is not possible to monitor multiple queues at a time."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_S_RING_BL_USED.UP_EVEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(29),
umask:
Tuple::One(1),
event_name:
"UNC_S_RING_BL_USED.UP_EVEN",
brief_description:
"BL Ring in Use; Up and Even",
public_description:
Some("Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the \'UP\' direction is on the clockwise ring and \'DN\' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_C_RING_AK_USED.UP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(28),
umask:
Tuple::One(3),
event_name:
"UNC_C_RING_AK_USED.UP",
brief_description:
"AK Ring In Use; Up",
public_description:
Some("Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the \'UP\' direction is on the clockwise ring and \'DN\' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_H_RING_AK_USED.CW_EVEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(63),
umask:
Tuple::One(1),
event_name:
"UNC_H_RING_AK_USED.CW_EVEN",
brief_description:
"HA AK Ring in Use; Clockwise and Even",
public_description:
Some("Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_C_RxR_ISMQ_RETRY.NID",
IntelPerformanceCounterDescription{event_code:
Tuple::One(51),
umask:
Tuple::One(64),
event_name:
"UNC_C_RxR_ISMQ_RETRY.NID",
brief_description:
"ISMQ Retries",
public_description:
Some("Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Qualify one of the other subevents by a given RTID destination NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER1.nid."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
Some("CBoFilter1[15:0]"),
extsel:
false,}),
("UNC_M_WR_CAS_RANK0.BANK4",
IntelPerformanceCounterDescription{event_code:
Tuple::One(184),
umask:
Tuple::One(4),
event_name:
"UNC_M_WR_CAS_RANK0.BANK4",
brief_description:
"WR_CAS Access to Rank 0; Bank 4",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_H_HITME_LOOKUP.HOM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(112),
umask:
Tuple::One(15),
event_name:
"UNC_H_HITME_LOOKUP.HOM",
brief_description:
"Counts Number of times HitMe Cache is accessed; HOM Requests",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_RING_AD_USED.CW",
IntelPerformanceCounterDescription{event_code:
Tuple::One(62),
umask:
Tuple::One(3),
event_name:
"UNC_H_RING_AD_USED.CW",
brief_description:
"HA AD Ring in Use; Clockwise",
public_description:
Some("Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_R3_VNA_CREDITS_ACQUIRED.AD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(51),
umask:
Tuple::One(1),
event_name:
"UNC_R3_VNA_CREDITS_ACQUIRED.AD",
brief_description:
"VNA credit Acquisitions; HOM Message Class",
public_description:
Some("Number of QPI VNA Credit acquisitions. This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder. VNA credits are used by all message classes in order to communicate across QPI. If a packet is unable to acquire credits, it will then attempt to use credts from the VN0 pool. Note that a single packet may require multiple flit buffers (i.e. when data is being transfered). Therefore, this event will increment by the number of credits acquired in each cycle. Filtering based on message class is not provided. One can count the number of packets transfered in a given message class using an qfclk event.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_I_TRANSACTIONS.WR_PREF",
IntelPerformanceCounterDescription{event_code:
Tuple::One(22),
umask:
Tuple::One(8),
event_name:
"UNC_I_TRANSACTIONS.WR_PREF",
brief_description:
"Inbound Transaction Count; Write Prefetches",
public_description:
Some("Counts the number of \'Inbound\' transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of write prefetches."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK1.BANK12",
IntelPerformanceCounterDescription{event_code:
Tuple::One(177),
umask:
Tuple::One(12),
event_name:
"UNC_M_RD_CAS_RANK1.BANK12",
brief_description:
"RD_CAS Access to Rank 1; Bank 12",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK0.BANK15",
IntelPerformanceCounterDescription{event_code:
Tuple::One(176),
umask:
Tuple::One(15),
event_name:
"UNC_M_RD_CAS_RANK0.BANK15",
brief_description:
"RD_CAS Access to Rank 0; Bank 15",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK6.BANK1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(190),
umask:
Tuple::One(1),
event_name:
"UNC_M_WR_CAS_RANK6.BANK1",
brief_description:
"WR_CAS Access to Rank 6; Bank 1",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_FLITS_G1.DRS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(2),
umask:
Tuple::One(24),
event_name:
"UNC_Q_RxL_FLITS_G1.DRS",
brief_description:
"Flits Received - Group 1; DRS Flits (both Header and Data)",
public_description:
Some("Counts the number of flits received from the QPI Link. This is one of three \'groups\' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each \'flit\' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four \'fits\', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI \'speed\' (for example, 8.0 GT/s), the \'transfers\' here refer to \'fits\'. Therefore, in L0, the system will transfer 1 \'flit\' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as \'data\' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual \'data\' and an additional 16 bits of other information. To calculate \'data\' bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits received over the NCB channel which transmits non-coherent data."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_H_SNP_RESP_RECV_LOCAL.RSPIFWD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(96),
umask:
Tuple::One(4),
event_name:
"UNC_H_SNP_RESP_RECV_LOCAL.RSPIFWD",
brief_description:
"Snoop Responses Received Local; RspIFwd",
public_description:
Some("Number of snoop responses received for a Local request; Filters for snoop responses of RspIFwd. This is returned when a remote caching agent forwards data and the requesting agent is able to acquire the data in E or M states. This is commonly returned with RFO transactions. It can be either a HitM or a HitFE."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_C_TOR_INSERTS.MISS_OPCODE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(53),
umask:
Tuple::One(3),
event_name:
"UNC_C_TOR_INSERTS.MISS_OPCODE",
brief_description:
"TOR Inserts; Miss Opcode Match",
public_description:
Some("Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent \'filters\' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select \'MISS_OPC_MATCH\' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
Some("CBoFilter1[28:20]"),
extsel:
false,}),
("UNC_C_SBO_CREDITS_ACQUIRED.BL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(61),
umask:
Tuple::One(2),
event_name:
"UNC_C_SBO_CREDITS_ACQUIRED.BL",
brief_description:
"SBo Credits Acquired; For BL Ring",
public_description:
Some("Number of Sbo credits acquired in a given cycle, per ring. Each Cbo is assigned an Sbo it can communicate with."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_S_RxR_OCCUPANCY.AD_BNC",
IntelPerformanceCounterDescription{event_code:
Tuple::One(17),
umask:
Tuple::One(2),
event_name:
"UNC_S_RxR_OCCUPANCY.AD_BNC",
brief_description:
"Ingress Occupancy; AD - Bounces",
public_description:
Some("Occupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_R2_RING_AK_BOUNCES.DN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(18),
umask:
Tuple::One(2),
event_name:
"UNC_R2_RING_AK_BOUNCES.DN",
brief_description:
"AK Ingress Bounced; Dn",
public_description:
Some("Counts the number of times when a request destined for the AK ingress bounced."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK5.BANK9",
IntelPerformanceCounterDescription{event_code:
Tuple::One(189),
umask:
Tuple::One(9),
event_name:
"UNC_M_WR_CAS_RANK5.BANK9",
brief_description:
"WR_CAS Access to Rank 5; Bank 9",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_P_CORE7_TRANSITION_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(103),
umask:
Tuple::One(0),
event_name:
"UNC_P_CORE7_TRANSITION_CYCLES",
brief_description:
"Core C State Transition Cycles",
public_description:
Some("Number of cycles spent performing core C state transitions. There is one event per core."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_BL_INSERTS.ALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(51),
umask:
Tuple::One(3),
event_name:
"UNC_H_TxR_BL_INSERTS.ALL",
brief_description:
"BL Egress Allocations; All",
public_description:
Some("BL Egress Allocations; Allocations from both schedulers"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK5.BANK12",
IntelPerformanceCounterDescription{event_code:
Tuple::One(189),
umask:
Tuple::One(12),
event_name:
"UNC_M_WR_CAS_RANK5.BANK12",
brief_description:
"WR_CAS Access to Rank 5; Bank 12",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(53),
umask:
Tuple::One(35),
event_name:
"UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE",
brief_description:
"TOR Inserts; Misses to Local Memory - Opcode Matched",
public_description:
Some("Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent \'filters\' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select \'MISS_OPC_MATCH\' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions, satisifed by an opcode, inserted into the TOR that are satisifed by locally HOMed memory."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
Some("CBoFilter1[28:20]"),
extsel:
false,}),
("UNC_M_WR_CAS_RANK0.BANK0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(184),
umask:
Tuple::One(0),
event_name:
"UNC_M_WR_CAS_RANK0.BANK0",
brief_description:
"WR_CAS Access to Rank 0; Bank 0",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_R3_IOT_CTS_HI.CTS2",
IntelPerformanceCounterDescription{event_code:
Tuple::One(13),
umask:
Tuple::One(1),
event_name:
"UNC_R3_IOT_CTS_HI.CTS2",
brief_description:
"IOT Common Trigger Sequencer - Hi",
public_description:
Some("Debug Mask/Match Tie-Ins"),
counter:
Counter::Programmable(7),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_S_CLOCKTICKS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(0),
umask:
Tuple::One(0),
event_name:
"UNC_S_CLOCKTICKS",
brief_description:
"Uncore Clocks",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_H_IMC_WRITES.PARTIAL_ISOCH",
IntelPerformanceCounterDescription{event_code:
Tuple::One(26),
umask:
Tuple::One(8),
event_name:
"UNC_H_IMC_WRITES.PARTIAL_ISOCH",
brief_description:
"HA to iMC Full Line Writes Issued; ISOCH Partial",
public_description:
Some("Counts the total number of full line writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK5.BANK9",
IntelPerformanceCounterDescription{event_code:
Tuple::One(181),
umask:
Tuple::One(9),
event_name:
"UNC_M_RD_CAS_RANK5.BANK9",
brief_description:
"RD_CAS Access to Rank 5; Bank 9",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_C_RxR_IPQ_RETRY.ADDR_CONFLICT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(49),
umask:
Tuple::One(4),
event_name:
"UNC_C_RxR_IPQ_RETRY.ADDR_CONFLICT",
brief_description:
"Probe Queue Retries; Address Conflict",
public_description:
Some("Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.; Counts the number of times that a request form the IPQ was retried because of a TOR reject from an address conflicts. Address conflicts out of the IPQ should be rare. They will generally only occur if two different sockets are sending requests to the same address at the same time. This is a true \'conflict\' case, unlike the IPQ Address Conflict which is commonly caused by prefetching characteristics."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK7.BANK3",
IntelPerformanceCounterDescription{event_code:
Tuple::One(191),
umask:
Tuple::One(3),
event_name:
"UNC_M_WR_CAS_RANK7.BANK3",
brief_description:
"WR_CAS Access to Rank 7; Bank 3",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_H_HITME_LOOKUP.RSPFWDS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(112),
umask:
Tuple::One(64),
event_name:
"UNC_H_HITME_LOOKUP.RSPFWDS",
brief_description:
"Counts Number of times HitMe Cache is accessed; op is RsSFwd or RspSFwdWb",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_ACT_COUNT.WR",
IntelPerformanceCounterDescription{event_code:
Tuple::One(1),
umask:
Tuple::One(2),
event_name:
"UNC_M_ACT_COUNT.WR",
brief_description:
"DRAM Activate Count; Activate due to Write",
public_description:
Some("Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_R2_STALL_NO_SBO_CREDIT.SBO0_AD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(44),
umask:
Tuple::One(1),
event_name:
"UNC_R2_STALL_NO_SBO_CREDIT.SBO0_AD",
brief_description:
"Stall on No Sbo Credits; For SBo0, AD Ring",
public_description:
Some("Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_PRIO.PANIC",
IntelPerformanceCounterDescription{event_code:
Tuple::One(160),
umask:
Tuple::One(8),
event_name:
"UNC_M_RD_CAS_PRIO.PANIC",
brief_description:
"Read CAS issued with PANIC NON ISOCH priority (starved)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK4.BANKG3",
IntelPerformanceCounterDescription{event_code:
Tuple::One(180),
umask:
Tuple::One(20),
event_name:
"UNC_M_RD_CAS_RANK4.BANKG3",
brief_description:
"RD_CAS Access to Rank 4; Bank Group 3 (Banks 12-15)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_R2_RxR_INSERTS.NCB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(17),
umask:
Tuple::One(16),
event_name:
"UNC_R2_RxR_INSERTS.NCB",
brief_description:
"Ingress Allocations; NCB",
public_description:
Some("Counts the number of allocations into the R2PCIe Ingress. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_H_RING_BL_USED.CW_EVEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(64),
umask:
Tuple::One(1),
event_name:
"UNC_H_RING_BL_USED.CW_EVEN",
brief_description:
"HA BL Ring in Use; Clockwise and Even",
public_description:
Some("Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK7.BANK4",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(4),
event_name:
"UNC_M_RD_CAS_RANK7.BANK4",
brief_description:
"RD_CAS Access to Rank 7; Bank 4",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_I_TRANSACTIONS.ATOMIC",
IntelPerformanceCounterDescription{event_code:
Tuple::One(22),
umask:
Tuple::One(16),
event_name:
"UNC_I_TRANSACTIONS.ATOMIC",
brief_description:
"Inbound Transaction Count; Atomic",
public_description:
Some("Counts the number of \'Inbound\' transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of atomic transactions"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_R3_VN1_CREDITS_REJECT.NDR",
IntelPerformanceCounterDescription{event_code:
Tuple::One(57),
umask:
Tuple::One(4),
event_name:
"UNC_R3_VN1_CREDITS_REJECT.NDR",
brief_description:
"VN1 Credit Acquisition Failed on DRS; NDR Message Class",
public_description:
Some("Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP)."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_C_TOR_OCCUPANCY.NID_MISS_OPCODE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(54),
umask:
Tuple::One(67),
event_name:
"UNC_C_TOR_OCCUPANCY.NID_MISS_OPCODE",
brief_description:
"TOR Occupancy; NID and Opcode Matched Miss",
public_description:
Some("For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent \'filters\' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select \'MISS_OPC_MATCH\' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss requests in the TOR that match a NID and an opcode."),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
Some("CBoFilter1[28:20], CBoFilter1[15:0]"),
extsel:
false,}),
("UNC_H_IOT_BACKPRESSURE.SAT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(97),
umask:
Tuple::One(1),
event_name:
"UNC_H_IOT_BACKPRESSURE.SAT",
brief_description:
"IOT Backpressure",
public_description:
None,
counter:
Counter::Programmable(7),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_C_RING_BL_USED.UP_EVEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(29),
umask:
Tuple::One(1),
event_name:
"UNC_C_RING_BL_USED.UP_EVEN",
brief_description:
"BL Ring in Use; Up and Even",
public_description:
Some("Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the \'UP\' direction is on the clockwise ring and \'DN\' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_H_RING_AK_USED.CCW_EVEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(63),
umask:
Tuple::One(4),
event_name:
"UNC_H_RING_AK_USED.CCW_EVEN",
brief_description:
"HA AK Ring in Use; Counterclockwise and Even",
public_description:
Some("Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_INSERTS_NCS.VN0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(11),
umask:
Tuple::One(1),
event_name:
"UNC_Q_RxL_INSERTS_NCS.VN0",
brief_description:
"Rx Flit Buffer Allocations - NCS; for VN0",
public_description:
Some("Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCS flits."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_C_LLC_VICTIMS.F_STATE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(55),
umask:
Tuple::One(8),
event_name:
"UNC_C_LLC_VICTIMS.F_STATE",
brief_description:
"Lines Victimized",
public_description:
Some("Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_INSERTS_NDR.VN0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(14),
umask:
Tuple::One(1),
event_name:
"UNC_Q_RxL_INSERTS_NDR.VN0",
brief_description:
"Rx Flit Buffer Allocations - NDR; for VN0",
public_description:
Some("Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NDR flits."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_M_RD_CAS_RANK5.BANK4",
IntelPerformanceCounterDescription{event_code:
Tuple::One(181),
umask:
Tuple::One(4),
event_name:
"UNC_M_RD_CAS_RANK5.BANK4",
brief_description:
"RD_CAS Access to Rank 5; Bank 4",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxR_BL_NCB_CREDIT_ACQUIRED.VN0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(43),
umask:
Tuple::One(1),
event_name:
"UNC_Q_TxR_BL_NCB_CREDIT_ACQUIRED.VN0",
brief_description:
"R3QPI Egress Credit Occupancy - NCB; for VN0",
public_description:
Some("Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCB message class to BL Egress."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_H_SNOOPS_RSP_AFTER_DATA.LOCAL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(10),
umask:
Tuple::One(1),
event_name:
"UNC_H_SNOOPS_RSP_AFTER_DATA.LOCAL",
brief_description:
"Data beat the Snoop Responses; Local Requests",
public_description:
Some("Counts the number of reads when the snoop was on the critical path to the data return.; This filter includes only requests coming from the local socket."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_SNOOP_CYCLES_NE.ALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(8),
umask:
Tuple::One(3),
event_name:
"UNC_H_SNOOP_CYCLES_NE.ALL",
brief_description:
"Cycles with Snoops Outstanding; All Requests",
public_description:
Some("Counts cycles when one or more snoops are outstanding.; Tracked for snoops from both local and remote sockets."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_U_FILTER_MATCH.ENABLE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(65),
umask:
Tuple::One(1),
event_name:
"UNC_U_FILTER_MATCH.ENABLE",
brief_description:
"Filter Match",
public_description:
Some("Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("UBOX"),
filter:
Some("UBoxFilter[3:0]"),
extsel:
false,}),
("UNC_S_RING_BOUNCES.AD_CACHE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(5),
umask:
Tuple::One(1),
event_name:
"UNC_S_RING_BOUNCES.AD_CACHE",
brief_description:
"Number of LLC responses that bounced on the Ring.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_C_RxR_IPQ_RETRY.QPI_CREDITS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(49),
umask:
Tuple::One(16),
event_name:
"UNC_C_RxR_IPQ_RETRY.QPI_CREDITS",
brief_description:
"Probe Queue Retries; No QPI Credits",
public_description:
Some("Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK4.BANK4",
IntelPerformanceCounterDescription{event_code:
Tuple::One(188),
umask:
Tuple::One(4),
event_name:
"UNC_M_WR_CAS_RANK4.BANK4",
brief_description:
"WR_CAS Access to Rank 4; Bank 4",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_R2_RING_BL_USED.CW_EVEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(9),
umask:
Tuple::One(1),
event_name:
"UNC_R2_RING_BL_USED.CW_EVEN",
brief_description:
"R2 BL Ring in Use; Clockwise and Even",
public_description:
Some("Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_Q_DIRECT2CORE.FAILURE_RBT_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(19),
umask:
Tuple::One(64),
event_name:
"UNC_Q_DIRECT2CORE.FAILURE_RBT_MISS",
brief_description:
"Direct 2 Core Spawning; Spawn Failure - RBT Miss and Invalid",
public_description:
Some("Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exlusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match and the valid bit was not set although there were enough Egress credits."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_P_FREQ_BAND2_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(13),
umask:
Tuple::One(0),
event_name:
"UNC_P_FREQ_BAND2_CYCLES",
brief_description:
"Frequency Residency",
public_description:
Some("Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter. One can use all four counters with this event, so it is possible to track up to 4 configurable bands. One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
Some("PCUFilter[23:16]"),
extsel:
false,}),
("UNC_M_POWER_CKE_CYCLES.RANK4",
IntelPerformanceCounterDescription{event_code:
Tuple::One(131),
umask:
Tuple::One(16),
event_name:
"UNC_M_POWER_CKE_CYCLES.RANK4",
brief_description:
"CKE_ON_CYCLES by Rank; DIMM ID",
public_description:
Some("Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary)."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK5.BANK11",
IntelPerformanceCounterDescription{event_code:
Tuple::One(181),
umask:
Tuple::One(11),
event_name:
"UNC_M_RD_CAS_RANK5.BANK11",
brief_description:
"RD_CAS Access to Rank 5; Bank 11",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK5.BANK6",
IntelPerformanceCounterDescription{event_code:
Tuple::One(181),
umask:
Tuple::One(6),
event_name:
"UNC_M_RD_CAS_RANK5.BANK6",
brief_description:
"RD_CAS Access to Rank 5; Bank 6",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_C_QLRU.LRU_DECREMENT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(60),
umask:
Tuple::One(16),
event_name:
"UNC_C_QLRU.LRU_DECREMENT",
brief_description:
"LRU Queue; LRU Bits Decremented",
public_description:
Some("How often all LRU bits were decremented by 1"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxR_BL_NCS_CREDIT_OCCUPANCY.VN1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(33),
umask:
Tuple::One(2),
event_name:
"UNC_Q_TxR_BL_NCS_CREDIT_OCCUPANCY.VN1",
brief_description:
"R3QPI Egress Credit Occupancy - BL NCS; for VN1",
public_description:
Some("Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. NCS message class to BL Egress."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_H_TxR_BL.DRS_QPI",
IntelPerformanceCounterDescription{event_code:
Tuple::One(16),
umask:
Tuple::One(4),
event_name:
"UNC_H_TxR_BL.DRS_QPI",
brief_description:
"Outbound DRS Ring Transactions to Cache; Data to QPI",
public_description:
Some("Counts the number of DRS messages sent out on the BL ring. This can be filtered by the destination.; Filter for data being sent to a remote socket over QPI."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_C_RxR_EXT_STARVED.IRQ",
IntelPerformanceCounterDescription{event_code:
Tuple::One(18),
umask:
Tuple::One(1),
event_name:
"UNC_C_RxR_EXT_STARVED.IRQ",
brief_description:
"Ingress Arbiter Blocking Cycles; IPQ",
public_description:
Some("Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues.; IRQ is externally starved and therefore we are blocking the IPQ."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_AK_CYCLES_FULL.SCHED1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(50),
umask:
Tuple::One(2),
event_name:
"UNC_H_TxR_AK_CYCLES_FULL.SCHED1",
brief_description:
"AK Egress Full; Scheduler 1",
public_description:
Some("AK Egress Full; Filter for cycles full from scheduler bank 1"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_FLITS_G1.SNP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(2),
umask:
Tuple::One(1),
event_name:
"UNC_Q_RxL_FLITS_G1.SNP",
brief_description:
"Flits Received - Group 1; SNP Flits",
public_description:
Some("Counts the number of flits received from the QPI Link. This is one of three \'groups\' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each \'flit\' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four \'fits\', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI \'speed\' (for example, 8.0 GT/s), the \'transfers\' here refer to \'fits\'. Therefore, in L0, the system will transfer 1 \'flit\' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as \'data\' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual \'data\' and an additional 16 bits of other information. To calculate \'data\' bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of snoop request flits received over QPI. These requests are contained in the snoop channel. This does not include snoop responses, which are received on the home channel."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_H_TRACKER_PENDING_OCCUPANCY.REMOTE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(5),
umask:
Tuple::One(2),
event_name:
"UNC_H_TRACKER_PENDING_OCCUPANCY.REMOTE",
brief_description:
"Data Pending Occupancy Accumultor; Remote Requests",
public_description:
Some("Accumulates the number of transactions that have data from the memory controller until they get scheduled to the Egress. This can be used to calculate the queuing latency for two things. (1) If the system is waiting for snoops, this will increase. (2) If the system can\'t schedule to the Egress because of either (a) Egress Credits or (b) QPI BL IGR credits for remote requests.; This filter includes only requests coming from remote sockets."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_P_DEMOTIONS_CORE15",
IntelPerformanceCounterDescription{event_code:
Tuple::One(63),
umask:
Tuple::One(0),
event_name:
"UNC_P_DEMOTIONS_CORE15",
brief_description:
"Core C State Demotions",
public_description:
Some("Counts the number of times when a configurable cores had a C-state demotion"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_H_HITME_HIT.RSP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(113),
umask:
Tuple::One(128),
event_name:
"UNC_H_HITME_HIT.RSP",
brief_description:
"Counts Number of Hits in HitMe Cache; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK7.BANK15",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(15),
event_name:
"UNC_M_RD_CAS_RANK7.BANK15",
brief_description:
"RD_CAS Access to Rank 7; Bank 15",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_R3_STALL_NO_SBO_CREDIT.SBO1_BL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(44),
umask:
Tuple::One(8),
event_name:
"UNC_R3_STALL_NO_SBO_CREDIT.SBO1_BL",
brief_description:
"Stall on No Sbo Credits; For SBo1, BL Ring",
public_description:
Some("Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_M_BYP_CMDS.CAS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(161),
umask:
Tuple::One(2),
event_name:
"UNC_M_BYP_CMDS.CAS",
brief_description:
"CAS command issued by 2 cycle bypass",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_H_SNOOP_RESP.RSP_WB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(33),
umask:
Tuple::One(16),
event_name:
"UNC_H_SNOOP_RESP.RSP_WB",
brief_description:
"Snoop Responses Received; Rsp*WB",
public_description:
Some("Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of RspIWB or RspSWB. This is returned when a non-RFO request hits in M state. Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured. InvItoE transactions will also return RspIWB because they must acquire ownership."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_I_COHERENT_OPS.CRD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(19),
umask:
Tuple::One(2),
event_name:
"UNC_I_COHERENT_OPS.CRD",
brief_description:
"Coherent Ops; CRd",
public_description:
Some("Counts the number of coherency related operations servied by the IRP"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_C_LLC_VICTIMS.S_STATE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(55),
umask:
Tuple::One(4),
event_name:
"UNC_C_LLC_VICTIMS.S_STATE",
brief_description:
"Lines in S State",
public_description:
Some("Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_M_DRAM_REFRESH.HIGH",
IntelPerformanceCounterDescription{event_code:
Tuple::One(5),
umask:
Tuple::One(4),
event_name:
"UNC_M_DRAM_REFRESH.HIGH",
brief_description:
"Number of DRAM Refreshes Issued",
public_description:
Some("Counts the number of refreshes issued."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_I_TxR_DATA_INSERTS_NCS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(15),
umask:
Tuple::One(0),
event_name:
"UNC_I_TxR_DATA_INSERTS_NCS",
brief_description:
"Outbound Read Requests",
public_description:
Some("Counts the number of requests issued to the switch (towards the devices)."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(42),
umask:
Tuple::One(1),
event_name:
"UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN0",
brief_description:
"R3QPI Egress Credit Occupancy - DRS; for VN0",
public_description:
Some("Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_M_RD_CAS_RANK1.BANK5",
IntelPerformanceCounterDescription{event_code:
Tuple::One(177),
umask:
Tuple::One(5),
event_name:
"UNC_M_RD_CAS_RANK1.BANK5",
brief_description:
"RD_CAS Access to Rank 1; Bank 5",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_H_STALL_NO_SBO_CREDIT.SBO0_BL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(108),
umask:
Tuple::One(4),
event_name:
"UNC_H_STALL_NO_SBO_CREDIT.SBO0_BL",
brief_description:
"Stall on No Sbo Credits; For SBo0, BL Ring",
public_description:
Some("Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_SNOOP_OCCUPANCY.LOCAL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(9),
umask:
Tuple::One(1),
event_name:
"UNC_H_SNOOP_OCCUPANCY.LOCAL",
brief_description:
"Tracker Snoops Outstanding Accumulator; Local Requests",
public_description:
Some("Accumulates the occupancy of either the local HA tracker pool that have snoops pending in every cycle. This can be used in conjection with the \'not empty\' stat to calculate average queue occupancy or the \'allocations\' stat in order to calculate average queue latency. HA trackers are allocated as soon as a request enters the HA if an HT (HomeTracker) entry is available and this occupancy is decremented when all the snoop responses have returned.; This filter includes only requests coming from the local socket."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_R3_RING_BL_USED.CCW",
IntelPerformanceCounterDescription{event_code:
Tuple::One(9),
umask:
Tuple::One(12),
event_name:
"UNC_R3_RING_BL_USED.CCW",
brief_description:
"R3 BL Ring in Use; Counterclockwise",
public_description:
Some("Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop."),
counter:
Counter::Programmable(7),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_AK_CYCLES_NE.SCHED0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(49),
umask:
Tuple::One(1),
event_name:
"UNC_H_TxR_AK_CYCLES_NE.SCHED0",
brief_description:
"AK Egress Not Empty; Scheduler 0",
public_description:
Some("AK Egress Not Empty; Filter for cycles not empty from scheduler bank 0"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK0.BANK15",
IntelPerformanceCounterDescription{event_code:
Tuple::One(184),
umask:
Tuple::One(15),
event_name:
"UNC_M_WR_CAS_RANK0.BANK15",
brief_description:
"WR_CAS Access to Rank 0; Bank 15",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_C_RxR_IRQ_RETRY.QPI_CREDITS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(50),
umask:
Tuple::One(16),
event_name:
"UNC_C_RxR_IRQ_RETRY.QPI_CREDITS",
brief_description:
"Ingress Request Queue Rejects; No QPI Credits",
public_description:
Some("Number of requests rejects because of lack of QPI Ingress credits. These credits are required in order to send transactions to the QPI agent. Please see the QPI_IGR_CREDITS events for more information."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK4.BANKG1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(188),
umask:
Tuple::One(18),
event_name:
"UNC_M_WR_CAS_RANK4.BANKG1",
brief_description:
"WR_CAS Access to Rank 4; Bank Group 1 (Banks 4-7)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK1.BANKG1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(185),
umask:
Tuple::One(18),
event_name:
"UNC_M_WR_CAS_RANK1.BANKG1",
brief_description:
"WR_CAS Access to Rank 1; Bank Group 1 (Banks 4-7)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_S_RxR_BYPASS.BL_BNC",
IntelPerformanceCounterDescription{event_code:
Tuple::One(18),
umask:
Tuple::One(8),
event_name:
"UNC_S_RxR_BYPASS.BL_BNC",
brief_description:
"Bypass; BL - Bounces",
public_description:
Some("Bypass the Sbo Ingress."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_R3_TxR_NACK.DN_AK",
IntelPerformanceCounterDescription{event_code:
Tuple::One(38),
umask:
Tuple::One(4),
event_name:
"UNC_R3_TxR_NACK.DN_AK",
brief_description:
"Egress CCW NACK; AK CCW",
public_description:
Some("AK CounterClockwise Egress Queue"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_C_RxR_IRQ_RETRY.IIO_CREDITS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(50),
umask:
Tuple::One(32),
event_name:
"UNC_C_RxR_IRQ_RETRY.IIO_CREDITS",
brief_description:
"Ingress Request Queue Rejects; No IIO Credits",
public_description:
Some("Number of times a request attempted to acquire the NCS/NCB credit for sending messages on BL to the IIO. There is a single credit in each CBo that is shared between the NCS and NCB message classes for sending transactions on the BL ring (such as read data) to the IIO."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_C_RxR_INSERTS.PRQ",
IntelPerformanceCounterDescription{event_code:
Tuple::One(19),
umask:
Tuple::One(16),
event_name:
"UNC_C_RxR_INSERTS.PRQ",
brief_description:
"Ingress Allocations; PRQ",
public_description:
Some("Counts number of allocations per cycle into the specified Ingress queue."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_H_IMC_RETRY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(30),
umask:
Tuple::One(0),
event_name:
"UNC_H_IMC_RETRY",
brief_description:
"Retry Events",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_HITME_HIT_PV_BITS_SET.WBMTOI",
IntelPerformanceCounterDescription{event_code:
Tuple::One(114),
umask:
Tuple::One(2),
event_name:
"UNC_H_HITME_HIT_PV_BITS_SET.WBMTOI",
brief_description:
"Accumulates Number of PV bits set on HitMe Cache Hits; op is WbMtoI",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_OSB.CANCELLED",
IntelPerformanceCounterDescription{event_code:
Tuple::One(83),
umask:
Tuple::One(16),
event_name:
"UNC_H_OSB.CANCELLED",
brief_description:
"OSB Snoop Broadcast; Cancelled",
public_description:
Some("Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.; OSB Snoop broadcast cancelled due to D2C or Other. OSB cancel is counted when OSB local read is not allowed even when the transaction in local InItoE. It also counts D2C OSB cancel, but also includes the cases were D2C was not set in the first place for the transaction coming from the ring."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK1.BANK0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(185),
umask:
Tuple::One(0),
event_name:
"UNC_M_WR_CAS_RANK1.BANK0",
brief_description:
"WR_CAS Access to Rank 1; Bank 0",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO7",
IntelPerformanceCounterDescription{event_code:
Tuple::One(34),
umask:
Tuple::One(128),
event_name:
"UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO7",
brief_description:
"CBox AD Credits Empty",
public_description:
Some("No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 7"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK6.BANKG1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(190),
umask:
Tuple::One(18),
event_name:
"UNC_M_WR_CAS_RANK6.BANKG1",
brief_description:
"WR_CAS Access to Rank 6; Bank Group 1 (Banks 4-7)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_H_BT_TO_HT_NOT_ISSUED.WBMDATA_HAZARD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(81),
umask:
Tuple::One(16),
event_name:
"UNC_H_BT_TO_HT_NOT_ISSUED.WBMDATA_HAZARD",
brief_description:
"BT to HT Not Issued; Incoming Data Hazard",
public_description:
Some("Counts the number of cycles when the HA does not issue transaction from BT to HT.; Cycles unable to issue from BT due to incoming BL data hazard"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_P_DEMOTIONS_CORE4",
IntelPerformanceCounterDescription{event_code:
Tuple::One(52),
umask:
Tuple::One(0),
event_name:
"UNC_P_DEMOTIONS_CORE4",
brief_description:
"Core C State Demotions",
public_description:
Some("Counts the number of times when a configurable cores had a C-state demotion"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK0.BANK12",
IntelPerformanceCounterDescription{event_code:
Tuple::One(184),
umask:
Tuple::One(12),
event_name:
"UNC_M_WR_CAS_RANK0.BANK12",
brief_description:
"WR_CAS Access to Rank 0; Bank 12",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_R2_RING_AK_USED.CW_ODD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(8),
umask:
Tuple::One(2),
event_name:
"UNC_R2_RING_AK_USED.CW_ODD",
brief_description:
"R2 AK Ring in Use; Clockwise and Odd",
public_description:
Some("Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK0.BANK9",
IntelPerformanceCounterDescription{event_code:
Tuple::One(184),
umask:
Tuple::One(9),
event_name:
"UNC_M_WR_CAS_RANK0.BANK9",
brief_description:
"WR_CAS Access to Rank 0; Bank 9",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_C_TOR_INSERTS.WB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(53),
umask:
Tuple::One(16),
event_name:
"UNC_C_TOR_INSERTS.WB",
brief_description:
"TOR Inserts; Writebacks",
public_description:
Some("Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent \'filters\' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select \'MISS_OPC_MATCH\' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Write transactions inserted into the TOR. This does not include \'RFO\', but actual operations that contain data being sent from the core."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_S_RING_BL_USED.DOWN_ODD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(29),
umask:
Tuple::One(8),
event_name:
"UNC_S_RING_BL_USED.DOWN_ODD",
brief_description:
"BL Ring in Use; Down and Odd",
public_description:
Some("Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the \'UP\' direction is on the clockwise ring and \'DN\' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_H_ADDR_OPC_MATCH.AK",
IntelPerformanceCounterDescription{event_code:
Tuple::One(32),
umask:
Tuple::One(16),
event_name:
"UNC_H_ADDR_OPC_MATCH.AK",
brief_description:
"QPI Address/Opcode Match; AK Opcodes",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
Some("HA_OpcodeMatch[5:0]"),
extsel:
false,}),
("UNC_M_RD_CAS_RANK4.BANK2",
IntelPerformanceCounterDescription{event_code:
Tuple::One(180),
umask:
Tuple::One(2),
event_name:
"UNC_M_RD_CAS_RANK4.BANK2",
brief_description:
"RD_CAS Access to Rank 4; Bank 2",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_Q_DIRECT2CORE.FAILURE_RBT_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(19),
umask:
Tuple::One(4),
event_name:
"UNC_Q_DIRECT2CORE.FAILURE_RBT_HIT",
brief_description:
"Direct 2 Core Spawning; Spawn Failure - RBT Invalid",
public_description:
Some("Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exlusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the route-back table (RBT) specified that the transaction should not trigger a direct2core tranaction. This is common for IO transactions. There were enough Egress credits and the RBT tag matched but the valid bit was not set."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_H_RING_BL_USED.CW_ODD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(64),
umask:
Tuple::One(2),
event_name:
"UNC_H_RING_BL_USED.CW_ODD",
brief_description:
"HA BL Ring in Use; Clockwise and Odd",
public_description:
Some("Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK6.BANKG3",
IntelPerformanceCounterDescription{event_code:
Tuple::One(190),
umask:
Tuple::One(20),
event_name:
"UNC_M_WR_CAS_RANK6.BANKG3",
brief_description:
"WR_CAS Access to Rank 6; Bank Group 3 (Banks 12-15)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_R3_VN1_CREDITS_USED.DRS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(56),
umask:
Tuple::One(8),
event_name:
"UNC_R3_VN1_CREDITS_USED.DRS",
brief_description:
"VN1 Credit Used; DRS Message Class",
public_description:
Some("Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_M_CAS_COUNT.WR",
IntelPerformanceCounterDescription{event_code:
Tuple::One(4),
umask:
Tuple::One(12),
event_name:
"UNC_M_CAS_COUNT.WR",
brief_description:
"DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (both Modes)",
public_description:
Some("DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Write CAS commands issued on this channel."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_SNP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(46),
umask:
Tuple::One(32),
event_name:
"UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_SNP",
brief_description:
"QPI1 AD Credits Empty",
public_description:
Some("No credits available to send to QPI1 on the AD Ring; VN1 SNP Messages"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_M_RPQ_CYCLES_NE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(17),
umask:
Tuple::One(0),
event_name:
"UNC_M_RPQ_CYCLES_NE",
brief_description:
"Read Pending Queue Not Empty",
public_description:
Some("Counts the number of cycles that the Read Pending Queue is not empty. This can then be used to calculate the average occupancy (in conjunction with the Read Pending Queue Occupancy count). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This filter is to be used in conjunction with the occupancy filter so that one can correctly track the average occupancies for schedulable entries and scheduled requests."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_H_SNOOPS_RSP_AFTER_DATA.REMOTE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(10),
umask:
Tuple::One(2),
event_name:
"UNC_H_SNOOPS_RSP_AFTER_DATA.REMOTE",
brief_description:
"Data beat the Snoop Responses; Remote Requests",
public_description:
Some("Counts the number of reads when the snoop was on the critical path to the data return.; This filter includes only requests coming from remote sockets."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxR_AD_NDR_CREDIT_OCCUPANCY.VN1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(36),
umask:
Tuple::One(2),
event_name:
"UNC_Q_TxR_AD_NDR_CREDIT_OCCUPANCY.VN1",
brief_description:
"R3QPI Egress Credit Occupancy - AD NDR; for VN1",
public_description:
Some("Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for NDR messages on AD."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_M_WR_CAS_RANK0.BANK11",
IntelPerformanceCounterDescription{event_code:
Tuple::One(184),
umask:
Tuple::One(11),
event_name:
"UNC_M_WR_CAS_RANK0.BANK11",
brief_description:
"WR_CAS Access to Rank 0; Bank 11",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_P_CORE12_TRANSITION_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(108),
umask:
Tuple::One(0),
event_name:
"UNC_P_CORE12_TRANSITION_CYCLES",
brief_description:
"Core C State Transition Cycles",
public_description:
Some("Number of cycles spent performing core C state transitions. There is one event per core."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_H_IOT_CTS_EAST_LO.CTS0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(100),
umask:
Tuple::One(1),
event_name:
"UNC_H_IOT_CTS_EAST_LO.CTS0",
brief_description:
"IOT Common Trigger Sequencer - Lo",
public_description:
Some("Debug Mask/Match Tie-Ins"),
counter:
Counter::Programmable(7),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxL_FLITS_G0.NON_DATA",
IntelPerformanceCounterDescription{event_code:
Tuple::One(0),
umask:
Tuple::One(4),
event_name:
"UNC_Q_TxL_FLITS_G0.NON_DATA",
brief_description:
"Flits Transferred - Group 0; Non-Data protocol Tx Flits",
public_description:
Some("Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each \'flit\' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four \'fits\', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI \'speed\' (for example, 8.0 GT/s), the \'transfers\' here refer to \'fits\'. Therefore, in L0, the system will transfer 1 \'flit\' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as \'data\' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual \'data\' and an additional 16 bits of other information. To calculate \'data\' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of non-NULL non-data flits transmitted across QPI. This basically tracks the protocol overhead on the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This includes the header flits for data packets."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_S_TxR_INSERTS.AK",
IntelPerformanceCounterDescription{event_code:
Tuple::One(2),
umask:
Tuple::One(16),
event_name:
"UNC_S_TxR_INSERTS.AK",
brief_description:
"Egress Allocations; AK",
public_description:
Some("Number of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_P_DEMOTIONS_CORE5",
IntelPerformanceCounterDescription{event_code:
Tuple::One(53),
umask:
Tuple::One(0),
event_name:
"UNC_P_DEMOTIONS_CORE5",
brief_description:
"Core C State Demotions",
public_description:
Some("Counts the number of times when a configurable cores had a C-state demotion"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_C_TOR_INSERTS.LOCAL_OPCODE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(53),
umask:
Tuple::One(33),
event_name:
"UNC_C_TOR_INSERTS.LOCAL_OPCODE",
brief_description:
"TOR Inserts; Local Memory - Opcode Matched",
public_description:
Some("Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent \'filters\' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select \'MISS_OPC_MATCH\' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions, satisifed by an opcode, inserted into the TOR that are satisifed by locally HOMed memory."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
Some("CBoFilter1[28:20]"),
extsel:
false,}),
("UNC_I_SNOOP_RESP.HIT_ES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(23),
umask:
Tuple::One(4),
event_name:
"UNC_I_SNOOP_RESP.HIT_ES",
brief_description:
"Snoop Responses; Hit E or S",
public_description:
None,
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxR_BL_NCB_CREDIT_OCCUPANCY.VN1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(32),
umask:
Tuple::One(2),
event_name:
"UNC_Q_TxR_BL_NCB_CREDIT_OCCUPANCY.VN1",
brief_description:
"R3QPI Egress Credit Occupancy - BL NCB; for VN1",
public_description:
Some("Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. NCB message class to BL Egress."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_M_RD_CAS_RANK6.BANK10",
IntelPerformanceCounterDescription{event_code:
Tuple::One(182),
umask:
Tuple::One(10),
event_name:
"UNC_M_RD_CAS_RANK6.BANK10",
brief_description:
"RD_CAS Access to Rank 6; Bank 10",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK0.BANKG1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(184),
umask:
Tuple::One(18),
event_name:
"UNC_M_WR_CAS_RANK0.BANKG1",
brief_description:
"WR_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_R3_RING_BL_USED.CW",
IntelPerformanceCounterDescription{event_code:
Tuple::One(9),
umask:
Tuple::One(3),
event_name:
"UNC_R3_RING_BL_USED.CW",
brief_description:
"R3 BL Ring in Use; Clockwise",
public_description:
Some("Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop."),
counter:
Counter::Programmable(7),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_C_RING_BL_USED.ALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(29),
umask:
Tuple::One(15),
event_name:
"UNC_C_RING_BL_USED.ALL",
brief_description:
"BL Ring in Use; Down",
public_description:
Some("Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the \'UP\' direction is on the clockwise ring and \'DN\' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_H_TAD_REQUESTS_G0.REGION1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(27),
umask:
Tuple::One(2),
event_name:
"UNC_H_TAD_REQUESTS_G0.REGION1",
brief_description:
"HA Requests to a TAD Region - Group 0; TAD Region 1",
public_description:
Some("Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for \'Monroe\' systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 1"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_S_TxR_STARVED.BL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(3),
umask:
Tuple::One(4),
event_name:
"UNC_S_TxR_STARVED.BL",
brief_description:
"Injection Starvation; Onto BL Ring",
public_description:
Some("Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_M_WRONG_MM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(193),
umask:
Tuple::One(0),
event_name:
"UNC_M_WRONG_MM",
brief_description:
"Not getting the requested Major Mode",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_C_RING_AD_USED.ALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(27),
umask:
Tuple::One(15),
event_name:
"UNC_C_RING_AD_USED.ALL",
brief_description:
"AD Ring In Use; All",
public_description:
Some("Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the \'UP\' direction is on the clockwise ring and \'DN\' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_H_IMC_WRITES.PARTIAL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(26),
umask:
Tuple::One(2),
event_name:
"UNC_H_IMC_WRITES.PARTIAL",
brief_description:
"HA to iMC Full Line Writes Issued; Partial Non-ISOCH",
public_description:
Some("Counts the total number of full line writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK6.BANK11",
IntelPerformanceCounterDescription{event_code:
Tuple::One(182),
umask:
Tuple::One(11),
event_name:
"UNC_M_RD_CAS_RANK6.BANK11",
brief_description:
"RD_CAS Access to Rank 6; Bank 11",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_HOM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(33),
umask:
Tuple::One(16),
event_name:
"UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_HOM",
brief_description:
"QPI0 BL Credits Empty",
public_description:
Some("No credits available to send to QPI0 on the BL Ring; VN1 HOM Messages"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_H_ADDR_OPC_MATCH.AD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(32),
umask:
Tuple::One(4),
event_name:
"UNC_H_ADDR_OPC_MATCH.AD",
brief_description:
"QPI Address/Opcode Match; AD Opcodes",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
Some("HA_OpcodeMatch[5:0]"),
extsel:
false,}),
("UNC_S_TxR_OCCUPANCY.IV",
IntelPerformanceCounterDescription{event_code:
Tuple::One(1),
umask:
Tuple::One(32),
event_name:
"UNC_S_TxR_OCCUPANCY.IV",
brief_description:
"Egress Occupancy; IV",
public_description:
Some("Occupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK7.BANKG2",
IntelPerformanceCounterDescription{event_code:
Tuple::One(191),
umask:
Tuple::One(19),
event_name:
"UNC_M_WR_CAS_RANK7.BANKG2",
brief_description:
"WR_CAS Access to Rank 7; Bank Group 2 (Banks 8-11)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_H_SNOOP_RESP.RSPS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(33),
umask:
Tuple::One(2),
event_name:
"UNC_H_SNOOP_RESP.RSPS",
brief_description:
"Snoop Responses Received; RspS",
public_description:
Some("Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoop responses of RspS. RspS is returned when a remote cache has data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E state. No data is sent with S RspS."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_PREEMPTION.RD_PREEMPT_RD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(8),
umask:
Tuple::One(1),
event_name:
"UNC_M_PREEMPTION.RD_PREEMPT_RD",
brief_description:
"Read Preemption Count; Read over Read Preemption",
public_description:
Some("Counts the number of times a read in the iMC preempts another read or write. Generally reads to an open page are issued ahead of requests to closed pages. This improves the page hit rate of the system. However, high priority requests can cause pages of active requests to be closed in order to get them out. This will reduce the latency of the high-priority request at the expense of lower bandwidth and increased overall average latency.; Filter for when a read preempts another read."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxL_FLITS_G0.DATA",
IntelPerformanceCounterDescription{event_code:
Tuple::One(0),
umask:
Tuple::One(2),
event_name:
"UNC_Q_TxL_FLITS_G0.DATA",
brief_description:
"Flits Transferred - Group 0; Data Tx Flits",
public_description:
Some("Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each \'flit\' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four \'fits\', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI \'speed\' (for example, 8.0 GT/s), the \'transfers\' here refer to \'fits\'. Therefore, in L0, the system will transfer 1 \'flit\' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as \'data\' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual \'data\' and an additional 16 bits of other information. To calculate \'data\' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of data flits transmitted over QPI. Each flit contains 64b of data. This includes both DRS and NCB data flits (coherent and non-coherent). This can be used to calculate the data bandwidth of the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This does not include the header flits that go in data packets."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_C_RxR_ISMQ_RETRY.WB_CREDITS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(51),
umask:
Tuple::One(128),
event_name:
"UNC_C_RxR_ISMQ_RETRY.WB_CREDITS",
brief_description:
"ISMQ Retries",
public_description:
Some("Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Qualify one of the other subevents by a given RTID destination NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER1.nid."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
Some("CBoFilter1[15:0]"),
extsel:
false,}),
("UNC_M_RD_CAS_RANK6.ALLBANKS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(182),
umask:
Tuple::One(16),
event_name:
"UNC_M_RD_CAS_RANK6.ALLBANKS",
brief_description:
"RD_CAS Access to Rank 6; All Banks",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_S_RxR_BUSY_STARVED.AD_BNC",
IntelPerformanceCounterDescription{event_code:
Tuple::One(21),
umask:
Tuple::One(2),
event_name:
"UNC_S_RxR_BUSY_STARVED.AD_BNC",
brief_description:
"Injection Starvation; AD - Bounces",
public_description:
Some("Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress because a message (credited/bounceable) is being sent."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL0_POWER_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(15),
umask:
Tuple::One(0),
event_name:
"UNC_Q_RxL0_POWER_CYCLES",
brief_description:
"Cycles in L0",
public_description:
Some("Number of QPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_C_RxR_ISMQ_RETRY2.BL_SBO",
IntelPerformanceCounterDescription{event_code:
Tuple::One(42),
umask:
Tuple::One(2),
event_name:
"UNC_C_RxR_ISMQ_RETRY2.BL_SBO",
brief_description:
"ISMQ Request Queue Rejects; No BL Sbo Credits",
public_description:
Some("Counts the number of times that a request from the ISMQ was retried because of it lacked credits to send an BL packet to the Sbo."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_H_HITME_HIT.HOM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(113),
umask:
Tuple::One(15),
event_name:
"UNC_H_HITME_HIT.HOM",
brief_description:
"Counts Number of Hits in HitMe Cache; HOM Requests",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK7.BANK2",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(2),
event_name:
"UNC_M_RD_CAS_RANK7.BANK2",
brief_description:
"RD_CAS Access to Rank 7; Bank 2",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_P_DEMOTIONS_CORE16",
IntelPerformanceCounterDescription{event_code:
Tuple::One(64),
umask:
Tuple::One(0),
event_name:
"UNC_P_DEMOTIONS_CORE16",
brief_description:
"Core C State Demotions",
public_description:
Some("Counts the number of times when a configurable cores had a C-state demotion"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_H_DIRECTORY_UPDATE.ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(13),
umask:
Tuple::One(3),
event_name:
"UNC_H_DIRECTORY_UPDATE.ANY",
brief_description:
"Directory Updates; Any Directory Update",
public_description:
Some("Counts the number of directory updates that were required. These result in writes to the memory controller. This can be filtered by directory sets and directory clears."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK7.BANK5",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(5),
event_name:
"UNC_M_RD_CAS_RANK7.BANK5",
brief_description:
"RD_CAS Access to Rank 7; Bank 5",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_FLITS_G2.NDR_AK",
IntelPerformanceCounterDescription{event_code:
Tuple::One(3),
umask:
Tuple::One(2),
event_name:
"UNC_Q_RxL_FLITS_G2.NDR_AK",
brief_description:
"Flits Received - Group 2; Non-Data Response Rx Flits - AK",
public_description:
Some("Counts the number of flits received from the QPI Link. This is one of three \'groups\' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each \'flit\' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four \'fits\', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI \'speed\' (for example, 8.0 GT/s), the \'transfers\' here refer to \'fits\'. Therefore, in L0, the system will transfer 1 \'flit\' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as \'data\' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual \'data\' and an additional 16 bits of other information. To calculate \'data\' bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets destined for Route-thru to a remote socket."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_I_CACHE_TOTAL_OCCUPANCY.ANY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(18),
umask:
Tuple::One(1),
event_name:
"UNC_I_CACHE_TOTAL_OCCUPANCY.ANY",
brief_description:
"Total Write Cache Occupancy; Any Source",
public_description:
Some("Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks all requests from any source port."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_I_MISC1.SLOW_I",
IntelPerformanceCounterDescription{event_code:
Tuple::One(21),
umask:
Tuple::One(1),
event_name:
"UNC_I_MISC1.SLOW_I",
brief_description:
"Misc Events - Set 1; Slow Transfer of I Line",
public_description:
Some("Snoop took cacheline ownership before write from data was committed."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_I_RxR_BL_NCB_OCCUPANCY",
IntelPerformanceCounterDescription{event_code:
Tuple::One(8),
umask:
Tuple::One(0),
event_name:
"UNC_I_RxR_BL_NCB_OCCUPANCY",
brief_description:
"tbd",
public_description:
Some("Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_R3_RING_AD_USED.CCW_ODD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(7),
umask:
Tuple::One(8),
event_name:
"UNC_R3_RING_AD_USED.CCW_ODD",
brief_description:
"R3 AD Ring in Use; Counterclockwise and Odd",
public_description:
Some("Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity."),
counter:
Counter::Programmable(7),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK5.BANKG0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(181),
umask:
Tuple::One(17),
event_name:
"UNC_M_RD_CAS_RANK5.BANKG0",
brief_description:
"RD_CAS Access to Rank 5; Bank Group 0 (Banks 0-3)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_H_SBO1_CREDIT_OCCUPANCY.AD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(107),
umask:
Tuple::One(1),
event_name:
"UNC_H_SBO1_CREDIT_OCCUPANCY.AD",
brief_description:
"SBo1 Credits Occupancy; For AD Ring",
public_description:
Some("Number of Sbo 1 credits in use in a given cycle, per ring."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK1.BANKG2",
IntelPerformanceCounterDescription{event_code:
Tuple::One(177),
umask:
Tuple::One(19),
event_name:
"UNC_M_RD_CAS_RANK1.BANKG2",
brief_description:
"RD_CAS Access to Rank 1; Bank Group 2 (Banks 8-11)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_STALLS_VN1.BGF_NCS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(58),
umask:
Tuple::One(4),
event_name:
"UNC_Q_RxL_STALLS_VN1.BGF_NCS",
brief_description:
"Stalls Sending to R3QPI on VN1; BGF Stall - NDR",
public_description:
Some("Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the NDR message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_C_TxR_INSERTS.AK_CORE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(2),
umask:
Tuple::One(32),
event_name:
"UNC_C_TxR_INSERTS.AK_CORE",
brief_description:
"Egress Allocations; AK - Corebo",
public_description:
Some("Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the AK ring. This is commonly used for snoop responses coming from the core and destined for a Cachebo."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_STARVED.AK",
IntelPerformanceCounterDescription{event_code:
Tuple::One(109),
umask:
Tuple::One(1),
event_name:
"UNC_H_TxR_STARVED.AK",
brief_description:
"Injection Starvation; For AK Ring",
public_description:
Some("Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_U_FILTER_MATCH.U2C_DISABLE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(65),
umask:
Tuple::One(8),
event_name:
"UNC_U_FILTER_MATCH.U2C_DISABLE",
brief_description:
"Filter Match",
public_description:
Some("Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("UBOX"),
filter:
None,
extsel:
false,}),
("UNC_R3_RxR_INSERTS.NCB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(17),
umask:
Tuple::One(16),
event_name:
"UNC_R3_RxR_INSERTS.NCB",
brief_description:
"Ingress Allocations; NCB",
public_description:
Some("Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK4.BANK13",
IntelPerformanceCounterDescription{event_code:
Tuple::One(188),
umask:
Tuple::One(13),
event_name:
"UNC_M_WR_CAS_RANK4.BANK13",
brief_description:
"WR_CAS Access to Rank 4; Bank 13",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_P_FREQ_MIN_IO_P_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(115),
umask:
Tuple::One(0),
event_name:
"UNC_P_FREQ_MIN_IO_P_CYCLES",
brief_description:
"IO P Limit Strongest Lower Limit Cycles",
public_description:
Some("Counts the number of cycles when IO P Limit is preventing us from dropping the frequency lower. This algorithm monitors the needs to the IO subsystem on both local and remote sockets and will maintain a frequency high enough to maintain good IO BW. This is necessary for when all the IA cores on a socket are idle but a user still would like to maintain high IO Bandwidth."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_H_HITME_HIT.EVICTS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(113),
umask:
Tuple::One(66),
event_name:
"UNC_H_HITME_HIT.EVICTS",
brief_description:
"Counts Number of Hits in HitMe Cache; Allocations",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_RING_AK_USED.CW",
IntelPerformanceCounterDescription{event_code:
Tuple::One(63),
umask:
Tuple::One(3),
event_name:
"UNC_H_RING_AK_USED.CW",
brief_description:
"HA AK Ring in Use; Clockwise",
public_description:
Some("Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_S_TxR_OCCUPANCY.BL_BNC",
IntelPerformanceCounterDescription{event_code:
Tuple::One(1),
umask:
Tuple::One(8),
event_name:
"UNC_S_TxR_OCCUPANCY.BL_BNC",
brief_description:
"Egress Occupancy; BL - Bounces",
public_description:
Some("Occupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK7.BANK6",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(6),
event_name:
"UNC_M_RD_CAS_RANK7.BANK6",
brief_description:
"RD_CAS Access to Rank 7; Bank 6",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_P_CORE4_TRANSITION_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(100),
umask:
Tuple::One(0),
event_name:
"UNC_P_CORE4_TRANSITION_CYCLES",
brief_description:
"Core C State Transition Cycles",
public_description:
Some("Number of cycles spent performing core C state transitions. There is one event per core."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_H_REQUESTS.WRITES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(1),
umask:
Tuple::One(12),
event_name:
"UNC_H_REQUESTS.WRITES",
brief_description:
"Read and Write Requests; Writes",
public_description:
Some("Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).; Incoming write requests."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_C_TOR_OCCUPANCY.EVICTION",
IntelPerformanceCounterDescription{event_code:
Tuple::One(54),
umask:
Tuple::One(4),
event_name:
"UNC_C_TOR_OCCUPANCY.EVICTION",
brief_description:
"TOR Occupancy; Evictions",
public_description:
Some("For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent \'filters\' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select \'MISS_OPC_MATCH\' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding eviction transactions in the TOR. Evictions can be quick, such as when the line is in the F, S, or E states and no core valid bits are set. They can also be longer if either CV bits are set (so the cores need to be snooped) and/or if there is a HitM (in which case it is necessary to write the request out to memory)."),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_R3_RxR_OCCUPANCY_VN1.NCS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(19),
umask:
Tuple::One(32),
event_name:
"UNC_R3_RxR_OCCUPANCY_VN1.NCS",
brief_description:
"VN1 Ingress Occupancy Accumulator; NCS",
public_description:
Some("Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.; NCS Ingress Queue"),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_R2_IIO_CREDIT.ISOCH_QPI0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(45),
umask:
Tuple::One(4),
event_name:
"UNC_R2_IIO_CREDIT.ISOCH_QPI0",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_CREDITS_CONSUMED_VNA",
IntelPerformanceCounterDescription{event_code:
Tuple::One(29),
umask:
Tuple::One(0),
event_name:
"UNC_Q_RxL_CREDITS_CONSUMED_VNA",
brief_description:
"VNA Credit Consumed",
public_description:
Some("Counts the number of times that an RxQ VNA credit was consumed (i.e. message uses a VNA credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_M_RD_CAS_RANK7.BANK7",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(7),
event_name:
"UNC_M_RD_CAS_RANK7.BANK7",
brief_description:
"RD_CAS Access to Rank 7; Bank 7",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_H_HITME_LOOKUP.RSP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(112),
umask:
Tuple::One(128),
event_name:
"UNC_H_HITME_LOOKUP.RSP",
brief_description:
"Counts Number of times HitMe Cache is accessed; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK6.BANK12",
IntelPerformanceCounterDescription{event_code:
Tuple::One(190),
umask:
Tuple::One(12),
event_name:
"UNC_M_WR_CAS_RANK6.BANK12",
brief_description:
"WR_CAS Access to Rank 6; Bank 12",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_C_TOR_OCCUPANCY.NID_OPCODE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(54),
umask:
Tuple::One(65),
event_name:
"UNC_C_TOR_OCCUPANCY.NID_OPCODE",
brief_description:
"TOR Occupancy; NID and Opcode Matched",
public_description:
Some("For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent \'filters\' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select \'MISS_OPC_MATCH\' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries that match a NID and an opcode."),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
Some("CBoFilter1[28:20], CBoFilter1[15:0]"),
extsel:
false,}),
("UNC_S_RING_AD_USED.DOWN_EVEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(27),
umask:
Tuple::One(4),
event_name:
"UNC_S_RING_AD_USED.DOWN_EVEN",
brief_description:
"AD Ring In Use; Down and Event",
public_description:
Some("Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the \'UP\' direction is on the clockwise ring and \'DN\' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Event ring polarity."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK1.BANK1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(185),
umask:
Tuple::One(1),
event_name:
"UNC_M_WR_CAS_RANK1.BANK1",
brief_description:
"WR_CAS Access to Rank 1; Bank 1",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK1.BANKG0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(177),
umask:
Tuple::One(17),
event_name:
"UNC_M_RD_CAS_RANK1.BANKG0",
brief_description:
"RD_CAS Access to Rank 1; Bank Group 0 (Banks 0-3)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_CREDITS_CONSUMED_VN0.HOM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(30),
umask:
Tuple::One(8),
event_name:
"UNC_Q_RxL_CREDITS_CONSUMED_VN0.HOM",
brief_description:
"VN0 Credit Consumed; HOM",
public_description:
Some("Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the HOM message class."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_M_POWER_THROTTLE_CYCLES.RANK0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(65),
umask:
Tuple::One(1),
event_name:
"UNC_M_POWER_THROTTLE_CYCLES.RANK0",
brief_description:
"Throttle Cycles for Rank 0; DIMM ID",
public_description:
Some("Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.; Thermal throttling is performed per DIMM. We support 3 DIMMs per channel. This ID allows us to filter by ID."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_POWER_CKE_CYCLES.RANK1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(131),
umask:
Tuple::One(2),
event_name:
"UNC_M_POWER_CKE_CYCLES.RANK1",
brief_description:
"CKE_ON_CYCLES by Rank; DIMM ID",
public_description:
Some("Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary)."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_PRE_COUNT.RD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(2),
umask:
Tuple::One(4),
event_name:
"UNC_M_PRE_COUNT.RD",
brief_description:
"DRAM Precharge commands.; Precharge due to read",
public_description:
Some("Counts the number of DRAM Precharge commands sent on this channel."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK0.BANKG1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(176),
umask:
Tuple::One(18),
event_name:
"UNC_M_RD_CAS_RANK0.BANKG1",
brief_description:
"RD_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN3",
IntelPerformanceCounterDescription{event_code:
Tuple::One(24),
umask:
Tuple::One(8),
event_name:
"UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN3",
brief_description:
"HA iMC CHN0 WPQ Credits Empty - Regular; Channel 3",
public_description:
Some("Counts the number of cycles when there are no \'regular\' credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC\'s WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and \'special\' requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK0.BANK2",
IntelPerformanceCounterDescription{event_code:
Tuple::One(184),
umask:
Tuple::One(2),
event_name:
"UNC_M_WR_CAS_RANK0.BANK2",
brief_description:
"WR_CAS Access to Rank 0; Bank 2",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_C_QLRU.AGE1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(60),
umask:
Tuple::One(2),
event_name:
"UNC_C_QLRU.AGE1",
brief_description:
"LRU Queue; LRU Age 1",
public_description:
Some("How often age was set to 1"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_I_RxR_BL_NCB_INSERTS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(2),
umask:
Tuple::One(0),
event_name:
"UNC_I_RxR_BL_NCB_INSERTS",
brief_description:
"BL Ingress Occupancy - NCB",
public_description:
Some("Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK5.BANK15",
IntelPerformanceCounterDescription{event_code:
Tuple::One(181),
umask:
Tuple::One(15),
event_name:
"UNC_M_RD_CAS_RANK5.BANK15",
brief_description:
"RD_CAS Access to Rank 5; Bank 15",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_I_TxR_DATA_INSERTS_NCB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(14),
umask:
Tuple::One(0),
event_name:
"UNC_I_TxR_DATA_INSERTS_NCB",
brief_description:
"Outbound Read Requests",
public_description:
Some("Counts the number of requests issued to the switch (towards the devices)."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_H_TxR_BL_INSERTS.SCHED0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(51),
umask:
Tuple::One(1),
event_name:
"UNC_H_TxR_BL_INSERTS.SCHED0",
brief_description:
"BL Egress Allocations; Scheduler 0",
public_description:
Some("BL Egress Allocations; Filter for allocations from scheduler bank 0"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_C_LLC_VICTIMS.E_STATE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(55),
umask:
Tuple::One(2),
event_name:
"UNC_C_LLC_VICTIMS.E_STATE",
brief_description:
"Lines Victimized; Lines in E state",
public_description:
Some("Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_R2_TxR_CYCLES_NE.AK",
IntelPerformanceCounterDescription{event_code:
Tuple::One(35),
umask:
Tuple::One(2),
event_name:
"UNC_R2_TxR_CYCLES_NE.AK",
brief_description:
"Egress Cycles Not Empty; AK",
public_description:
Some("Counts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity.; AK Egress Queue"),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_STALLS_VN1.BGF_SNP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(58),
umask:
Tuple::One(16),
event_name:
"UNC_Q_RxL_STALLS_VN1.BGF_SNP",
brief_description:
"Stalls Sending to R3QPI on VN1; BGF Stall - NCB",
public_description:
Some("Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the NCB message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_M_RD_CAS_RANK4.BANK1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(180),
umask:
Tuple::One(1),
event_name:
"UNC_M_RD_CAS_RANK4.BANK1",
brief_description:
"RD_CAS Access to Rank 4; Bank 1",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_R3_IOT_CTS_LO.CTS1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(12),
umask:
Tuple::One(2),
event_name:
"UNC_R3_IOT_CTS_LO.CTS1",
brief_description:
"IOT Common Trigger Sequencer - Lo",
public_description:
Some("Debug Mask/Match Tie-Ins"),
counter:
Counter::Programmable(7),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxL_FLITS_G1.DRS_DATA",
IntelPerformanceCounterDescription{event_code:
Tuple::One(0),
umask:
Tuple::One(8),
event_name:
"UNC_Q_TxL_FLITS_G1.DRS_DATA",
brief_description:
"Flits Transferred - Group 1; DRS Data Flits",
public_description:
Some("Counts the number of flits trasmitted across the QPI Link. This is one of three \'groups\' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each \'flit\' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four \'fits\', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI \'speed\' (for example, 8.0 GT/s), the \'transfers\' here refer to \'fits\'. Therefore, in L0, the system will transfer 1 \'flit\' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as \'data\' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual \'data\' and an additional 16 bits of other information. To calculate \'data\' bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of data flits transmitted over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits transmitted over the NCB channel which transmits non-coherent data. This includes only the data flits (not the header)."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_H_REQUESTS.WRITES_REMOTE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(1),
umask:
Tuple::One(8),
event_name:
"UNC_H_REQUESTS.WRITES_REMOTE",
brief_description:
"Read and Write Requests; Remote Writes",
public_description:
Some("Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only writes coming from remote sockets."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN2",
IntelPerformanceCounterDescription{event_code:
Tuple::One(21),
umask:
Tuple::One(4),
event_name:
"UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN2",
brief_description:
"iMC RPQ Credits Empty - Regular; Channel 2",
public_description:
Some("Counts the number of cycles when there are no \'regular\' credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC\'s RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and \'special\' requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_C_RxR_INSERTS.IPQ",
IntelPerformanceCounterDescription{event_code:
Tuple::One(19),
umask:
Tuple::One(4),
event_name:
"UNC_C_RxR_INSERTS.IPQ",
brief_description:
"Ingress Allocations; IPQ",
public_description:
Some("Counts number of allocations per cycle into the specified Ingress queue."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_M_PRE_COUNT.PAGE_CLOSE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(2),
umask:
Tuple::One(2),
event_name:
"UNC_M_PRE_COUNT.PAGE_CLOSE",
brief_description:
"DRAM Precharge commands.; Precharge due to timer expiration",
public_description:
Some("Counts the number of DRAM Precharge commands sent on this channel.; Counts the number of DRAM Precharge commands sent on this channel as a result of the page close counter expiring. This does not include implicit precharge commands sent in auto-precharge mode."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK0.BANK10",
IntelPerformanceCounterDescription{event_code:
Tuple::One(184),
umask:
Tuple::One(10),
event_name:
"UNC_M_WR_CAS_RANK0.BANK10",
brief_description:
"WR_CAS Access to Rank 0; Bank 10",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_C_RING_BOUNCES.IV",
IntelPerformanceCounterDescription{event_code:
Tuple::One(5),
umask:
Tuple::One(16),
event_name:
"UNC_C_RING_BOUNCES.IV",
brief_description:
"Number of LLC responses that bounced on the Ring.; Snoops of processor\'s cache.",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_I_MISC1.SLOW_S",
IntelPerformanceCounterDescription{event_code:
Tuple::One(21),
umask:
Tuple::One(2),
event_name:
"UNC_I_MISC1.SLOW_S",
brief_description:
"Misc Events - Set 1; Slow Transfer of S Line",
public_description:
Some("Secondary received a transfer that did not have sufficient MESI state"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_FLITS_G2.NDR_AD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(3),
umask:
Tuple::One(1),
event_name:
"UNC_Q_RxL_FLITS_G2.NDR_AD",
brief_description:
"Flits Received - Group 2; Non-Data Response Rx Flits - AD",
public_description:
Some("Counts the number of flits received from the QPI Link. This is one of three \'groups\' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each \'flit\' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four \'fits\', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI \'speed\' (for example, 8.0 GT/s), the \'transfers\' here refer to \'fits\'. Therefore, in L0, the system will transfer 1 \'flit\' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as \'data\' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual \'data\' and an additional 16 bits of other information. To calculate \'data\' bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets to the local socket which use the AK ring."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_H_DIRECT2CORE_COUNT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(17),
umask:
Tuple::One(0),
event_name:
"UNC_H_DIRECT2CORE_COUNT",
brief_description:
"Direct2Core Messages Sent",
public_description:
Some("Number of Direct2Core messages sent"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK0.BANK6",
IntelPerformanceCounterDescription{event_code:
Tuple::One(184),
umask:
Tuple::One(6),
event_name:
"UNC_M_WR_CAS_RANK0.BANK6",
brief_description:
"WR_CAS Access to Rank 0; Bank 6",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_I_MISC1.SEC_RCVD_VLD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(21),
umask:
Tuple::One(64),
event_name:
"UNC_I_MISC1.SEC_RCVD_VLD",
brief_description:
"Misc Events - Set 1; Received Valid",
public_description:
Some("Secondary received a transfer that did have sufficient MESI state"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_M_PRE_COUNT.PAGE_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(2),
umask:
Tuple::One(1),
event_name:
"UNC_M_PRE_COUNT.PAGE_MISS",
brief_description:
"DRAM Precharge commands.; Precharges due to page miss",
public_description:
Some("Counts the number of DRAM Precharge commands sent on this channel.; Counts the number of DRAM Precharge commands sent on this channel as a result of page misses. This does not include explicit precharge commands sent with CAS commands in Auto-Precharge mode. This does not include PRE commands sent as a result of the page close counter expiration."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_WPQ_WRITE_HIT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(36),
umask:
Tuple::One(0),
event_name:
"UNC_M_WPQ_WRITE_HIT",
brief_description:
"Write Pending Queue CAM Match",
public_description:
Some("Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_S_TxR_ADS_USED.AD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(4),
umask:
Tuple::One(1),
event_name:
"UNC_S_TxR_ADS_USED.AD",
brief_description:
"tbd",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_C_TOR_INSERTS.NID_MISS_ALL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(53),
umask:
Tuple::One(74),
event_name:
"UNC_C_TOR_INSERTS.NID_MISS_ALL",
brief_description:
"TOR Inserts; NID Matched Miss All",
public_description:
Some("Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent \'filters\' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select \'MISS_OPC_MATCH\' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All NID matched miss requests that were inserted into the TOR."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
Some("CBoFilter1[15:0]"),
extsel:
false,}),
("UNC_Q_RxL_OCCUPANCY_SNP.VN1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(25),
umask:
Tuple::One(2),
event_name:
"UNC_Q_RxL_OCCUPANCY_SNP.VN1",
brief_description:
"RxQ Occupancy - SNP; for VN1",
public_description:
Some("Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors SNP flits only."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_H_SNOOP_CYCLES_NE.REMOTE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(8),
umask:
Tuple::One(2),
event_name:
"UNC_H_SNOOP_CYCLES_NE.REMOTE",
brief_description:
"Cycles with Snoops Outstanding; Remote Requests",
public_description:
Some("Counts cycles when one or more snoops are outstanding.; This filter includes only requests coming from remote sockets."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_RING_BL_USED.CCW_ODD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(64),
umask:
Tuple::One(8),
event_name:
"UNC_H_RING_BL_USED.CCW_ODD",
brief_description:
"HA BL Ring in Use; Counterclockwise and Odd",
public_description:
Some("Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_I_MISC0.2ND_ATOMIC_INSERT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(20),
umask:
Tuple::One(16),
event_name:
"UNC_I_MISC0.2ND_ATOMIC_INSERT",
brief_description:
"Misc Events - Set 0; Cache Inserts of Atomic Transactions as Secondary",
public_description:
None,
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK7.BANK10",
IntelPerformanceCounterDescription{event_code:
Tuple::One(191),
umask:
Tuple::One(10),
event_name:
"UNC_M_WR_CAS_RANK7.BANK10",
brief_description:
"WR_CAS Access to Rank 7; Bank 10",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_H_SNOOP_RESP.RSP_FWD_WB",
IntelPerformanceCounterDescription{event_code:
Tuple::One(33),
umask:
Tuple::One(32),
event_name:
"UNC_H_SNOOP_RESP.RSP_FWD_WB",
brief_description:
"Snoop Responses Received; Rsp*Fwd*WB",
public_description:
Some("Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of Rsp*Fwd*WB. This snoop response is only used in 4s systems. It is used when a snoop HITM\'s in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_C_RING_BL_USED.DOWN_EVEN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(29),
umask:
Tuple::One(4),
event_name:
"UNC_C_RING_BL_USED.DOWN_EVEN",
brief_description:
"BL Ring in Use; Down and Even",
public_description:
Some("Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the \'UP\' direction is on the clockwise ring and \'DN\' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_M_POWER_CKE_CYCLES.RANK2",
IntelPerformanceCounterDescription{event_code:
Tuple::One(131),
umask:
Tuple::One(4),
event_name:
"UNC_M_POWER_CKE_CYCLES.RANK2",
brief_description:
"CKE_ON_CYCLES by Rank; DIMM ID",
public_description:
Some("Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary)."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_CLOCKTICKS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(0),
umask:
Tuple::One(0),
event_name:
"UNC_M_CLOCKTICKS",
brief_description:
"DRAM Clockticks",
public_description:
Some("RTLSignal: 1\'b1;RTLSignal2: ONE"),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK0.BANK8",
IntelPerformanceCounterDescription{event_code:
Tuple::One(184),
umask:
Tuple::One(8),
event_name:
"UNC_M_WR_CAS_RANK0.BANK8",
brief_description:
"WR_CAS Access to Rank 0; Bank 8",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_R2_RING_BL_USED.CW",
IntelPerformanceCounterDescription{event_code:
Tuple::One(9),
umask:
Tuple::One(3),
event_name:
"UNC_R2_RING_BL_USED.CW",
brief_description:
"R2 BL Ring in Use; Clockwise",
public_description:
Some("Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK7.BANK12",
IntelPerformanceCounterDescription{event_code:
Tuple::One(191),
umask:
Tuple::One(12),
event_name:
"UNC_M_WR_CAS_RANK7.BANK12",
brief_description:
"WR_CAS Access to Rank 7; Bank 12",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_U_FILTER_MATCH.U2C_ENABLE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(65),
umask:
Tuple::One(4),
event_name:
"UNC_U_FILTER_MATCH.U2C_ENABLE",
brief_description:
"Filter Match",
public_description:
Some("Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("UBOX"),
filter:
Some("UBoxFilter[3:0]"),
extsel:
false,}),
("UNC_M_RD_CAS_RANK1.BANK10",
IntelPerformanceCounterDescription{event_code:
Tuple::One(177),
umask:
Tuple::One(10),
event_name:
"UNC_M_RD_CAS_RANK1.BANK10",
brief_description:
"RD_CAS Access to Rank 1; Bank 10",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK7.BANK14",
IntelPerformanceCounterDescription{event_code:
Tuple::One(183),
umask:
Tuple::One(14),
event_name:
"UNC_M_RD_CAS_RANK7.BANK14",
brief_description:
"RD_CAS Access to Rank 7; Bank 14",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK6.BANK6",
IntelPerformanceCounterDescription{event_code:
Tuple::One(182),
umask:
Tuple::One(6),
event_name:
"UNC_M_RD_CAS_RANK6.BANK6",
brief_description:
"RD_CAS Access to Rank 6; Bank 6",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_RPQ_INSERTS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(16),
umask:
Tuple::One(0),
event_name:
"UNC_M_RPQ_INSERTS",
brief_description:
"Read Pending Queue Allocations",
public_description:
Some("Counts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK4.BANK14",
IntelPerformanceCounterDescription{event_code:
Tuple::One(188),
umask:
Tuple::One(14),
event_name:
"UNC_M_WR_CAS_RANK4.BANK14",
brief_description:
"WR_CAS Access to Rank 4; Bank 14",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_STALLS_VN0.GV",
IntelPerformanceCounterDescription{event_code:
Tuple::One(53),
umask:
Tuple::One(128),
event_name:
"UNC_Q_RxL_STALLS_VN0.GV",
brief_description:
"Stalls Sending to R3QPI on VN0; GV",
public_description:
Some("Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled because a GV transition (frequency transition) was taking place."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_R3_SBO0_CREDITS_ACQUIRED.AD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(40),
umask:
Tuple::One(1),
event_name:
"UNC_R3_SBO0_CREDITS_ACQUIRED.AD",
brief_description:
"SBo0 Credits Acquired; For AD Ring",
public_description:
Some("Number of Sbo 0 credits acquired in a given cycle, per ring."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_CREDITS_CONSUMED_VN1.NCS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(57),
umask:
Tuple::One(4),
event_name:
"UNC_Q_RxL_CREDITS_CONSUMED_VN1.NCS",
brief_description:
"VN1 Credit Consumed; NCS",
public_description:
Some("Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the NCS message class."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_C_RING_SINK_STARVED.AK",
IntelPerformanceCounterDescription{event_code:
Tuple::One(6),
umask:
Tuple::One(2),
event_name:
"UNC_C_RING_SINK_STARVED.AK",
brief_description:
"AK",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_R3_QPI0_BL_CREDITS_EMPTY.VNA",
IntelPerformanceCounterDescription{event_code:
Tuple::One(33),
umask:
Tuple::One(1),
event_name:
"UNC_R3_QPI0_BL_CREDITS_EMPTY.VNA",
brief_description:
"QPI0 BL Credits Empty",
public_description:
Some("No credits available to send to QPI0 on the BL Ring; VNA"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R3QPI"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK1.BANK12",
IntelPerformanceCounterDescription{event_code:
Tuple::One(185),
umask:
Tuple::One(12),
event_name:
"UNC_M_WR_CAS_RANK1.BANK12",
brief_description:
"WR_CAS Access to Rank 1; Bank 12",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_Q_TxL0_POWER_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(12),
umask:
Tuple::One(0),
event_name:
"UNC_Q_TxL0_POWER_CYCLES",
brief_description:
"Cycles in L0",
public_description:
Some("Number of QPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_U_FILTER_MATCH.DISABLE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(65),
umask:
Tuple::One(2),
event_name:
"UNC_U_FILTER_MATCH.DISABLE",
brief_description:
"Filter Match",
public_description:
Some("Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID."),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("UBOX"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(30),
umask:
Tuple::One(4),
event_name:
"UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCS",
brief_description:
"VN0 Credit Consumed; NCS",
public_description:
Some("Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the NCS message class."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_H_TRACKER_OCCUPANCY.WRITES_LOCAL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(4),
umask:
Tuple::One(16),
event_name:
"UNC_H_TRACKER_OCCUPANCY.WRITES_LOCAL",
brief_description:
"Tracker Occupancy Accumultor; Local Write Requests",
public_description:
Some("Accumulates the occupancy of the local HA tracker pool in every cycle. This can be used in conjection with the \'not empty\' stat to calculate average queue occupancy or the \'allocations\' stat in order to calculate average queue latency. HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_HITME_LOOKUP.ALLOCS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(112),
umask:
Tuple::One(112),
event_name:
"UNC_H_HITME_LOOKUP.ALLOCS",
brief_description:
"Counts Number of times HitMe Cache is accessed; Allocations",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_P_FREQ_MAX_POWER_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(5),
umask:
Tuple::One(0),
event_name:
"UNC_P_FREQ_MAX_POWER_CYCLES",
brief_description:
"Power Strongest Upper Limit Cycles",
public_description:
Some("Counts the number of cycles when power is the upper limit on frequency."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_H_STALL_NO_SBO_CREDIT.SBO0_AD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(108),
umask:
Tuple::One(1),
event_name:
"UNC_H_STALL_NO_SBO_CREDIT.SBO0_AD",
brief_description:
"Stall on No Sbo Credits; For SBo0, AD Ring",
public_description:
Some("Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN1",
IntelPerformanceCounterDescription{event_code:
Tuple::One(25),
umask:
Tuple::One(2),
event_name:
"UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN1",
brief_description:
"HA iMC CHN0 WPQ Credits Empty - Special; Channel 1",
public_description:
Some("Counts the number of cycles when there are no \'special\' credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC\'s WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and \'special\' requests such as ISOCH writes. This count only tracks the \'special\' credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_R2_TxR_NACK_CW.UP_BL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(38),
umask:
Tuple::One(16),
event_name:
"UNC_R2_TxR_NACK_CW.UP_BL",
brief_description:
"Egress CCW NACK; BL CCW",
public_description:
Some("AD CounterClockwise Egress Queue"),
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_C_TOR_OCCUPANCY.MISS_LOCAL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(54),
umask:
Tuple::One(42),
event_name:
"UNC_C_TOR_OCCUPANCY.MISS_LOCAL",
brief_description:
"TOR Occupancy",
public_description:
Some("For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent \'filters\' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select \'MISS_OPC_MATCH\' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)"),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_C_RxR_ISMQ_RETRY2.TARGET",
IntelPerformanceCounterDescription{event_code:
Tuple::One(42),
umask:
Tuple::One(64),
event_name:
"UNC_C_RxR_ISMQ_RETRY2.TARGET",
brief_description:
"ISMQ Request Queue Rejects; Target Node Filter",
public_description:
Some("Counts the number of times that a request from the ISMQ was retried filtered by the Target NodeID as specified in the Cbox\'s Filter register."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
Some("CBoFilter1[15:0]"),
extsel:
false,}),
("UNC_H_SNOOP_RESP.RSPI",
IntelPerformanceCounterDescription{event_code:
Tuple::One(33),
umask:
Tuple::One(1),
event_name:
"UNC_H_SNOOP_RESP.RSPI",
brief_description:
"Snoop Responses Received; RspI",
public_description:
Some("Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoops responses of RspI. RspI is returned when the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO hits non-modified data)."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_C_RxR_IRQ_RETRY.ADDR_CONFLICT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(50),
umask:
Tuple::One(4),
event_name:
"UNC_C_RxR_IRQ_RETRY.ADDR_CONFLICT",
brief_description:
"Ingress Request Queue Rejects; Address Conflict",
public_description:
Some("Counts the number of times that a request from the IRQ was retried because of an address match in the TOR. In order to maintain coherency, requests to the same address are not allowed to pass each other up in the Cbo. Therefore, if there is an outstanding request to a given address, one cannot issue another request to that address until it is complete. This comes up most commonly with prefetches. Outstanding prefetches occasionally will not complete their memory fetch and a demand request to the same address will then sit in the IRQ and get retried until the prefetch fills the data into the LLC. Therefore, it will not be uncommon to see this case in high bandwidth streaming workloads when the LLC Prefetcher in the core is enabled."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_FLITS_G0.IDLE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(1),
umask:
Tuple::One(1),
event_name:
"UNC_Q_RxL_FLITS_G0.IDLE",
brief_description:
"Flits Received - Group 0; Idle and Null Flits",
public_description:
Some("Counts the number of flits received from the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each \'flit\' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four \'fits\', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI \'speed\' (for example, 8.0 GT/s), the \'transfers\' here refer to \'fits\'. Therefore, in L0, the system will transfer 1 \'flit\' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as \'data\' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual \'data\' and an additional 16 bits of other information. To calculate \'data\' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of flits received over QPI that do not hold protocol payload. When QPI is not in a power saving state, it continuously transmits flits across the link. When there are no protocol flits to send, it will send IDLE and NULL flits across. These flits sometimes do carry a payload, such as credit returns, but are generall not considered part of the QPI bandwidth."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
false,}),
("UNC_S_TxR_OCCUPANCY.AD_BNC",
IntelPerformanceCounterDescription{event_code:
Tuple::One(1),
umask:
Tuple::One(2),
event_name:
"UNC_S_TxR_OCCUPANCY.AD_BNC",
brief_description:
"Egress Occupancy; AD - Bounces",
public_description:
Some("Occupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_OCCUPANCY_DRS.VN0",
IntelPerformanceCounterDescription{event_code:
Tuple::One(21),
umask:
Tuple::One(1),
event_name:
"UNC_Q_RxL_OCCUPANCY_DRS.VN0",
brief_description:
"RxQ Occupancy - DRS; for VN0",
public_description:
Some("Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors DRS flits only."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_P_CORE1_TRANSITION_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(97),
umask:
Tuple::One(0),
event_name:
"UNC_P_CORE1_TRANSITION_CYCLES",
brief_description:
"Core C State Transition Cycles",
public_description:
Some("Number of cycles spent performing core C state transitions. There is one event per core."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_C_MISC.WC_ALIASING",
IntelPerformanceCounterDescription{event_code:
Tuple::One(57),
umask:
Tuple::One(2),
event_name:
"UNC_C_MISC.WC_ALIASING",
brief_description:
"Cbo Misc; Write Combining Aliasing",
public_description:
Some("Miscellaneous events in the Cbo.; Counts the number of times that a USWC write (WCIL(F)) transaction hit in the LLC in M state, triggering a WBMtoI followed by the USWC write. This occurs when there is WC aliasing."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_R2_TxR_CYCLES_NE.AD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(35),
umask:
Tuple::One(1),
event_name:
"UNC_R2_TxR_CYCLES_NE.AD",
brief_description:
"Egress Cycles Not Empty; AD",
public_description:
Some("Counts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity.; AD Egress Queue"),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK6.BANK12",
IntelPerformanceCounterDescription{event_code:
Tuple::One(182),
umask:
Tuple::One(12),
event_name:
"UNC_M_RD_CAS_RANK6.BANK12",
brief_description:
"RD_CAS Access to Rank 6; Bank 12",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_C_TOR_OCCUPANCY.REMOTE",
IntelPerformanceCounterDescription{event_code:
Tuple::One(54),
umask:
Tuple::One(136),
event_name:
"UNC_C_TOR_OCCUPANCY.REMOTE",
brief_description:
"TOR Occupancy",
public_description:
Some("For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent \'filters\' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select \'MISS_OPC_MATCH\' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)"),
counter:
Counter::Programmable(1),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_FLITS_G1.HOM_REQ",
IntelPerformanceCounterDescription{event_code:
Tuple::One(2),
umask:
Tuple::One(2),
event_name:
"UNC_Q_RxL_FLITS_G1.HOM_REQ",
brief_description:
"Flits Received - Group 1; HOM Request Flits",
public_description:
Some("Counts the number of flits received from the QPI Link. This is one of three \'groups\' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each \'flit\' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four \'fits\', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI \'speed\' (for example, 8.0 GT/s), the \'transfers\' here refer to \'fits\'. Therefore, in L0, the system will transfer 1 \'flit\' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as \'data\' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual \'data\' and an additional 16 bits of other information. To calculate \'data\' bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of data request received over QPI on the home channel. This basically counts the number of remote memory requests received over QPI. In conjunction with the local read count in the Home Agent, one can calculate the number of LLC Misses."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_C_MISC.CVZERO_PREFETCH_MISS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(57),
umask:
Tuple::One(32),
event_name:
"UNC_C_MISC.CVZERO_PREFETCH_MISS",
brief_description:
"Cbo Misc; DRd hitting non-M with raw CV=0",
public_description:
Some("Miscellaneous events in the Cbo."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_STALLS_VN0.EGRESS_CREDITS",
IntelPerformanceCounterDescription{event_code:
Tuple::One(53),
umask:
Tuple::One(64),
event_name:
"UNC_Q_RxL_STALLS_VN0.EGRESS_CREDITS",
brief_description:
"Stalls Sending to R3QPI on VN0; Egress Credits",
public_description:
Some("Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet because there were insufficient BGF credits. For details on a message class granularity, use the Egress Credit Occupancy events."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_M_CAS_COUNT.WR_WMM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(4),
umask:
Tuple::One(4),
event_name:
"UNC_M_CAS_COUNT.WR_WMM",
brief_description:
"DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode",
public_description:
Some("DRAM RD_CAS and WR_CAS Commands; Counts the total number or DRAM Write CAS commands issued on this channel while in Write-Major-Mode."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_H_HITME_HIT_PV_BITS_SET.HOM",
IntelPerformanceCounterDescription{event_code:
Tuple::One(114),
umask:
Tuple::One(15),
event_name:
"UNC_H_HITME_HIT_PV_BITS_SET.HOM",
brief_description:
"Accumulates Number of PV bits set on HitMe Cache Hits; HOM Requests",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK4.BANK12",
IntelPerformanceCounterDescription{event_code:
Tuple::One(188),
umask:
Tuple::One(12),
event_name:
"UNC_M_WR_CAS_RANK4.BANK12",
brief_description:
"WR_CAS Access to Rank 4; Bank 12",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_Q_RxL_CREDITS_CONSUMED_VN0.SNP",
IntelPerformanceCounterDescription{event_code:
Tuple::One(30),
umask:
Tuple::One(16),
event_name:
"UNC_Q_RxL_CREDITS_CONSUMED_VN0.SNP",
brief_description:
"VN0 Credit Consumed; SNP",
public_description:
Some("Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the SNP message class."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("QPI LL"),
filter:
None,
extsel:
true,}),
("UNC_M_RD_CAS_RANK0.BANK9",
IntelPerformanceCounterDescription{event_code:
Tuple::One(176),
umask:
Tuple::One(9),
event_name:
"UNC_M_RD_CAS_RANK0.BANK9",
brief_description:
"RD_CAS Access to Rank 0; Bank 9",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_S_RxR_INSERTS.AD_CRD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(19),
umask:
Tuple::One(1),
event_name:
"UNC_S_RxR_INSERTS.AD_CRD",
brief_description:
"Ingress Allocations; AD - Credits",
public_description:
Some("Number of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("SBO"),
filter:
None,
extsel:
false,}),
("UNC_C_RxR_IRQ_RETRY2.BL_SBO",
IntelPerformanceCounterDescription{event_code:
Tuple::One(41),
umask:
Tuple::One(2),
event_name:
"UNC_C_RxR_IRQ_RETRY2.BL_SBO",
brief_description:
"Ingress Request Queue Rejects; No BL Sbo Credits",
public_description:
Some("Counts the number of times that a request from the IPQ was retried because of it lacked credits to send an BL packet to the Sbo."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_M_WR_CAS_RANK7.BANK4",
IntelPerformanceCounterDescription{event_code:
Tuple::One(191),
umask:
Tuple::One(4),
event_name:
"UNC_M_WR_CAS_RANK7.BANK4",
brief_description:
"WR_CAS Access to Rank 7; Bank 4",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_R2_RING_BL_USED.CW_ODD",
IntelPerformanceCounterDescription{event_code:
Tuple::One(9),
umask:
Tuple::One(2),
event_name:
"UNC_R2_RING_BL_USED.CW_ODD",
brief_description:
"R2 BL Ring in Use; Clockwise and Odd",
public_description:
Some("Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("R2PCIe"),
filter:
None,
extsel:
false,}),
("UNC_I_MISC0.PF_ACK_HINT",
IntelPerformanceCounterDescription{event_code:
Tuple::One(20),
umask:
Tuple::One(64),
event_name:
"UNC_I_MISC0.PF_ACK_HINT",
brief_description:
"Misc Events - Set 0; Prefetch Ack Hints From Primary to Secondary",
public_description:
None,
counter:
Counter::Programmable(3),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("IRP"),
filter:
None,
extsel:
false,}),
("UNC_P_PROCHOT_EXTERNAL_CYCLES",
IntelPerformanceCounterDescription{event_code:
Tuple::One(10),
umask:
Tuple::One(0),
event_name:
"UNC_P_PROCHOT_EXTERNAL_CYCLES",
brief_description:
"External Prochot",
public_description:
Some("Counts the number of cycles that we are in external PROCHOT mode. This mode is triggered when a sensor off the die determines that something off-die (like DRAM) is too hot and must throttle to avoid damaging the chip."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("PCU"),
filter:
None,
extsel:
false,}),
("UNC_H_SBO0_CREDITS_ACQUIRED.BL",
IntelPerformanceCounterDescription{event_code:
Tuple::One(104),
umask:
Tuple::One(2),
event_name:
"UNC_H_SBO0_CREDITS_ACQUIRED.BL",
brief_description:
"SBo0 Credits Acquired; For BL Ring",
public_description:
Some("Number of Sbo 0 credits acquired in a given cycle, per ring."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("HA"),
filter:
None,
extsel:
false,}),
("UNC_C_RING_BL_USED.DOWN",
IntelPerformanceCounterDescription{event_code:
Tuple::One(29),
umask:
Tuple::One(12),
event_name:
"UNC_C_RING_BL_USED.DOWN",
brief_description:
"BL Ring in Use; Down",
public_description:
Some("Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the \'UP\' direction is on the clockwise ring and \'DN\' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,}),
("UNC_M_RD_CAS_RANK0.BANK13",
IntelPerformanceCounterDescription{event_code:
Tuple::One(176),
umask:
Tuple::One(13),
event_name:
"UNC_M_RD_CAS_RANK0.BANK13",
brief_description:
"RD_CAS Access to Rank 0; Bank 13",
public_description:
None,
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("iMC"),
filter:
None,
extsel:
false,}),
("UNC_C_RxR_IPQ_RETRY2.AD_SBO",
IntelPerformanceCounterDescription{event_code:
Tuple::One(40),
umask:
Tuple::One(1),
event_name:
"UNC_C_RxR_IPQ_RETRY2.AD_SBO",
brief_description:
"Probe Queue Retries; No AD Sbo Credits",
public_description:
Some("Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.; Counts the number of times that a request from the IPQ was retried because of it lacked credits to send an AD packet to the Sbo."),
counter:
Counter::Programmable(15),
counter_ht_off:
Counter::Fixed(0),
pebs_counters:
None,
sample_after_value:
0,
msr_index:
MSRIndex::None,
msr_value:
0,
taken_alone:
false,
counter_mask:
0,
invert:
false,
any_thread:
false,
edge_detect:
false,
pebs:
PebsType::Regular,
precise_store:
false,
data_la:
false,
l1_hit_indication:
false,
errata:
None,
offcore:
false,
unit:
Some("CBO"),
filter:
None,
extsel:
false,})]),}