x86::msr::MSR_EMON_L3_CTR_CTL4

pub const MSR_EMON_L3_CTR_CTL4: u32 = 67536

FSB Event Control and Counter Register (R/W) See Section 18.17, Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte L3 Cache for details.