x86::msr::IA32_X2APIC_TMR5
[−]
[src]
pub const IA32_X2APIC_TMR5: u32=
2077
x2APIC Trigger Mode register bits 191:160
pub const IA32_X2APIC_TMR5: u32=
2077
x2APIC Trigger Mode register bits 191:160