x86
::
msr
Constants
APIC_BASE
BIOS_UPDT_TRIG
DEBUGCTLMSR
EBL_CR_POWERON
IA32_APERF
IA32_APIC_BASE
IA32_A_PMC0
IA32_A_PMC1
IA32_A_PMC2
IA32_A_PMC3
IA32_A_PMC4
IA32_A_PMC5
IA32_A_PMC6
IA32_A_PMC7
IA32_BIOS_SIGN_ID
IA32_BIOS_UPDT_TRIG
IA32_CLOCK_MODULATION
IA32_CPU_DCA_CAP
IA32_DCA_0_CAP
IA32_DEBUGCTL
IA32_DS_AREA
IA32_EFER
IA32_ENERGY_PERF_BIAS
IA32_FEATURE_CONTROL
IA32_FIXED_CTR0
IA32_FIXED_CTR1
IA32_FIXED_CTR2
IA32_FIXED_CTR_CTRL
IA32_FMASK
IA32_FS_BASE
IA32_GS_BASE
IA32_KERNEL_GSBASE
IA32_KERNEL_GS_BASE
IA32_LSTAR
IA32_MC0_ADDR
IA32_MC0_ADDR1
IA32_MC0_CTL
IA32_MC0_CTL2
IA32_MC0_MISC
IA32_MC0_STATUS
IA32_MC10_ADDR1
IA32_MC10_CTL
IA32_MC10_CTL2
IA32_MC10_MISC
IA32_MC10_STATUS
IA32_MC11_ADDR1
IA32_MC11_CTL
IA32_MC11_CTL2
IA32_MC11_MISC
IA32_MC11_STATUS
IA32_MC12_ADDR1
IA32_MC12_CTL
IA32_MC12_CTL2
IA32_MC12_MISC
IA32_MC12_STATUS
IA32_MC13_ADDR1
IA32_MC13_CTL
IA32_MC13_CTL2
IA32_MC13_MISC
IA32_MC13_STATUS
IA32_MC14_ADDR1
IA32_MC14_CTL
IA32_MC14_CTL2
IA32_MC14_MISC
IA32_MC14_STATUS
IA32_MC15_ADDR1
IA32_MC15_CTL
IA32_MC15_CTL2
IA32_MC15_MISC
IA32_MC15_STATUS
IA32_MC16_ADDR1
IA32_MC16_CTL
IA32_MC16_CTL2
IA32_MC16_MISC
IA32_MC16_STATUS
IA32_MC17_ADDR1
IA32_MC17_CTL
IA32_MC17_CTL2
IA32_MC17_MISC
IA32_MC17_STATUS
IA32_MC18_ADDR1
IA32_MC18_CTL
IA32_MC18_CTL2
IA32_MC18_MISC
IA32_MC18_STATUS
IA32_MC19_ADDR1
IA32_MC19_CTL
IA32_MC19_CTL2
IA32_MC19_MISC
IA32_MC19_STATUS
IA32_MC1_ADDR
IA32_MC1_ADDR2
IA32_MC1_CTL
IA32_MC1_CTL2
IA32_MC1_MISC
IA32_MC1_STATUS
IA32_MC20_ADDR1
IA32_MC20_CTL
IA32_MC20_CTL2
IA32_MC20_MISC
IA32_MC20_STATUS
IA32_MC21_ADDR1
IA32_MC21_CTL
IA32_MC21_CTL2
IA32_MC21_MISC
IA32_MC21_STATUS
IA32_MC2_ADDR
IA32_MC2_ADDR1
IA32_MC2_CTL
IA32_MC2_CTL2
IA32_MC2_MISC
IA32_MC2_STATUS
IA32_MC3_ADDR
IA32_MC3_ADDR1
IA32_MC3_CTL
IA32_MC3_CTL2
IA32_MC3_MISC
IA32_MC3_STATUS
IA32_MC4_ADDR
IA32_MC4_ADDR1
IA32_MC4_CTL
IA32_MC4_CTL2
IA32_MC4_MISC
IA32_MC4_STATUS
IA32_MC5_ADDR1
IA32_MC5_CTL
IA32_MC5_CTL2
IA32_MC5_MISC
IA32_MC5_STATUS
IA32_MC6_ADDR1
IA32_MC6_CTL
IA32_MC6_CTL2
IA32_MC6_MISC
IA32_MC6_STATUS
IA32_MC7_ADDR1
IA32_MC7_CTL
IA32_MC7_CTL2
IA32_MC7_MISC
IA32_MC7_STATUS
IA32_MC8_ADDR1
IA32_MC8_CTL
IA32_MC8_CTL2
IA32_MC8_MISC
IA32_MC8_STATUS
IA32_MC9_ADDR1
IA32_MC9_CTL
IA32_MC9_CTL2
IA32_MC9_MISC
IA32_MC9_STATUS
IA32_MCG_CAP
IA32_MCG_CTL
IA32_MCG_STATUS
IA32_MISC_ENABLE
IA32_MONITOR_FILTER_LINE_SIZE
IA32_MONITOR_FILTER_SIZE
IA32_MPERF
IA32_MTRRCAP
IA32_MTRR_DEF_TYPE
IA32_MTRR_FIX16K_80000
IA32_MTRR_FIX16K_A0000
IA32_MTRR_FIX4K_C0000
IA32_MTRR_FIX4K_C8000
IA32_MTRR_FIX4K_D0000
IA32_MTRR_FIX4K_D8000
IA32_MTRR_FIX4K_E0000
IA32_MTRR_FIX4K_E8000
IA32_MTRR_FIX4K_F0000
IA32_MTRR_FIX4K_F8000
IA32_MTRR_FIX64K_00000
IA32_MTRR_PHYSBASE0
IA32_MTRR_PHYSBASE1
IA32_MTRR_PHYSBASE2
IA32_MTRR_PHYSBASE3
IA32_MTRR_PHYSBASE4
IA32_MTRR_PHYSBASE5
IA32_MTRR_PHYSBASE6
IA32_MTRR_PHYSBASE7
IA32_MTRR_PHYSBASE8
IA32_MTRR_PHYSBASE9
IA32_MTRR_PHYSMASK0
IA32_MTRR_PHYSMASK1
IA32_MTRR_PHYSMASK2
IA32_MTRR_PHYSMASK3
IA32_MTRR_PHYSMASK4
IA32_MTRR_PHYSMASK5
IA32_MTRR_PHYSMASK6
IA32_MTRR_PHYSMASK7
IA32_MTRR_PHYSMASK8
IA32_MTRR_PHYSMASK9
IA32_P5_MC_ADDR
IA32_P5_MC_TYPE
IA32_PACKAGE_THERM_INTERRUPT
IA32_PACKAGE_THERM_STATUS
IA32_PAT
IA32_PEBS_ENABLE
IA32_PERFEVTSEL0
IA32_PERFEVTSEL1
IA32_PERFEVTSEL2
IA32_PERFEVTSEL3
IA32_PERFEVTSEL4
IA32_PERFEVTSEL5
IA32_PERFEVTSEL6
IA32_PERFEVTSEL7
IA32_PERF_CAPABILITIES
IA32_PERF_CTL
IA32_PERF_GLOBAL_CTRL
IA32_PERF_GLOBAL_OVF_CTRL
IA32_PERF_GLOBAL_STAUS
IA32_PERF_STATUS
IA32_PLATFORM_DCA_CAP
IA32_PLATFORM_ID
IA32_PMC0
IA32_PMC1
IA32_PMC2
IA32_PMC3
IA32_PMC4
IA32_PMC5
IA32_PMC6
IA32_PMC7
IA32_PQR_ASSOC
IA32_QM_CTR
IA32_QM_EVTSEL
IA32_SMBASE
IA32_SMM_MONITOR_CTL
IA32_SMRR_PHYSBASE
IA32_SMRR_PHYSMASK
IA32_STAR
IA32_SYSENTER_CS
IA32_SYSENTER_EIP
IA32_SYSENTER_ESP
IA32_THERM_INTERRUPT
IA32_THERM_STATUS
IA32_TIME_STAMP_COUNTER
IA32_TSC_ADJUST
IA32_TSC_AUX
IA32_TSC_DEADLINE
IA32_VMX_BASIC
IA32_VMX_CR0_FIXED0
IA32_VMX_CR0_FIXED1
IA32_VMX_CR4_FIXED0
IA32_VMX_CR4_FIXED1
IA32_VMX_CRO_FIXED0
IA32_VMX_CRO_FIXED1
IA32_VMX_ENTRY_CTLS
IA32_VMX_EPT_VPID_CAP
IA32_VMX_EPT_VPID_ENUM
IA32_VMX_EXIT_CTLS
IA32_VMX_FMFUNC
IA32_VMX_MISC
IA32_VMX_PINBASED_CTLS
IA32_VMX_PROCBASED_CTLS
IA32_VMX_PROCBASED_CTLS2
IA32_VMX_TRUE_ENTRY_CTLS
IA32_VMX_TRUE_EXIT_CTLS
IA32_VMX_TRUE_PINBASED_CTLS
IA32_VMX_TRUE_PROCBASED_CTLS
IA32_VMX_VMCS_ENUM
IA32_VMX_VMFUNC
IA32_X2APIC_APICID
IA32_X2APIC_CUR_COUNT
IA32_X2APIC_DIV_CONF
IA32_X2APIC_EOI
IA32_X2APIC_ESR
IA32_X2APIC_ICR
IA32_X2APIC_INIT_COUNT
IA32_X2APIC_IRR0
IA32_X2APIC_IRR1
IA32_X2APIC_IRR2
IA32_X2APIC_IRR3
IA32_X2APIC_IRR4
IA32_X2APIC_IRR5
IA32_X2APIC_IRR6
IA32_X2APIC_IRR7
IA32_X2APIC_ISR0
IA32_X2APIC_ISR1
IA32_X2APIC_ISR2
IA32_X2APIC_ISR3
IA32_X2APIC_ISR4
IA32_X2APIC_ISR5
IA32_X2APIC_ISR6
IA32_X2APIC_ISR7
IA32_X2APIC_LDR
IA32_X2APIC_LVT_CMCI
IA32_X2APIC_LVT_ERROR
IA32_X2APIC_LVT_LINT0
IA32_X2APIC_LVT_LINT1
IA32_X2APIC_LVT_PMI
IA32_X2APIC_LVT_THERMAL
IA32_X2APIC_LVT_TIMER
IA32_X2APIC_PPR
IA32_X2APIC_SELF_IPI
IA32_X2APIC_SIVR
IA32_X2APIC_TMR0
IA32_X2APIC_TMR1
IA32_X2APIC_TMR2
IA32_X2APIC_TMR3
IA32_X2APIC_TMR4
IA32_X2APIC_TMR5
IA32_X2APIC_TMR6
IA32_X2APIC_TMR7
IA32_X2APIC_TPR
IA32_X2APIC_VERSION
LASTBRANCHFROMIP
LASTBRANCHTOIP
LASTINTFROMIP
LASTINTTOIP
MC0_ADDR
MC0_CTL
MC0_MISC
MC0_STATUS
MC1_ADDR
MC1_CTL
MC1_MISC
MC1_STATUS
MC2_ADDR
MC2_CTL
MC2_MISC
MC2_STATUS
MC3_ADDR
MC3_CTL
MC3_MISC
MC3_STATUS
MC4_ADDR
MC4_CTL
MC4_MISC
MC4_STATUS
MCG_CAP
MCG_CTL
MCG_STATUS
MSR_ALF_ESCR0
MSR_ALF_ESCR1
MSR_B0_PMON_BOX_CTRL
MSR_B0_PMON_BOX_OVF_CTRL
MSR_B0_PMON_BOX_STATUS
MSR_B0_PMON_CTR0
MSR_B0_PMON_CTR1
MSR_B0_PMON_CTR2
MSR_B0_PMON_CTR3
MSR_B0_PMON_EVNT_SEL0
MSR_B0_PMON_EVNT_SEL1
MSR_B0_PMON_EVNT_SEL2
MSR_B0_PMON_EVNT_SEL3
MSR_B0_PMON_MASK
MSR_B0_PMON_MATCH
MSR_B1_PMON_BOX_CTRL
MSR_B1_PMON_BOX_OVF_CTRL
MSR_B1_PMON_BOX_STATUS
MSR_B1_PMON_CTR0
MSR_B1_PMON_CTR1
MSR_B1_PMON_CTR2
MSR_B1_PMON_CTR3
MSR_B1_PMON_EVNT_SEL0
MSR_B1_PMON_EVNT_SEL1
MSR_B1_PMON_EVNT_SEL2
MSR_B1_PMON_EVNT_SEL3
MSR_B1_PMON_MASK
MSR_B1_PMON_MATCH
MSR_BBL_CR_CTL
MSR_BBL_CR_CTL3
MSR_BPU_CCCR0
MSR_BPU_CCCR1
MSR_BPU_CCCR2
MSR_BPU_CCCR3
MSR_BPU_COUNTER0
MSR_BPU_COUNTER1
MSR_BPU_COUNTER2
MSR_BPU_COUNTER3
MSR_BPU_ESCR0
MSR_BPU_ESCR1
MSR_BSU_ESCR0
MSR_BSU_ESCR1
MSR_C0_PMON_BOX_CTRL
MSR_C0_PMON_BOX_OVF_CTRL
MSR_C0_PMON_BOX_STATUS
MSR_C0_PMON_CTR0
MSR_C0_PMON_CTR1
MSR_C0_PMON_CTR2
MSR_C0_PMON_CTR3
MSR_C0_PMON_CTR4
MSR_C0_PMON_CTR5
MSR_C0_PMON_EVNT_SEL0
MSR_C0_PMON_EVNT_SEL1
MSR_C0_PMON_EVNT_SEL2
MSR_C0_PMON_EVNT_SEL3
MSR_C0_PMON_EVNT_SEL4
MSR_C0_PMON_EVNT_SEL5
MSR_C1_PMON_BOX_CTRL
MSR_C1_PMON_BOX_OVF_CTRL
MSR_C1_PMON_BOX_STATUS
MSR_C1_PMON_CTR0
MSR_C1_PMON_CTR1
MSR_C1_PMON_CTR2
MSR_C1_PMON_CTR3
MSR_C1_PMON_CTR4
MSR_C1_PMON_CTR5
MSR_C1_PMON_EVNT_SEL0
MSR_C1_PMON_EVNT_SEL1
MSR_C1_PMON_EVNT_SEL2
MSR_C1_PMON_EVNT_SEL3
MSR_C1_PMON_EVNT_SEL4
MSR_C1_PMON_EVNT_SEL5
MSR_C2_PMON_BOX_CTRL
MSR_C2_PMON_BOX_OVF_CTRL
MSR_C2_PMON_BOX_STATUS
MSR_C2_PMON_CTR0
MSR_C2_PMON_CTR1
MSR_C2_PMON_CTR2
MSR_C2_PMON_CTR3
MSR_C2_PMON_CTR4
MSR_C2_PMON_CTR5
MSR_C2_PMON_EVNT_SEL0
MSR_C2_PMON_EVNT_SEL1
MSR_C2_PMON_EVNT_SEL2
MSR_C2_PMON_EVNT_SEL3
MSR_C2_PMON_EVNT_SEL4
MSR_C2_PMON_EVNT_SEL5
MSR_C3_PMON_BOX_CTRL
MSR_C3_PMON_BOX_OVF_CTRL
MSR_C3_PMON_BOX_STATUS
MSR_C3_PMON_CTR0
MSR_C3_PMON_CTR1
MSR_C3_PMON_CTR2
MSR_C3_PMON_CTR3
MSR_C3_PMON_CTR4
MSR_C3_PMON_CTR5
MSR_C3_PMON_EVNT_SEL0
MSR_C3_PMON_EVNT_SEL1
MSR_C3_PMON_EVNT_SEL2
MSR_C3_PMON_EVNT_SEL3
MSR_C3_PMON_EVNT_SEL4
MSR_C3_PMON_EVNT_SEL5
MSR_C4_PMON_BOX_CTRL
MSR_C4_PMON_BOX_OVF_CTRL
MSR_C4_PMON_BOX_STATUS
MSR_C4_PMON_CTR0
MSR_C4_PMON_CTR1
MSR_C4_PMON_CTR2
MSR_C4_PMON_CTR3
MSR_C4_PMON_CTR4
MSR_C4_PMON_CTR5
MSR_C4_PMON_EVNT_SEL0
MSR_C4_PMON_EVNT_SEL1
MSR_C4_PMON_EVNT_SEL2
MSR_C4_PMON_EVNT_SEL3
MSR_C4_PMON_EVNT_SEL4
MSR_C4_PMON_EVNT_SEL5
MSR_C5_PMON_BOX_CTRL
MSR_C5_PMON_BOX_OVF_CTRL
MSR_C5_PMON_BOX_STATUS
MSR_C5_PMON_CTR0
MSR_C5_PMON_CTR1
MSR_C5_PMON_CTR2
MSR_C5_PMON_CTR3
MSR_C5_PMON_CTR4
MSR_C5_PMON_CTR5
MSR_C5_PMON_EVNT_SEL0
MSR_C5_PMON_EVNT_SEL1
MSR_C5_PMON_EVNT_SEL2
MSR_C5_PMON_EVNT_SEL3
MSR_C5_PMON_EVNT_SEL4
MSR_C5_PMON_EVNT_SEL5
MSR_C6_PMON_BOX_CTRL
MSR_C6_PMON_BOX_OVF_CTRL
MSR_C6_PMON_BOX_STATUS
MSR_C6_PMON_CTR0
MSR_C6_PMON_CTR1
MSR_C6_PMON_CTR2
MSR_C6_PMON_CTR3
MSR_C6_PMON_CTR4
MSR_C6_PMON_CTR5
MSR_C6_PMON_EVNT_SEL0
MSR_C6_PMON_EVNT_SEL1
MSR_C6_PMON_EVNT_SEL2
MSR_C6_PMON_EVNT_SEL3
MSR_C6_PMON_EVNT_SEL4
MSR_C6_PMON_EVNT_SEL5
MSR_C7_PMON_BOX_CTRL
MSR_C7_PMON_BOX_OVF_CTRL
MSR_C7_PMON_BOX_STATUS
MSR_C7_PMON_CTR0
MSR_C7_PMON_CTR1
MSR_C7_PMON_CTR2
MSR_C7_PMON_CTR3
MSR_C7_PMON_CTR4
MSR_C7_PMON_CTR5
MSR_C7_PMON_EVNT_SEL0
MSR_C7_PMON_EVNT_SEL1
MSR_C7_PMON_EVNT_SEL2
MSR_C7_PMON_EVNT_SEL3
MSR_C7_PMON_EVNT_SEL4
MSR_C7_PMON_EVNT_SEL5
MSR_C8_PMON_BOX_CTRL
MSR_C8_PMON_BOX_OVF_CTRL
MSR_C8_PMON_BOX_STATUS
MSR_C8_PMON_CTR0
MSR_C8_PMON_CTR1
MSR_C8_PMON_CTR2
MSR_C8_PMON_CTR3
MSR_C8_PMON_CTR4
MSR_C8_PMON_CTR5
MSR_C8_PMON_EVNT_SEL0
MSR_C8_PMON_EVNT_SEL1
MSR_C8_PMON_EVNT_SEL2
MSR_C8_PMON_EVNT_SEL3
MSR_C8_PMON_EVNT_SEL4
MSR_C8_PMON_EVNT_SEL5
MSR_C9_PMON_BOX_CTRL
MSR_C9_PMON_BOX_OVF_CTRL
MSR_C9_PMON_BOX_STATUS
MSR_C9_PMON_CTR0
MSR_C9_PMON_CTR1
MSR_C9_PMON_CTR2
MSR_C9_PMON_CTR3
MSR_C9_PMON_CTR4
MSR_C9_PMON_CTR5
MSR_C9_PMON_EVNT_SEL0
MSR_C9_PMON_EVNT_SEL1
MSR_C9_PMON_EVNT_SEL2
MSR_C9_PMON_EVNT_SEL3
MSR_C9_PMON_EVNT_SEL4
MSR_C9_PMON_EVNT_SEL5
MSR_CONFIG_TDP_CONTROL
MSR_CONFIG_TDP_LEVEL1
MSR_CONFIG_TDP_LEVEL2
MSR_CONFIG_TDP_NOMINAL
MSR_CORE_C1_RESIDENCY
MSR_CORE_C3_RESIDENCY
MSR_CORE_C4_RESIDENCY
MSR_CORE_C6_RESIDENCY
MSR_CORE_C7_RESIDENCY
MSR_CRU_ESCR0
MSR_CRU_ESCR1
MSR_CRU_ESCR2
MSR_CRU_ESCR3
MSR_CRU_ESCR4
MSR_CRU_ESCR5
MSR_DAC_ESCR0
MSR_DAC_ESCR1
MSR_DEBUGCTLA
MSR_DEBUGCTLB
MSR_DRAM_ENERGY_STATUS
MSR_DRAM_PERF_STATUS
MSR_DRAM_POWER_INFO
MSR_DRAM_POWER_LIMIT
MSR_EBC_FREQUENCY_ID
MSR_EBC_HARD_POWERON
MSR_EBC_SOFT_POWERON
MSR_EBL_CR_POWERON
MSR_EFSB_DRDY0
MSR_EFSB_DRDY1
MSR_EMON_L3_CTR_CTL0
MSR_EMON_L3_CTR_CTL1
MSR_EMON_L3_CTR_CTL2
MSR_EMON_L3_CTR_CTL3
MSR_EMON_L3_CTR_CTL4
MSR_EMON_L3_CTR_CTL5
MSR_EMON_L3_CTR_CTL6
MSR_EMON_L3_CTR_CTL7
MSR_EMON_L3_GL_CTL
MSR_ERROR_CONTROL
MSR_FIRM_ESCR0
MSR_FIRM_ESCR1
MSR_FLAME_CCCR0
MSR_FLAME_CCCR1
MSR_FLAME_CCCR2
MSR_FLAME_CCCR3
MSR_FLAME_COUNTER0
MSR_FLAME_COUNTER1
MSR_FLAME_COUNTER2
MSR_FLAME_COUNTER3
MSR_FLAME_ESCR0
MSR_FLAME_ESCR1
MSR_FSB_ESCR0
MSR_FSB_ESCR1
MSR_FSB_FREQ
MSR_GQ_SNOOP_MESF
MSR_IFSB_BUSQ0
MSR_IFSB_BUSQ1
MSR_IFSB_CNTR7
MSR_IFSB_CTL6
MSR_IFSB_SNPQ0
MSR_IFSB_SNPQ1
MSR_IQ_CCCR0
MSR_IQ_CCCR1
MSR_IQ_CCCR2
MSR_IQ_CCCR3
MSR_IQ_CCCR4
MSR_IQ_CCCR5
MSR_IQ_COUNTER4
MSR_IQ_COUNTER5
MSR_IQ_ESCR0
MSR_IQ_ESCR1
MSR_IS_ESCR0
MSR_IS_ESCR1
MSR_ITLB_ESCR0
MSR_ITLB_ESCR1
MSR_IX_ESCR0
MSR_LASTBRANCH_0
MSR_LASTBRANCH_0_FROM_IP
MSR_LASTBRANCH_0_TO_IP
MSR_LASTBRANCH_1
MSR_LASTBRANCH_10_FROM_IP
MSR_LASTBRANCH_10_TO_IP
MSR_LASTBRANCH_11_FROM_IP
MSR_LASTBRANCH_11_TO_IP
MSR_LASTBRANCH_12_FROM_IP
MSR_LASTBRANCH_12_TO_IP
MSR_LASTBRANCH_13_FROM_IP
MSR_LASTBRANCH_13_TO_IP
MSR_LASTBRANCH_14_FROM_IP
MSR_LASTBRANCH_14_TO_IP
MSR_LASTBRANCH_15_FROM_IP
MSR_LASTBRANCH_15_TO_IP
MSR_LASTBRANCH_1_FROM_IP
MSR_LASTBRANCH_1_TO_IP
MSR_LASTBRANCH_2
MSR_LASTBRANCH_2_FROM_IP
MSR_LASTBRANCH_2_TO_IP
MSR_LASTBRANCH_3
MSR_LASTBRANCH_3_FROM_IP
MSR_LASTBRANCH_3_TO_IP
MSR_LASTBRANCH_4
MSR_LASTBRANCH_4_FROM_IP
MSR_LASTBRANCH_4_TO_IP
MSR_LASTBRANCH_5
MSR_LASTBRANCH_5_FROM_IP
MSR_LASTBRANCH_5_TO_IP
MSR_LASTBRANCH_6
MSR_LASTBRANCH_6_FROM_IP
MSR_LASTBRANCH_6_TO_IP
MSR_LASTBRANCH_7
MSR_LASTBRANCH_7_FROM_IP
MSR_LASTBRANCH_7_TO_IP
MSR_LASTBRANCH_8_FROM_IP
MSR_LASTBRANCH_8_TO_IP
MSR_LASTBRANCH_9_FROM_IP
MSR_LASTBRANCH_9_TO_IP
MSR_LASTBRANCH_TOS
MSR_LBR_SELECT
MSR_LER_FROM_LIP
MSR_LER_TO_LIP
MSR_M0_PMON_ADDR_MASK
MSR_M0_PMON_ADDR_MATCH
MSR_M0_PMON_BOX_CTRL
MSR_M0_PMON_BOX_OVF_CTRL
MSR_M0_PMON_BOX_STATUS
MSR_M0_PMON_CTR0
MSR_M0_PMON_CTR1
MSR_M0_PMON_CTR2
MSR_M0_PMON_CTR3
MSR_M0_PMON_CTR4
MSR_M0_PMON_CTR5
MSR_M0_PMON_DSP
MSR_M0_PMON_EVNT_SEL0
MSR_M0_PMON_EVNT_SEL1
MSR_M0_PMON_EVNT_SEL2
MSR_M0_PMON_EVNT_SEL3
MSR_M0_PMON_EVNT_SEL4
MSR_M0_PMON_EVNT_SEL5
MSR_M0_PMON_ISS
MSR_M0_PMON_MAP
MSR_M0_PMON_MM_CONFIG
MSR_M0_PMON_MSC_THR
MSR_M0_PMON_PGT
MSR_M0_PMON_PLD
MSR_M0_PMON_TIMESTAMP
MSR_M0_PMON_ZDP
MSR_M1_PMON_ADDR_MASK
MSR_M1_PMON_ADDR_MATCH
MSR_M1_PMON_BOX_CTRL
MSR_M1_PMON_BOX_OVF_CTRL
MSR_M1_PMON_BOX_STATUS
MSR_M1_PMON_CTR0
MSR_M1_PMON_CTR1
MSR_M1_PMON_CTR2
MSR_M1_PMON_CTR3
MSR_M1_PMON_CTR4
MSR_M1_PMON_CTR5
MSR_M1_PMON_DSP
MSR_M1_PMON_EVNT_SEL0
MSR_M1_PMON_EVNT_SEL1
MSR_M1_PMON_EVNT_SEL2
MSR_M1_PMON_EVNT_SEL3
MSR_M1_PMON_EVNT_SEL4
MSR_M1_PMON_EVNT_SEL5
MSR_M1_PMON_ISS
MSR_M1_PMON_MAP
MSR_M1_PMON_MM_CONFIG
MSR_M1_PMON_MSC_THR
MSR_M1_PMON_PGT
MSR_M1_PMON_PLD
MSR_M1_PMON_TIMESTAMP
MSR_M1_PMON_ZDP
MSR_MC0_MISC
MSR_MC10_ADDR
MSR_MC10_CTL
MSR_MC10_MISC
MSR_MC10_STATUS
MSR_MC11_ADDR
MSR_MC11_CTL
MSR_MC11_MISC
MSR_MC11_STATUS
MSR_MC12_ADDR
MSR_MC12_CTL
MSR_MC12_MISC
MSR_MC12_STATUS
MSR_MC13_ADDR
MSR_MC13_CTL
MSR_MC13_MISC
MSR_MC13_STATUS
MSR_MC14_ADDR
MSR_MC14_CTL
MSR_MC14_MISC
MSR_MC14_STATUS
MSR_MC15_ADDR
MSR_MC15_CTL
MSR_MC15_MISC
MSR_MC15_STATUS
MSR_MC16_ADDR
MSR_MC16_CTL
MSR_MC16_MISC
MSR_MC16_STATUS
MSR_MC17_ADDR
MSR_MC17_CTL
MSR_MC17_MISC
MSR_MC17_STATUS
MSR_MC18_ADDR
MSR_MC18_CTL
MSR_MC18_MISC
MSR_MC18_STATUS
MSR_MC19_ADDR
MSR_MC19_CTL
MSR_MC19_MISC
MSR_MC19_STATUS
MSR_MC1_MISC
MSR_MC20_ADDR
MSR_MC20_CTL
MSR_MC20_MISC
MSR_MC20_STATUS
MSR_MC21_ADDR
MSR_MC21_CTL
MSR_MC21_MISC
MSR_MC21_STATUS
MSR_MC22_ADDR
MSR_MC22_CTL
MSR_MC22_MISC
MSR_MC22_STATUS
MSR_MC23_ADDR
MSR_MC23_CTL
MSR_MC23_MISC
MSR_MC23_STATUS
MSR_MC24_ADDR
MSR_MC24_CTL
MSR_MC24_MISC
MSR_MC24_STATUS
MSR_MC25_ADDR
MSR_MC25_CTL
MSR_MC25_MISC
MSR_MC25_STATUS
MSR_MC26_ADDR
MSR_MC26_CTL
MSR_MC26_MISC
MSR_MC26_STATUS
MSR_MC2_MISC
MSR_MC3_ADDR
MSR_MC3_CTL
MSR_MC3_MISC
MSR_MC3_STATUS
MSR_MC4_ADDR
MSR_MC4_CTL
MSR_MC4_CTL2
MSR_MC4_MISC
MSR_MC4_STATUS
MSR_MC5_ADDR
MSR_MC5_CTL
MSR_MC5_MISC
MSR_MC5_STATUS
MSR_MC6_ADDR
MSR_MC6_CTL
MSR_MC6_MISC
MSR_MC6_STATUS
MSR_MC7_ADDR
MSR_MC7_CTL
MSR_MC7_MISC
MSR_MC7_STATUS
MSR_MC8_ADDR
MSR_MC8_CTL
MSR_MC8_MISC
MSR_MC8_STATUS
MSR_MC9_ADDR
MSR_MC9_CTL
MSR_MC9_MISC
MSR_MC9_STATUS
MSR_MCG_MISC
MSR_MCG_R10
MSR_MCG_R11
MSR_MCG_R12
MSR_MCG_R13
MSR_MCG_R14
MSR_MCG_R8
MSR_MCG_R9
MSR_MCG_RAX
MSR_MCG_RBP
MSR_MCG_RBX
MSR_MCG_RCX
MSR_MCG_RDI
MSR_MCG_RDX
MSR_MCG_RFLAGS
MSR_MCG_RIP
MSR_MCG_RSI
MSR_MISC_PWR_MGMT
MSR_MOB_ESCR0
MSR_MOB_ESCR1
MSR_MS_CCCR0
MSR_MS_CCCR1
MSR_MS_CCCR2
MSR_MS_CCCR3
MSR_MS_COUNTER0
MSR_MS_COUNTER1
MSR_MS_COUNTER2
MSR_MS_COUNTER3
MSR_MS_ESCR0
MSR_MS_ESCR1
MSR_OFFCORE_RSP_0
MSR_OFFCORE_RSP_1
MSR_PEBS_ENABLE
MSR_PEBS_LD_LAT
MSR_PEBS_MATRIX_VERT
MSR_PEBS_NUM_ALT
MSR_PERF_CAPABILITIES
MSR_PERF_FIXED_CTR0
MSR_PERF_FIXED_CTR1
MSR_PERF_FIXED_CTR2
MSR_PERF_FIXED_CTR_CTRL
MSR_PERF_GLOBAL_CTRL
MSR_PERF_GLOBAL_OVF_CTRL
MSR_PERF_GLOBAL_STAUS
MSR_PERF_STATUS
MSR_PKGC3_IRTL
MSR_PKGC6_IRTL
MSR_PKGC7_IRTL
MSR_PKG_C10_RESIDENCY
MSR_PKG_C2_RESIDENCY
MSR_PKG_C3_RESIDENCY
MSR_PKG_C4_RESIDENCY
MSR_PKG_C6C_RESIDENCY
MSR_PKG_C6_RESIDENCY
MSR_PKG_C7_RESIDENCY
MSR_PKG_C9_RESIDENCY
MSR_PKG_CST_CONFIG_CONTROL
MSR_PKG_ENERGY_STATUS
MSR_PKG_PERF_STATUS
MSR_PKG_POWER_INFO
MSR_PKG_POWER_LIMIT
MSR_PLATFORM_BRV
MSR_PLATFORM_ID
MSR_PLATFORM_INFO
MSR_PMG_IO_CAPTURE_BASE
MSR_PMH_ESCR0
MSR_PMH_ESCR1
MSR_POWER_CTL
MSR_PP0_ENERGY_STATUS
MSR_PP0_PERF_STATUS
MSR_PP0_POLICY
MSR_PP0_POWER_LIMIT
MSR_PP1_ENERGY_STATUS
MSR_PP1_POLICY
MSR_PP1_POWER_LIMIT
MSR_R0_PMON_BOX_CTRL
MSR_R0_PMON_BOX_OVF_CTRL
MSR_R0_PMON_BOX_STATUS
MSR_R0_PMON_CTR0
MSR_R0_PMON_CTR1
MSR_R0_PMON_CTR2
MSR_R0_PMON_CTR3
MSR_R0_PMON_CTR4
MSR_R0_PMON_CTR5
MSR_R0_PMON_CTR6
MSR_R0_PMON_CTR7
MSR_R0_PMON_EVNT_SEL0
MSR_R0_PMON_EVNT_SEL1
MSR_R0_PMON_EVNT_SEL2
MSR_R0_PMON_EVNT_SEL3
MSR_R0_PMON_EVNT_SEL4
MSR_R0_PMON_EVNT_SEL5
MSR_R0_PMON_EVNT_SEL6
MSR_R0_PMON_EVNT_SEL7
MSR_R0_PMON_IPERF0_P0
MSR_R0_PMON_IPERF0_P1
MSR_R0_PMON_IPERF0_P2
MSR_R0_PMON_IPERF0_P3
MSR_R0_PMON_IPERF0_P4
MSR_R0_PMON_IPERF0_P5
MSR_R0_PMON_IPERF0_P6
MSR_R0_PMON_IPERF0_P7
MSR_R0_PMON_QLX_P0
MSR_R0_PMON_QLX_P1
MSR_R0_PMON_QLX_P2
MSR_R0_PMON_QLX_P3
MSR_R1_PMON_BOX_CTRL
MSR_R1_PMON_BOX_OVF_CTRL
MSR_R1_PMON_BOX_STATUS
MSR_R1_PMON_CTR10
MSR_R1_PMON_CTR11
MSR_R1_PMON_CTR12
MSR_R1_PMON_CTR13
MSR_R1_PMON_CTR14
MSR_R1_PMON_CTR15
MSR_R1_PMON_CTR8
MSR_R1_PMON_CTR9
MSR_R1_PMON_EVNT_SEL10
MSR_R1_PMON_EVNT_SEL11
MSR_R1_PMON_EVNT_SEL12
MSR_R1_PMON_EVNT_SEL13
MSR_R1_PMON_EVNT_SEL14
MSR_R1_PMON_EVNT_SEL15
MSR_R1_PMON_EVNT_SEL8
MSR_R1_PMON_EVNT_SEL9
MSR_R1_PMON_IPERF1_P10
MSR_R1_PMON_IPERF1_P11
MSR_R1_PMON_IPERF1_P12
MSR_R1_PMON_IPERF1_P13
MSR_R1_PMON_IPERF1_P14
MSR_R1_PMON_IPERF1_P15
MSR_R1_PMON_IPERF1_P8
MSR_R1_PMON_IPERF1_P9
MSR_R1_PMON_QLX_P4
MSR_R1_PMON_QLX_P5
MSR_R1_PMON_QLX_P6
MSR_R1_PMON_QLX_P7
MSR_RAPL_POWER_UNIT
MSR_RAT_ESCR0
MSR_RAT_ESCR1
MSR_S0_PMON_BOX_CTRL
MSR_S0_PMON_BOX_OVF_CTRL
MSR_S0_PMON_BOX_STATUS
MSR_S0_PMON_CTR0
MSR_S0_PMON_CTR1
MSR_S0_PMON_CTR2
MSR_S0_PMON_CTR3
MSR_S0_PMON_EVNT_SEL0
MSR_S0_PMON_EVNT_SEL1
MSR_S0_PMON_EVNT_SEL2
MSR_S0_PMON_EVNT_SEL3
MSR_S0_PMON_MASK
MSR_S0_PMON_MATCH
MSR_S1_PMON_BOX_CTRL
MSR_S1_PMON_BOX_OVF_CTRL
MSR_S1_PMON_BOX_STATUS
MSR_S1_PMON_CTR0
MSR_S1_PMON_CTR1
MSR_S1_PMON_CTR2
MSR_S1_PMON_CTR3
MSR_S1_PMON_EVNT_SEL0
MSR_S1_PMON_EVNT_SEL1
MSR_S1_PMON_EVNT_SEL2
MSR_S1_PMON_EVNT_SEL3
MSR_S1_PMON_MASK
MSR_S1_PMON_MATCH
MSR_SAAT_ESCR0
MSR_SAAT_ESCR1
MSR_SMI_COUNT
MSR_SMM_BLOCKED
MSR_SMM_DELAYED
MSR_SMM_FEATURE_CONTROL
MSR_SMM_MCA_CAP
MSR_SMRR_PHYSMASK
MSR_SSU_ESCR0
MSR_TBPU_ESCR0
MSR_TBPU_ESCR1
MSR_TC_ESCR0
MSR_TC_ESCR1
MSR_TEMPERATURE_TARGET
MSR_THERM2_CTL
MSR_TURBO_ACTIVATION_RATIO
MSR_TURBO_POWER_CURRENT_LIMIT
MSR_TURBO_RATIO_LIMIT
MSR_U2L_ESCR0
MSR_U2L_ESCR1
MSR_UNCORE_ADDR_OPCODE_MATCH
MSR_UNCORE_FIXED_CTR0
MSR_UNCORE_FIXED_CTR_CTRL
MSR_UNCORE_PERFEVTSEL0
MSR_UNCORE_PERFEVTSEL1
MSR_UNCORE_PERFEVTSEL2
MSR_UNCORE_PERFEVTSEL3
MSR_UNCORE_PERFEVTSEL4
MSR_UNCORE_PERFEVTSEL5
MSR_UNCORE_PERFEVTSEL6
MSR_UNCORE_PERFEVTSEL7
MSR_UNCORE_PERF_GLOBAL_CTRL
MSR_UNCORE_PERF_GLOBAL_OVF_CTRL
MSR_UNCORE_PERF_GLOBAL_STATUS
MSR_UNCORE_PMC0
MSR_UNCORE_PMC1
MSR_UNCORE_PMC2
MSR_UNCORE_PMC3
MSR_UNCORE_PMC4
MSR_UNCORE_PMC5
MSR_UNCORE_PMC6
MSR_UNCORE_PMC7
MSR_UNC_ARB_PERFEVTSEL0
MSR_UNC_ARB_PERFEVTSEL1
MSR_UNC_ARB_PER_CTR0
MSR_UNC_ARB_PER_CTR1
MSR_UNC_CBO_0_PERFEVTSEL0
MSR_UNC_CBO_0_PERFEVTSEL1
MSR_UNC_CBO_0_PER_CTR0
MSR_UNC_CBO_0_PER_CTR1
MSR_UNC_CBO_1_PERFEVTSEL0
MSR_UNC_CBO_1_PERFEVTSEL1
MSR_UNC_CBO_1_PER_CTR0
MSR_UNC_CBO_1_PER_CTR1
MSR_UNC_CBO_2_PERFEVTSEL0
MSR_UNC_CBO_2_PERFEVTSEL1
MSR_UNC_CBO_2_PER_CTR0
MSR_UNC_CBO_2_PER_CTR1
MSR_UNC_CBO_3_PERFEVTSEL0
MSR_UNC_CBO_3_PERFEVTSEL1
MSR_UNC_CBO_3_PER_CTR0
MSR_UNC_CBO_3_PER_CTR1
MSR_UNC_CBO_CONFIG
MSR_UNC_PERF_FIXED_CTR
MSR_UNC_PERF_FIXED_CTRL
MSR_UNC_PERF_GLOBAL_CTRL
MSR_UNC_PERF_GLOBAL_STATUS
MSR_U_PMON_CTR
MSR_U_PMON_EVNT_SEL
MSR_U_PMON_GLOBAL_CTRL
MSR_U_PMON_GLOBAL_OVF_CTRL
MSR_U_PMON_GLOBAL_STATUS
MSR_W_PMON_BOX_CTRL
MSR_W_PMON_BOX_OVF_CTRL
MSR_W_PMON_BOX_STATUS
MSR_W_PMON_CTR0
MSR_W_PMON_CTR1
MSR_W_PMON_CTR2
MSR_W_PMON_CTR3
MSR_W_PMON_EVNT_SEL0
MSR_W_PMON_EVNT_SEL1
MSR_W_PMON_EVNT_SEL2
MSR_W_PMON_EVNT_SEL3
MSR_W_PMON_FIXED_CTR
MSR_W_PMON_FIXED_CTR_CTL
P5_MC_ADDR
P5_MC_TYPE
ROB_CR_BKUPTMPDR6
SYSENTER_CS_MSR
SYSENTER_EIP_MSR
SYSENTER_ESP_MSR
TEST_CTL
TSC
Functions
rdmsr
wrmsr
x86
::
msr
::
IA32_MC7_MISC
[
−
]
[src]
pub const IA32_MC7_MISC: u32
=
1055
[
−
]
Expand description
06_1AH